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MachineInstr.h
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00001 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the declaration of the MachineInstr class, which is the
00011 // basic representation for all target dependent machine instructions used by
00012 // the back end.
00013 //
00014 //===----------------------------------------------------------------------===//
00015 
00016 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
00017 #define LLVM_CODEGEN_MACHINEINSTR_H
00018 
00019 #include "llvm/ADT/ArrayRef.h"
00020 #include "llvm/ADT/DenseMapInfo.h"
00021 #include "llvm/ADT/STLExtras.h"
00022 #include "llvm/ADT/StringRef.h"
00023 #include "llvm/ADT/ilist.h"
00024 #include "llvm/ADT/ilist_node.h"
00025 #include "llvm/ADT/iterator_range.h"
00026 #include "llvm/CodeGen/MachineOperand.h"
00027 #include "llvm/IR/DebugInfo.h"
00028 #include "llvm/IR/DebugLoc.h"
00029 #include "llvm/IR/InlineAsm.h"
00030 #include "llvm/MC/MCInstrDesc.h"
00031 #include "llvm/Support/ArrayRecycler.h"
00032 #include "llvm/Target/TargetOpcodes.h"
00033 
00034 namespace llvm {
00035 
00036 template <typename T> class SmallVectorImpl;
00037 class AliasAnalysis;
00038 class TargetInstrInfo;
00039 class TargetRegisterClass;
00040 class TargetRegisterInfo;
00041 class MachineFunction;
00042 class MachineMemOperand;
00043 
00044 //===----------------------------------------------------------------------===//
00045 /// MachineInstr - Representation of each machine instruction.
00046 ///
00047 /// This class isn't a POD type, but it must have a trivial destructor. When a
00048 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
00049 /// without having their destructor called.
00050 ///
00051 class MachineInstr : public ilist_node<MachineInstr> {
00052 public:
00053   typedef MachineMemOperand **mmo_iterator;
00054 
00055   /// Flags to specify different kinds of comments to output in
00056   /// assembly code.  These flags carry semantic information not
00057   /// otherwise easily derivable from the IR text.
00058   ///
00059   enum CommentFlag {
00060     ReloadReuse = 0x1
00061   };
00062 
00063   enum MIFlag {
00064     NoFlags      = 0,
00065     FrameSetup   = 1 << 0,              // Instruction is used as a part of
00066                                         // function frame setup code.
00067     BundledPred  = 1 << 1,              // Instruction has bundled predecessors.
00068     BundledSucc  = 1 << 2               // Instruction has bundled successors.
00069   };
00070 private:
00071   const MCInstrDesc *MCID;              // Instruction descriptor.
00072   MachineBasicBlock *Parent;            // Pointer to the owning basic block.
00073 
00074   // Operands are allocated by an ArrayRecycler.
00075   MachineOperand *Operands;             // Pointer to the first operand.
00076   unsigned NumOperands;                 // Number of operands on instruction.
00077   typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
00078   OperandCapacity CapOperands;          // Capacity of the Operands array.
00079 
00080   uint8_t Flags;                        // Various bits of additional
00081                                         // information about machine
00082                                         // instruction.
00083 
00084   uint8_t AsmPrinterFlags;              // Various bits of information used by
00085                                         // the AsmPrinter to emit helpful
00086                                         // comments.  This is *not* semantic
00087                                         // information.  Do not use this for
00088                                         // anything other than to convey comment
00089                                         // information to AsmPrinter.
00090 
00091   uint8_t NumMemRefs;                   // Information on memory references.
00092   mmo_iterator MemRefs;
00093 
00094   DebugLoc debugLoc;                    // Source line information.
00095 
00096   MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
00097   void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
00098   // Use MachineFunction::DeleteMachineInstr() instead.
00099   ~MachineInstr() LLVM_DELETED_FUNCTION;
00100 
00101   // Intrusive list support
00102   friend struct ilist_traits<MachineInstr>;
00103   friend struct ilist_traits<MachineBasicBlock>;
00104   void setParent(MachineBasicBlock *P) { Parent = P; }
00105 
00106   /// MachineInstr ctor - This constructor creates a copy of the given
00107   /// MachineInstr in the given MachineFunction.
00108   MachineInstr(MachineFunction &, const MachineInstr &);
00109 
00110   /// MachineInstr ctor - This constructor create a MachineInstr and add the
00111   /// implicit operands.  It reserves space for number of operands specified by
00112   /// MCInstrDesc.  An explicit DebugLoc is supplied.
00113   MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
00114                const DebugLoc dl, bool NoImp = false);
00115 
00116   // MachineInstrs are pool-allocated and owned by MachineFunction.
00117   friend class MachineFunction;
00118 
00119 public:
00120   const MachineBasicBlock* getParent() const { return Parent; }
00121   MachineBasicBlock* getParent() { return Parent; }
00122 
00123   /// getAsmPrinterFlags - Return the asm printer flags bitvector.
00124   ///
00125   uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
00126 
00127   /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
00128   ///
00129   void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
00130 
00131   /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
00132   ///
00133   bool getAsmPrinterFlag(CommentFlag Flag) const {
00134     return AsmPrinterFlags & Flag;
00135   }
00136 
00137   /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
00138   ///
00139   void setAsmPrinterFlag(CommentFlag Flag) {
00140     AsmPrinterFlags |= (uint8_t)Flag;
00141   }
00142 
00143   /// clearAsmPrinterFlag - clear specific AsmPrinter flags
00144   ///
00145   void clearAsmPrinterFlag(CommentFlag Flag) {
00146     AsmPrinterFlags &= ~Flag;
00147   }
00148 
00149   /// getFlags - Return the MI flags bitvector.
00150   uint8_t getFlags() const {
00151     return Flags;
00152   }
00153 
00154   /// getFlag - Return whether an MI flag is set.
00155   bool getFlag(MIFlag Flag) const {
00156     return Flags & Flag;
00157   }
00158 
00159   /// setFlag - Set a MI flag.
00160   void setFlag(MIFlag Flag) {
00161     Flags |= (uint8_t)Flag;
00162   }
00163 
00164   void setFlags(unsigned flags) {
00165     // Filter out the automatically maintained flags.
00166     unsigned Mask = BundledPred | BundledSucc;
00167     Flags = (Flags & Mask) | (flags & ~Mask);
00168   }
00169 
00170   /// clearFlag - Clear a MI flag.
00171   void clearFlag(MIFlag Flag) {
00172     Flags &= ~((uint8_t)Flag);
00173   }
00174 
00175   /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
00176   /// in a bundle).
00177   ///
00178   /// A bundle looks like this before it's finalized:
00179   ///   ----------------
00180   ///   |      MI      |
00181   ///   ----------------
00182   ///          |
00183   ///   ----------------
00184   ///   |      MI    * |
00185   ///   ----------------
00186   ///          |
00187   ///   ----------------
00188   ///   |      MI    * |
00189   ///   ----------------
00190   /// In this case, the first MI starts a bundle but is not inside a bundle, the
00191   /// next 2 MIs are considered "inside" the bundle.
00192   ///
00193   /// After a bundle is finalized, it looks like this:
00194   ///   ----------------
00195   ///   |    Bundle    |
00196   ///   ----------------
00197   ///          |
00198   ///   ----------------
00199   ///   |      MI    * |
00200   ///   ----------------
00201   ///          |
00202   ///   ----------------
00203   ///   |      MI    * |
00204   ///   ----------------
00205   ///          |
00206   ///   ----------------
00207   ///   |      MI    * |
00208   ///   ----------------
00209   /// The first instruction has the special opcode "BUNDLE". It's not "inside"
00210   /// a bundle, but the next three MIs are.
00211   bool isInsideBundle() const {
00212     return getFlag(BundledPred);
00213   }
00214 
00215   /// isBundled - Return true if this instruction part of a bundle. This is true
00216   /// if either itself or its following instruction is marked "InsideBundle".
00217   bool isBundled() const {
00218     return isBundledWithPred() || isBundledWithSucc();
00219   }
00220 
00221   /// Return true if this instruction is part of a bundle, and it is not the
00222   /// first instruction in the bundle.
00223   bool isBundledWithPred() const { return getFlag(BundledPred); }
00224 
00225   /// Return true if this instruction is part of a bundle, and it is not the
00226   /// last instruction in the bundle.
00227   bool isBundledWithSucc() const { return getFlag(BundledSucc); }
00228 
00229   /// Bundle this instruction with its predecessor. This can be an unbundled
00230   /// instruction, or it can be the first instruction in a bundle.
00231   void bundleWithPred();
00232 
00233   /// Bundle this instruction with its successor. This can be an unbundled
00234   /// instruction, or it can be the last instruction in a bundle.
00235   void bundleWithSucc();
00236 
00237   /// Break bundle above this instruction.
00238   void unbundleFromPred();
00239 
00240   /// Break bundle below this instruction.
00241   void unbundleFromSucc();
00242 
00243   /// getDebugLoc - Returns the debug location id of this MachineInstr.
00244   ///
00245   DebugLoc getDebugLoc() const { return debugLoc; }
00246 
00247   /// getDebugVariable() - Return the debug variable referenced by
00248   /// this DBG_VALUE instruction.
00249   DIVariable getDebugVariable() const {
00250     assert(isDebugValue() && "not a DBG_VALUE");
00251     const MDNode *Var = getOperand(getNumOperands() - 1).getMetadata();
00252     return DIVariable(Var);
00253   }
00254 
00255   /// emitError - Emit an error referring to the source location of this
00256   /// instruction. This should only be used for inline assembly that is somehow
00257   /// impossible to compile. Other errors should have been handled much
00258   /// earlier.
00259   ///
00260   /// If this method returns, the caller should try to recover from the error.
00261   ///
00262   void emitError(StringRef Msg) const;
00263 
00264   /// getDesc - Returns the target instruction descriptor of this
00265   /// MachineInstr.
00266   const MCInstrDesc &getDesc() const { return *MCID; }
00267 
00268   /// getOpcode - Returns the opcode of this MachineInstr.
00269   ///
00270   int getOpcode() const { return MCID->Opcode; }
00271 
00272   /// Access to explicit operands of the instruction.
00273   ///
00274   unsigned getNumOperands() const { return NumOperands; }
00275 
00276   const MachineOperand& getOperand(unsigned i) const {
00277     assert(i < getNumOperands() && "getOperand() out of range!");
00278     return Operands[i];
00279   }
00280   MachineOperand& getOperand(unsigned i) {
00281     assert(i < getNumOperands() && "getOperand() out of range!");
00282     return Operands[i];
00283   }
00284 
00285   /// getNumExplicitOperands - Returns the number of non-implicit operands.
00286   ///
00287   unsigned getNumExplicitOperands() const;
00288 
00289   /// iterator/begin/end - Iterate over all operands of a machine instruction.
00290   typedef MachineOperand *mop_iterator;
00291   typedef const MachineOperand *const_mop_iterator;
00292 
00293   mop_iterator operands_begin() { return Operands; }
00294   mop_iterator operands_end() { return Operands + NumOperands; }
00295 
00296   const_mop_iterator operands_begin() const { return Operands; }
00297   const_mop_iterator operands_end() const { return Operands + NumOperands; }
00298 
00299   iterator_range<mop_iterator> operands() {
00300     return iterator_range<mop_iterator>(operands_begin(), operands_end());
00301   }
00302   iterator_range<const_mop_iterator> operands() const {
00303     return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
00304   }
00305   iterator_range<mop_iterator> explicit_operands() {
00306     return iterator_range<mop_iterator>(
00307         operands_begin(), operands_begin() + getNumExplicitOperands());
00308   }
00309   iterator_range<const_mop_iterator> explicit_operands() const {
00310     return iterator_range<const_mop_iterator>(
00311         operands_begin(), operands_begin() + getNumExplicitOperands());
00312   }
00313   iterator_range<mop_iterator> implicit_operands() {
00314     return iterator_range<mop_iterator>(explicit_operands().end(),
00315                                         operands_end());
00316   }
00317   iterator_range<const_mop_iterator> implicit_operands() const {
00318     return iterator_range<const_mop_iterator>(explicit_operands().end(),
00319                                               operands_end());
00320   }
00321   iterator_range<mop_iterator> defs() {
00322     return iterator_range<mop_iterator>(
00323         operands_begin(), operands_begin() + getDesc().getNumDefs());
00324   }
00325   iterator_range<const_mop_iterator> defs() const {
00326     return iterator_range<const_mop_iterator>(
00327         operands_begin(), operands_begin() + getDesc().getNumDefs());
00328   }
00329   iterator_range<mop_iterator> uses() {
00330     return iterator_range<mop_iterator>(
00331         operands_begin() + getDesc().getNumDefs(), operands_end());
00332   }
00333   iterator_range<const_mop_iterator> uses() const {
00334     return iterator_range<const_mop_iterator>(
00335         operands_begin() + getDesc().getNumDefs(), operands_end());
00336   }
00337 
00338   /// Access to memory operands of the instruction
00339   mmo_iterator memoperands_begin() const { return MemRefs; }
00340   mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
00341   bool memoperands_empty() const { return NumMemRefs == 0; }
00342 
00343   iterator_range<mmo_iterator>  memoperands() {
00344     return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
00345   }
00346   iterator_range<mmo_iterator> memoperands() const {
00347     return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
00348   }
00349 
00350   /// hasOneMemOperand - Return true if this instruction has exactly one
00351   /// MachineMemOperand.
00352   bool hasOneMemOperand() const {
00353     return NumMemRefs == 1;
00354   }
00355 
00356   /// API for querying MachineInstr properties. They are the same as MCInstrDesc
00357   /// queries but they are bundle aware.
00358 
00359   enum QueryType {
00360     IgnoreBundle,    // Ignore bundles
00361     AnyInBundle,     // Return true if any instruction in bundle has property
00362     AllInBundle      // Return true if all instructions in bundle have property
00363   };
00364 
00365   /// hasProperty - Return true if the instruction (or in the case of a bundle,
00366   /// the instructions inside the bundle) has the specified property.
00367   /// The first argument is the property being queried.
00368   /// The second argument indicates whether the query should look inside
00369   /// instruction bundles.
00370   bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
00371     // Inline the fast path for unbundled or bundle-internal instructions.
00372     if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
00373       return getDesc().getFlags() & (1 << MCFlag);
00374 
00375     // If this is the first instruction in a bundle, take the slow path.
00376     return hasPropertyInBundle(1 << MCFlag, Type);
00377   }
00378 
00379   /// isVariadic - Return true if this instruction can have a variable number of
00380   /// operands.  In this case, the variable operands will be after the normal
00381   /// operands but before the implicit definitions and uses (if any are
00382   /// present).
00383   bool isVariadic(QueryType Type = IgnoreBundle) const {
00384     return hasProperty(MCID::Variadic, Type);
00385   }
00386 
00387   /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
00388   /// ARM instructions which can set condition code if 's' bit is set.
00389   bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
00390     return hasProperty(MCID::HasOptionalDef, Type);
00391   }
00392 
00393   /// isPseudo - Return true if this is a pseudo instruction that doesn't
00394   /// correspond to a real machine instruction.
00395   ///
00396   bool isPseudo(QueryType Type = IgnoreBundle) const {
00397     return hasProperty(MCID::Pseudo, Type);
00398   }
00399 
00400   bool isReturn(QueryType Type = AnyInBundle) const {
00401     return hasProperty(MCID::Return, Type);
00402   }
00403 
00404   bool isCall(QueryType Type = AnyInBundle) const {
00405     return hasProperty(MCID::Call, Type);
00406   }
00407 
00408   /// isBarrier - Returns true if the specified instruction stops control flow
00409   /// from executing the instruction immediately following it.  Examples include
00410   /// unconditional branches and return instructions.
00411   bool isBarrier(QueryType Type = AnyInBundle) const {
00412     return hasProperty(MCID::Barrier, Type);
00413   }
00414 
00415   /// isTerminator - Returns true if this instruction part of the terminator for
00416   /// a basic block.  Typically this is things like return and branch
00417   /// instructions.
00418   ///
00419   /// Various passes use this to insert code into the bottom of a basic block,
00420   /// but before control flow occurs.
00421   bool isTerminator(QueryType Type = AnyInBundle) const {
00422     return hasProperty(MCID::Terminator, Type);
00423   }
00424 
00425   /// isBranch - Returns true if this is a conditional, unconditional, or
00426   /// indirect branch.  Predicates below can be used to discriminate between
00427   /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
00428   /// get more information.
00429   bool isBranch(QueryType Type = AnyInBundle) const {
00430     return hasProperty(MCID::Branch, Type);
00431   }
00432 
00433   /// isIndirectBranch - Return true if this is an indirect branch, such as a
00434   /// branch through a register.
00435   bool isIndirectBranch(QueryType Type = AnyInBundle) const {
00436     return hasProperty(MCID::IndirectBranch, Type);
00437   }
00438 
00439   /// isConditionalBranch - Return true if this is a branch which may fall
00440   /// through to the next instruction or may transfer control flow to some other
00441   /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
00442   /// information about this branch.
00443   bool isConditionalBranch(QueryType Type = AnyInBundle) const {
00444     return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
00445   }
00446 
00447   /// isUnconditionalBranch - Return true if this is a branch which always
00448   /// transfers control flow to some other block.  The
00449   /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
00450   /// about this branch.
00451   bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
00452     return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
00453   }
00454 
00455   /// Return true if this instruction has a predicate operand that
00456   /// controls execution.  It may be set to 'always', or may be set to other
00457   /// values.   There are various methods in TargetInstrInfo that can be used to
00458   /// control and modify the predicate in this instruction.
00459   bool isPredicable(QueryType Type = AllInBundle) const {
00460     // If it's a bundle than all bundled instructions must be predicable for this
00461     // to return true.
00462     return hasProperty(MCID::Predicable, Type);
00463   }
00464 
00465   /// isCompare - Return true if this instruction is a comparison.
00466   bool isCompare(QueryType Type = IgnoreBundle) const {
00467     return hasProperty(MCID::Compare, Type);
00468   }
00469 
00470   /// isMoveImmediate - Return true if this instruction is a move immediate
00471   /// (including conditional moves) instruction.
00472   bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
00473     return hasProperty(MCID::MoveImm, Type);
00474   }
00475 
00476   /// isBitcast - Return true if this instruction is a bitcast instruction.
00477   ///
00478   bool isBitcast(QueryType Type = IgnoreBundle) const {
00479     return hasProperty(MCID::Bitcast, Type);
00480   }
00481 
00482   /// isSelect - Return true if this instruction is a select instruction.
00483   ///
00484   bool isSelect(QueryType Type = IgnoreBundle) const {
00485     return hasProperty(MCID::Select, Type);
00486   }
00487 
00488   /// isNotDuplicable - Return true if this instruction cannot be safely
00489   /// duplicated.  For example, if the instruction has a unique labels attached
00490   /// to it, duplicating it would cause multiple definition errors.
00491   bool isNotDuplicable(QueryType Type = AnyInBundle) const {
00492     return hasProperty(MCID::NotDuplicable, Type);
00493   }
00494 
00495   /// hasDelaySlot - Returns true if the specified instruction has a delay slot
00496   /// which must be filled by the code generator.
00497   bool hasDelaySlot(QueryType Type = AnyInBundle) const {
00498     return hasProperty(MCID::DelaySlot, Type);
00499   }
00500 
00501   /// canFoldAsLoad - Return true for instructions that can be folded as
00502   /// memory operands in other instructions. The most common use for this
00503   /// is instructions that are simple loads from memory that don't modify
00504   /// the loaded value in any way, but it can also be used for instructions
00505   /// that can be expressed as constant-pool loads, such as V_SETALLONES
00506   /// on x86, to allow them to be folded when it is beneficial.
00507   /// This should only be set on instructions that return a value in their
00508   /// only virtual register definition.
00509   bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
00510     return hasProperty(MCID::FoldableAsLoad, Type);
00511   }
00512 
00513   /// \brief Return true if this instruction behaves
00514   /// the same way as the generic REG_SEQUENCE instructions.
00515   /// E.g., on ARM,
00516   /// dX VMOVDRR rY, rZ
00517   /// is equivalent to
00518   /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
00519   ///
00520   /// Note that for the optimizers to be able to take advantage of
00521   /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
00522   /// override accordingly.
00523   bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
00524     return hasProperty(MCID::RegSequence, Type);
00525   }
00526 
00527   /// \brief Return true if this instruction behaves
00528   /// the same way as the generic EXTRACT_SUBREG instructions.
00529   /// E.g., on ARM,
00530   /// rX, rY VMOVRRD dZ
00531   /// is equivalent to two EXTRACT_SUBREG:
00532   /// rX = EXTRACT_SUBREG dZ, ssub_0
00533   /// rY = EXTRACT_SUBREG dZ, ssub_1
00534   ///
00535   /// Note that for the optimizers to be able to take advantage of
00536   /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
00537   /// override accordingly.
00538   bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
00539     return hasProperty(MCID::ExtractSubreg, Type);
00540   }
00541 
00542   /// \brief Return true if this instruction behaves
00543   /// the same way as the generic INSERT_SUBREG instructions.
00544   /// E.g., on ARM,
00545   /// dX = VSETLNi32 dY, rZ, Imm
00546   /// is equivalent to a INSERT_SUBREG:
00547   /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
00548   ///
00549   /// Note that for the optimizers to be able to take advantage of
00550   /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
00551   /// override accordingly.
00552   bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
00553     return hasProperty(MCID::InsertSubreg, Type);
00554   }
00555 
00556   //===--------------------------------------------------------------------===//
00557   // Side Effect Analysis
00558   //===--------------------------------------------------------------------===//
00559 
00560   /// mayLoad - Return true if this instruction could possibly read memory.
00561   /// Instructions with this flag set are not necessarily simple load
00562   /// instructions, they may load a value and modify it, for example.
00563   bool mayLoad(QueryType Type = AnyInBundle) const {
00564     if (isInlineAsm()) {
00565       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
00566       if (ExtraInfo & InlineAsm::Extra_MayLoad)
00567         return true;
00568     }
00569     return hasProperty(MCID::MayLoad, Type);
00570   }
00571 
00572 
00573   /// mayStore - Return true if this instruction could possibly modify memory.
00574   /// Instructions with this flag set are not necessarily simple store
00575   /// instructions, they may store a modified value based on their operands, or
00576   /// may not actually modify anything, for example.
00577   bool mayStore(QueryType Type = AnyInBundle) const {
00578     if (isInlineAsm()) {
00579       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
00580       if (ExtraInfo & InlineAsm::Extra_MayStore)
00581         return true;
00582     }
00583     return hasProperty(MCID::MayStore, Type);
00584   }
00585 
00586   //===--------------------------------------------------------------------===//
00587   // Flags that indicate whether an instruction can be modified by a method.
00588   //===--------------------------------------------------------------------===//
00589 
00590   /// isCommutable - Return true if this may be a 2- or 3-address
00591   /// instruction (of the form "X = op Y, Z, ..."), which produces the same
00592   /// result if Y and Z are exchanged.  If this flag is set, then the
00593   /// TargetInstrInfo::commuteInstruction method may be used to hack on the
00594   /// instruction.
00595   ///
00596   /// Note that this flag may be set on instructions that are only commutable
00597   /// sometimes.  In these cases, the call to commuteInstruction will fail.
00598   /// Also note that some instructions require non-trivial modification to
00599   /// commute them.
00600   bool isCommutable(QueryType Type = IgnoreBundle) const {
00601     return hasProperty(MCID::Commutable, Type);
00602   }
00603 
00604   /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
00605   /// which can be changed into a 3-address instruction if needed.  Doing this
00606   /// transformation can be profitable in the register allocator, because it
00607   /// means that the instruction can use a 2-address form if possible, but
00608   /// degrade into a less efficient form if the source and dest register cannot
00609   /// be assigned to the same register.  For example, this allows the x86
00610   /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
00611   /// is the same speed as the shift but has bigger code size.
00612   ///
00613   /// If this returns true, then the target must implement the
00614   /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
00615   /// is allowed to fail if the transformation isn't valid for this specific
00616   /// instruction (e.g. shl reg, 4 on x86).
00617   ///
00618   bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
00619     return hasProperty(MCID::ConvertibleTo3Addr, Type);
00620   }
00621 
00622   /// usesCustomInsertionHook - Return true if this instruction requires
00623   /// custom insertion support when the DAG scheduler is inserting it into a
00624   /// machine basic block.  If this is true for the instruction, it basically
00625   /// means that it is a pseudo instruction used at SelectionDAG time that is
00626   /// expanded out into magic code by the target when MachineInstrs are formed.
00627   ///
00628   /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
00629   /// is used to insert this into the MachineBasicBlock.
00630   bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
00631     return hasProperty(MCID::UsesCustomInserter, Type);
00632   }
00633 
00634   /// hasPostISelHook - Return true if this instruction requires *adjustment*
00635   /// after instruction selection by calling a target hook. For example, this
00636   /// can be used to fill in ARM 's' optional operand depending on whether
00637   /// the conditional flag register is used.
00638   bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
00639     return hasProperty(MCID::HasPostISelHook, Type);
00640   }
00641 
00642   /// isRematerializable - Returns true if this instruction is a candidate for
00643   /// remat.  This flag is deprecated, please don't use it anymore.  If this
00644   /// flag is set, the isReallyTriviallyReMaterializable() method is called to
00645   /// verify the instruction is really rematable.
00646   bool isRematerializable(QueryType Type = AllInBundle) const {
00647     // It's only possible to re-mat a bundle if all bundled instructions are
00648     // re-materializable.
00649     return hasProperty(MCID::Rematerializable, Type);
00650   }
00651 
00652   /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
00653   /// less) than a move instruction. This is useful during certain types of
00654   /// optimizations (e.g., remat during two-address conversion or machine licm)
00655   /// where we would like to remat or hoist the instruction, but not if it costs
00656   /// more than moving the instruction into the appropriate register. Note, we
00657   /// are not marking copies from and to the same register class with this flag.
00658   bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
00659     // Only returns true for a bundle if all bundled instructions are cheap.
00660     return hasProperty(MCID::CheapAsAMove, Type);
00661   }
00662 
00663   /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
00664   /// have special register allocation requirements that are not captured by the
00665   /// operand register classes. e.g. ARM::STRD's two source registers must be an
00666   /// even / odd pair, ARM::STM registers have to be in ascending order.
00667   /// Post-register allocation passes should not attempt to change allocations
00668   /// for sources of instructions with this flag.
00669   bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
00670     return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
00671   }
00672 
00673   /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
00674   /// have special register allocation requirements that are not captured by the
00675   /// operand register classes. e.g. ARM::LDRD's two def registers must be an
00676   /// even / odd pair, ARM::LDM registers have to be in ascending order.
00677   /// Post-register allocation passes should not attempt to change allocations
00678   /// for definitions of instructions with this flag.
00679   bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
00680     return hasProperty(MCID::ExtraDefRegAllocReq, Type);
00681   }
00682 
00683 
00684   enum MICheckType {
00685     CheckDefs,      // Check all operands for equality
00686     CheckKillDead,  // Check all operands including kill / dead markers
00687     IgnoreDefs,     // Ignore all definitions
00688     IgnoreVRegDefs  // Ignore virtual register definitions
00689   };
00690 
00691   /// isIdenticalTo - Return true if this instruction is identical to (same
00692   /// opcode and same operands as) the specified instruction.
00693   bool isIdenticalTo(const MachineInstr *Other,
00694                      MICheckType Check = CheckDefs) const;
00695 
00696   /// Unlink 'this' from the containing basic block, and return it without
00697   /// deleting it.
00698   ///
00699   /// This function can not be used on bundled instructions, use
00700   /// removeFromBundle() to remove individual instructions from a bundle.
00701   MachineInstr *removeFromParent();
00702 
00703   /// Unlink this instruction from its basic block and return it without
00704   /// deleting it.
00705   ///
00706   /// If the instruction is part of a bundle, the other instructions in the
00707   /// bundle remain bundled.
00708   MachineInstr *removeFromBundle();
00709 
00710   /// Unlink 'this' from the containing basic block and delete it.
00711   ///
00712   /// If this instruction is the header of a bundle, the whole bundle is erased.
00713   /// This function can not be used for instructions inside a bundle, use
00714   /// eraseFromBundle() to erase individual bundled instructions.
00715   void eraseFromParent();
00716 
00717   /// Unlink 'this' from the containing basic block and delete it.
00718   ///
00719   /// For all definitions mark their uses in DBG_VALUE nodes
00720   /// as undefined. Otherwise like eraseFromParent().
00721   void eraseFromParentAndMarkDBGValuesForRemoval();
00722 
00723   /// Unlink 'this' form its basic block and delete it.
00724   ///
00725   /// If the instruction is part of a bundle, the other instructions in the
00726   /// bundle remain bundled.
00727   void eraseFromBundle();
00728 
00729   bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
00730   bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
00731 
00732   /// isLabel - Returns true if the MachineInstr represents a label.
00733   ///
00734   bool isLabel() const { return isEHLabel() || isGCLabel(); }
00735   bool isCFIInstruction() const {
00736     return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
00737   }
00738 
00739   // True if the instruction represents a position in the function.
00740   bool isPosition() const { return isLabel() || isCFIInstruction(); }
00741 
00742   bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
00743   /// A DBG_VALUE is indirect iff the first operand is a register and
00744   /// the second operand is an immediate.
00745   bool isIndirectDebugValue() const {
00746     return isDebugValue()
00747       && getOperand(0).isReg()
00748       && getOperand(1).isImm();
00749   }
00750 
00751   bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
00752   bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
00753   bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
00754   bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
00755   bool isMSInlineAsm() const { 
00756     return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
00757   }
00758   bool isStackAligningInlineAsm() const;
00759   InlineAsm::AsmDialect getInlineAsmDialect() const;
00760   bool isInsertSubreg() const {
00761     return getOpcode() == TargetOpcode::INSERT_SUBREG;
00762   }
00763   bool isSubregToReg() const {
00764     return getOpcode() == TargetOpcode::SUBREG_TO_REG;
00765   }
00766   bool isRegSequence() const {
00767     return getOpcode() == TargetOpcode::REG_SEQUENCE;
00768   }
00769   bool isBundle() const {
00770     return getOpcode() == TargetOpcode::BUNDLE;
00771   }
00772   bool isCopy() const {
00773     return getOpcode() == TargetOpcode::COPY;
00774   }
00775   bool isFullCopy() const {
00776     return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
00777   }
00778   bool isExtractSubreg() const {
00779     return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
00780   }
00781 
00782   /// isCopyLike - Return true if the instruction behaves like a copy.
00783   /// This does not include native copy instructions.
00784   bool isCopyLike() const {
00785     return isCopy() || isSubregToReg();
00786   }
00787 
00788   /// isIdentityCopy - Return true is the instruction is an identity copy.
00789   bool isIdentityCopy() const {
00790     return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
00791       getOperand(0).getSubReg() == getOperand(1).getSubReg();
00792   }
00793 
00794   /// isTransient - Return true if this is a transient instruction that is
00795   /// either very likely to be eliminated during register allocation (such as
00796   /// copy-like instructions), or if this instruction doesn't have an
00797   /// execution-time cost.
00798   bool isTransient() const {
00799     switch(getOpcode()) {
00800     default: return false;
00801     // Copy-like instructions are usually eliminated during register allocation.
00802     case TargetOpcode::PHI:
00803     case TargetOpcode::COPY:
00804     case TargetOpcode::INSERT_SUBREG:
00805     case TargetOpcode::SUBREG_TO_REG:
00806     case TargetOpcode::REG_SEQUENCE:
00807     // Pseudo-instructions that don't produce any real output.
00808     case TargetOpcode::IMPLICIT_DEF:
00809     case TargetOpcode::KILL:
00810     case TargetOpcode::CFI_INSTRUCTION:
00811     case TargetOpcode::EH_LABEL:
00812     case TargetOpcode::GC_LABEL:
00813     case TargetOpcode::DBG_VALUE:
00814       return true;
00815     }
00816   }
00817 
00818   /// Return the number of instructions inside the MI bundle, excluding the
00819   /// bundle header.
00820   ///
00821   /// This is the number of instructions that MachineBasicBlock::iterator
00822   /// skips, 0 for unbundled instructions.
00823   unsigned getBundleSize() const;
00824 
00825   /// readsRegister - Return true if the MachineInstr reads the specified
00826   /// register. If TargetRegisterInfo is passed, then it also checks if there
00827   /// is a read of a super-register.
00828   /// This does not count partial redefines of virtual registers as reads:
00829   ///   %reg1024:6 = OP.
00830   bool readsRegister(unsigned Reg,
00831                      const TargetRegisterInfo *TRI = nullptr) const {
00832     return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
00833   }
00834 
00835   /// readsVirtualRegister - Return true if the MachineInstr reads the specified
00836   /// virtual register. Take into account that a partial define is a
00837   /// read-modify-write operation.
00838   bool readsVirtualRegister(unsigned Reg) const {
00839     return readsWritesVirtualRegister(Reg).first;
00840   }
00841 
00842   /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
00843   /// indicating if this instruction reads or writes Reg. This also considers
00844   /// partial defines.
00845   /// If Ops is not null, all operand indices for Reg are added.
00846   std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
00847                                 SmallVectorImpl<unsigned> *Ops = nullptr) const;
00848 
00849   /// killsRegister - Return true if the MachineInstr kills the specified
00850   /// register. If TargetRegisterInfo is passed, then it also checks if there is
00851   /// a kill of a super-register.
00852   bool killsRegister(unsigned Reg,
00853                      const TargetRegisterInfo *TRI = nullptr) const {
00854     return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
00855   }
00856 
00857   /// definesRegister - Return true if the MachineInstr fully defines the
00858   /// specified register. If TargetRegisterInfo is passed, then it also checks
00859   /// if there is a def of a super-register.
00860   /// NOTE: It's ignoring subreg indices on virtual registers.
00861   bool definesRegister(unsigned Reg,
00862                        const TargetRegisterInfo *TRI = nullptr) const {
00863     return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
00864   }
00865 
00866   /// modifiesRegister - Return true if the MachineInstr modifies (fully define
00867   /// or partially define) the specified register.
00868   /// NOTE: It's ignoring subreg indices on virtual registers.
00869   bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
00870     return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
00871   }
00872 
00873   /// registerDefIsDead - Returns true if the register is dead in this machine
00874   /// instruction. If TargetRegisterInfo is passed, then it also checks
00875   /// if there is a dead def of a super-register.
00876   bool registerDefIsDead(unsigned Reg,
00877                          const TargetRegisterInfo *TRI = nullptr) const {
00878     return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
00879   }
00880 
00881   /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
00882   /// the specific register or -1 if it is not found. It further tightens
00883   /// the search criteria to a use that kills the register if isKill is true.
00884   int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
00885                                 const TargetRegisterInfo *TRI = nullptr) const;
00886 
00887   /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
00888   /// a pointer to the MachineOperand rather than an index.
00889   MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
00890                                       const TargetRegisterInfo *TRI = nullptr) {
00891     int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
00892     return (Idx == -1) ? nullptr : &getOperand(Idx);
00893   }
00894 
00895   /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
00896   /// the specified register or -1 if it is not found. If isDead is true, defs
00897   /// that are not dead are skipped. If Overlap is true, then it also looks for
00898   /// defs that merely overlap the specified register. If TargetRegisterInfo is
00899   /// non-null, then it also checks if there is a def of a super-register.
00900   /// This may also return a register mask operand when Overlap is true.
00901   int findRegisterDefOperandIdx(unsigned Reg,
00902                                 bool isDead = false, bool Overlap = false,
00903                                 const TargetRegisterInfo *TRI = nullptr) const;
00904 
00905   /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
00906   /// a pointer to the MachineOperand rather than an index.
00907   MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
00908                                       const TargetRegisterInfo *TRI = nullptr) {
00909     int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
00910     return (Idx == -1) ? nullptr : &getOperand(Idx);
00911   }
00912 
00913   /// findFirstPredOperandIdx() - Find the index of the first operand in the
00914   /// operand list that is used to represent the predicate. It returns -1 if
00915   /// none is found.
00916   int findFirstPredOperandIdx() const;
00917 
00918   /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
00919   /// corresponds to operand OpIdx on an inline asm instruction.  Returns -1 if
00920   /// getOperand(OpIdx) does not belong to an inline asm operand group.
00921   ///
00922   /// If GroupNo is not NULL, it will receive the number of the operand group
00923   /// containing OpIdx.
00924   ///
00925   /// The flag operand is an immediate that can be decoded with methods like
00926   /// InlineAsm::hasRegClassConstraint().
00927   ///
00928   int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
00929 
00930   /// getRegClassConstraint - Compute the static register class constraint for
00931   /// operand OpIdx.  For normal instructions, this is derived from the
00932   /// MCInstrDesc.  For inline assembly it is derived from the flag words.
00933   ///
00934   /// Returns NULL if the static register classs constraint cannot be
00935   /// determined.
00936   ///
00937   const TargetRegisterClass*
00938   getRegClassConstraint(unsigned OpIdx,
00939                         const TargetInstrInfo *TII,
00940                         const TargetRegisterInfo *TRI) const;
00941 
00942   /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
00943   /// the given \p CurRC.
00944   /// If \p ExploreBundle is set and MI is part of a bundle, all the
00945   /// instructions inside the bundle will be taken into account. In other words,
00946   /// this method accumulates all the constrains of the operand of this MI and
00947   /// the related bundle if MI is a bundle or inside a bundle.
00948   ///
00949   /// Returns the register class that statisfies both \p CurRC and the
00950   /// constraints set by MI. Returns NULL if such a register class does not
00951   /// exist.
00952   ///
00953   /// \pre CurRC must not be NULL.
00954   const TargetRegisterClass *getRegClassConstraintEffectForVReg(
00955       unsigned Reg, const TargetRegisterClass *CurRC,
00956       const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
00957       bool ExploreBundle = false) const;
00958 
00959   /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
00960   /// to the given \p CurRC.
00961   ///
00962   /// Returns the register class that statisfies both \p CurRC and the
00963   /// constraints set by \p OpIdx MI. Returns NULL if such a register class
00964   /// does not exist.
00965   ///
00966   /// \pre CurRC must not be NULL.
00967   /// \pre The operand at \p OpIdx must be a register.
00968   const TargetRegisterClass *
00969   getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
00970                               const TargetInstrInfo *TII,
00971                               const TargetRegisterInfo *TRI) const;
00972 
00973   /// tieOperands - Add a tie between the register operands at DefIdx and
00974   /// UseIdx. The tie will cause the register allocator to ensure that the two
00975   /// operands are assigned the same physical register.
00976   ///
00977   /// Tied operands are managed automatically for explicit operands in the
00978   /// MCInstrDesc. This method is for exceptional cases like inline asm.
00979   void tieOperands(unsigned DefIdx, unsigned UseIdx);
00980 
00981   /// findTiedOperandIdx - Given the index of a tied register operand, find the
00982   /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
00983   /// index of the tied operand which must exist.
00984   unsigned findTiedOperandIdx(unsigned OpIdx) const;
00985 
00986   /// isRegTiedToUseOperand - Given the index of a register def operand,
00987   /// check if the register def is tied to a source operand, due to either
00988   /// two-address elimination or inline assembly constraints. Returns the
00989   /// first tied use operand index by reference if UseOpIdx is not null.
00990   bool isRegTiedToUseOperand(unsigned DefOpIdx,
00991                              unsigned *UseOpIdx = nullptr) const {
00992     const MachineOperand &MO = getOperand(DefOpIdx);
00993     if (!MO.isReg() || !MO.isDef() || !MO.isTied())
00994       return false;
00995     if (UseOpIdx)
00996       *UseOpIdx = findTiedOperandIdx(DefOpIdx);
00997     return true;
00998   }
00999 
01000   /// isRegTiedToDefOperand - Return true if the use operand of the specified
01001   /// index is tied to a def operand. It also returns the def operand index by
01002   /// reference if DefOpIdx is not null.
01003   bool isRegTiedToDefOperand(unsigned UseOpIdx,
01004                              unsigned *DefOpIdx = nullptr) const {
01005     const MachineOperand &MO = getOperand(UseOpIdx);
01006     if (!MO.isReg() || !MO.isUse() || !MO.isTied())
01007       return false;
01008     if (DefOpIdx)
01009       *DefOpIdx = findTiedOperandIdx(UseOpIdx);
01010     return true;
01011   }
01012 
01013   /// clearKillInfo - Clears kill flags on all operands.
01014   ///
01015   void clearKillInfo();
01016 
01017   /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
01018   /// properly composing subreg indices where necessary.
01019   void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
01020                           const TargetRegisterInfo &RegInfo);
01021 
01022   /// addRegisterKilled - We have determined MI kills a register. Look for the
01023   /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
01024   /// add a implicit operand if it's not found. Returns true if the operand
01025   /// exists / is added.
01026   bool addRegisterKilled(unsigned IncomingReg,
01027                          const TargetRegisterInfo *RegInfo,
01028                          bool AddIfNotFound = false);
01029 
01030   /// clearRegisterKills - Clear all kill flags affecting Reg.  If RegInfo is
01031   /// provided, this includes super-register kills.
01032   void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
01033 
01034   /// addRegisterDead - We have determined MI defined a register without a use.
01035   /// Look for the operand that defines it and mark it as IsDead. If
01036   /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
01037   /// true if the operand exists / is added.
01038   bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
01039                        bool AddIfNotFound = false);
01040 
01041   /// addRegisterDefined - We have determined MI defines a register. Make sure
01042   /// there is an operand defining Reg.
01043   void addRegisterDefined(unsigned Reg,
01044                           const TargetRegisterInfo *RegInfo = nullptr);
01045 
01046   /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
01047   /// dead except those in the UsedRegs list.
01048   ///
01049   /// On instructions with register mask operands, also add implicit-def
01050   /// operands for all registers in UsedRegs.
01051   void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
01052                              const TargetRegisterInfo &TRI);
01053 
01054   /// isSafeToMove - Return true if it is safe to move this instruction. If
01055   /// SawStore is set to true, it means that there is a store (or call) between
01056   /// the instruction's location and its intended destination.
01057   bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
01058                     bool &SawStore) const;
01059 
01060   /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
01061   /// or volatile memory reference, or if the information describing the memory
01062   /// reference is not available. Return false if it is known to have no
01063   /// ordered or volatile memory references.
01064   bool hasOrderedMemoryRef() const;
01065 
01066   /// isInvariantLoad - Return true if this instruction is loading from a
01067   /// location whose value is invariant across the function.  For example,
01068   /// loading a value from the constant pool or from the argument area of
01069   /// a function if it does not change.  This should only return true of *all*
01070   /// loads the instruction does are invariant (if it does multiple loads).
01071   bool isInvariantLoad(AliasAnalysis *AA) const;
01072 
01073   /// isConstantValuePHI - If the specified instruction is a PHI that always
01074   /// merges together the same virtual register, return the register, otherwise
01075   /// return 0.
01076   unsigned isConstantValuePHI() const;
01077 
01078   /// hasUnmodeledSideEffects - Return true if this instruction has side
01079   /// effects that are not modeled by mayLoad / mayStore, etc.
01080   /// For all instructions, the property is encoded in MCInstrDesc::Flags
01081   /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
01082   /// INLINEASM instruction, in which case the side effect property is encoded
01083   /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
01084   ///
01085   bool hasUnmodeledSideEffects() const;
01086 
01087   /// allDefsAreDead - Return true if all the defs of this instruction are dead.
01088   ///
01089   bool allDefsAreDead() const;
01090 
01091   /// copyImplicitOps - Copy implicit register operands from specified
01092   /// instruction to this instruction.
01093   void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
01094 
01095   //
01096   // Debugging support
01097   //
01098   void print(raw_ostream &OS, const TargetMachine *TM = nullptr,
01099              bool SkipOpers = false) const;
01100   void dump() const;
01101 
01102   //===--------------------------------------------------------------------===//
01103   // Accessors used to build up machine instructions.
01104 
01105   /// Add the specified operand to the instruction.  If it is an implicit
01106   /// operand, it is added to the end of the operand list.  If it is an
01107   /// explicit operand it is added at the end of the explicit operand list
01108   /// (before the first implicit operand).
01109   ///
01110   /// MF must be the machine function that was used to allocate this
01111   /// instruction.
01112   ///
01113   /// MachineInstrBuilder provides a more convenient interface for creating
01114   /// instructions and adding operands.
01115   void addOperand(MachineFunction &MF, const MachineOperand &Op);
01116 
01117   /// Add an operand without providing an MF reference. This only works for
01118   /// instructions that are inserted in a basic block.
01119   ///
01120   /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
01121   /// preferred.
01122   void addOperand(const MachineOperand &Op);
01123 
01124   /// setDesc - Replace the instruction descriptor (thus opcode) of
01125   /// the current instruction with a new one.
01126   ///
01127   void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
01128 
01129   /// setDebugLoc - Replace current source information with new such.
01130   /// Avoid using this, the constructor argument is preferable.
01131   ///
01132   void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
01133 
01134   /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
01135   /// fewer operand than it started with.
01136   ///
01137   void RemoveOperand(unsigned i);
01138 
01139   /// addMemOperand - Add a MachineMemOperand to the machine instruction.
01140   /// This function should be used only occasionally. The setMemRefs function
01141   /// is the primary method for setting up a MachineInstr's MemRefs list.
01142   void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
01143 
01144   /// setMemRefs - Assign this MachineInstr's memory reference descriptor
01145   /// list. This does not transfer ownership.
01146   void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
01147     MemRefs = NewMemRefs;
01148     NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
01149     assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
01150   }
01151 
01152 private:
01153   /// getRegInfo - If this instruction is embedded into a MachineFunction,
01154   /// return the MachineRegisterInfo object for the current function, otherwise
01155   /// return null.
01156   MachineRegisterInfo *getRegInfo();
01157 
01158   /// untieRegOperand - Break any tie involving OpIdx.
01159   void untieRegOperand(unsigned OpIdx) {
01160     MachineOperand &MO = getOperand(OpIdx);
01161     if (MO.isReg() && MO.isTied()) {
01162       getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
01163       MO.TiedTo = 0;
01164     }
01165   }
01166 
01167   /// addImplicitDefUseOperands - Add all implicit def and use operands to
01168   /// this instruction.
01169   void addImplicitDefUseOperands(MachineFunction &MF);
01170 
01171   /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
01172   /// this instruction from their respective use lists.  This requires that the
01173   /// operands already be on their use lists.
01174   void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
01175 
01176   /// AddRegOperandsToUseLists - Add all of the register operands in
01177   /// this instruction from their respective use lists.  This requires that the
01178   /// operands not be on their use lists yet.
01179   void AddRegOperandsToUseLists(MachineRegisterInfo&);
01180 
01181   /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
01182   /// bundle.
01183   bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
01184 
01185   /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
01186   /// this MI and the given operand index \p OpIdx.
01187   /// If the related operand does not constrained Reg, this returns CurRC.
01188   const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
01189       unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
01190       const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
01191 };
01192 
01193 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
01194 /// MachineInstr* by *value* of the instruction rather than by pointer value.
01195 /// The hashing and equality testing functions ignore definitions so this is
01196 /// useful for CSE, etc.
01197 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
01198   static inline MachineInstr *getEmptyKey() {
01199     return nullptr;
01200   }
01201 
01202   static inline MachineInstr *getTombstoneKey() {
01203     return reinterpret_cast<MachineInstr*>(-1);
01204   }
01205 
01206   static unsigned getHashValue(const MachineInstr* const &MI);
01207 
01208   static bool isEqual(const MachineInstr* const &LHS,
01209                       const MachineInstr* const &RHS) {
01210     if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
01211         LHS == getEmptyKey() || LHS == getTombstoneKey())
01212       return LHS == RHS;
01213     return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
01214   }
01215 };
01216 
01217 //===----------------------------------------------------------------------===//
01218 // Debugging Support
01219 
01220 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
01221   MI.print(OS);
01222   return OS;
01223 }
01224 
01225 } // End llvm namespace
01226 
01227 #endif