Enumerations

enum NodeType {
FIRST_NUMBER = ISD::BUILTIN_OP_END, FSEL, FCFID, FCFIDU,
FCFIDS, FCFIDUS, FCTIDZ, FCTIWZ,
FCTIDUZ, FCTIWUZ, FRE, FRSQRTE,
VMADDFP, VNMSUBFP, VPERM, Hi,
Lo, TOC_ENTRY, LOAD, LOAD_TOC,
DYNALLOC, GlobalBaseReg, SRL, SRA,
SHL, CALL, CALL_NOP, MTCTR,
BCTRL, RET_FLAG, MFOCRF, ANDIo_1_EQ_BIT,
ANDIo_1_GT_BIT, EH_SJLJ_SETJMP, EH_SJLJ_LONGJMP, VCMP,
VCMPo, COND_BRANCH, BDNZ, BDZ,
FADDRTZ, MFFS, LARX, STCX,
TC_RETURN, CR6SET, CR6UNSET, PPC32_GOT,
PPC32_PICGOT, ADDIS_GOT_TPREL_HA, LD_GOT_TPREL_L, ADD_TLS,
ADDIS_TLSGD_HA, ADDI_TLSGD_L, GET_TLS_ADDR, ADDIS_TLSLD_HA,
ADDI_TLSLD_L, GET_TLSLD_ADDR, ADDIS_DTPREL_HA, ADDI_DTPREL_L,
VADD_SPLAT, SC, STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, LBRX,
STFIWX, LFIWAX, LFIWZX, ADDIS_TOC_HA,
LD_TOC_L, ADDI_TOC_L
}

Enumeration Type Documentation

enum llvm::PPCISD::NodeType

Enumerator:

FIRST_NUMBER
FSEL	FSEL - Traditional three-operand fsel node.
FCFID	FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP representation of the integer that was temporarily in the f64 operand.
FCFIDU	Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-precision outputs.
FCFIDS
FCFIDUS
FCTIDZ	FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value containing the integer representation of that FP value.
FCTIWZ
FCTIDUZ	Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers.
FCTIWUZ
FRE	Reciprocal estimate instructions (unary FP ops).
FRSQRTE
VMADDFP
VNMSUBFP
VPERM	VPERM - The PPC VPERM Instruction.
Hi	Hi/Lo - These represent the high and low 16-bit parts of a global address respectively. These nodes have two operands, the first of which must be a TargetGlobalAddress, and the second of which must be a Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', though these are usually folded into other nodes.
Lo
TOC_ENTRY
LOAD	Like a regular LOAD but additionally taking/producing a flag. The following two target-specific nodes are used for calls through function pointers in the 64-bit SVR4 ABI.
LOAD_TOC	Like LOAD (taking/producing a flag), but using r2 as hard-coded destination.
DYNALLOC	OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an allocation on the stack.
GlobalBaseReg	GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry, used for PIC code.
SRL	These nodes represent the 32-bit PPC shifts that operate on 6-bit shift amounts. These nodes are generated by the multi-precision shift code.
SRA
SHL
CALL	CALL - A direct function call. CALL_NOP is a call with the special NOP which follows 64-bit SVR4 calls.
CALL_NOP
MTCTR	CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
BCTRL	CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
RET_FLAG	Return with a flag operand, matched by 'blr'.
MFOCRF	R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. This copies the bits corresponding to the specified CRREG into the resultant GPR. Bits corresponding to other CR regs are undefined.
ANDIo_1_EQ_BIT	i1 = ANDIo_1_[EQ\|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after executing andi. x, 1. This is used to implement truncation of i32 or i64 to i1.
ANDIo_1_GT_BIT
EH_SJLJ_SETJMP
EH_SJLJ_LONGJMP
VCMP	RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions. For lack of better number, we use the opcode number encoding for the OPC field to identify the compare. For example, 838 is VCMPGTSH.
VCMPo	RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the altivec VCMP*o instructions. For lack of better number, we use the opcode number encoding for the OPC field to identify the compare. For example, 838 is VCMPGTSH.
COND_BRANCH	CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo instruction. CRRC is the condition register to branch on, OPC is the branch opcode to use (e.g. PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is an optional input flag argument.
BDNZ	CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
BDZ
FADDRTZ	F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero. Used only as part of the long double-to-int conversion sequence.
MFFS	F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
LARX	LARX = This corresponds to PPC l{w\|d}arx instrcution: load and reserve indexed. This is used to implement atomic operations.
STCX	STCX = This corresponds to PPC stcx. instrcution: store conditional indexed. This is used to implement atomic operations.
TC_RETURN	TC_RETURN - A tail call return. operand #0 chain operand #1 callee (register or absolute) operand #2 stack adjustment operand #3 optional in flag
CR6SET	ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
CR6UNSET
PPC32_GOT	GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS on PPC32.
PPC32_PICGOT	GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and local dynamic TLS on PPC32.
ADDIS_GOT_TPREL_HA	G8RC = ADDIS_GOT_TPREL_HA X2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruction that adds the GOT base to sym@got@tprel@ha.
LD_GOT_TPREL_L	G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction with base register G8RReg and offset sym@got@tprel@l. This completes the addition that finds the offset of "sym" relative to the thread pointer.
ADD_TLS	G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that adds the contents of G8RReg to the thread pointer. Symbol contains a relocation sym@tls which is to be replaced by the thread pointer and identifies to the linker that the instruction is part of a TLS sequence.
ADDIS_TLSGD_HA	G8RC = ADDIS_TLSGD_HA X2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction that adds the GOT base register to sym@got@tlsgd@ha.
ADDI_TLSGD_L	G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction that adds G8RReg to sym@got@tlsgd@l.
GET_TLS_ADDR	G8RC = GET_TLS_ADDR X3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(sym@tlsgd).
ADDIS_TLSLD_HA	G8RC = ADDIS_TLSLD_HA X2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction that adds the GOT base register to sym@got@tlsld@ha.
ADDI_TLSLD_L	G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction that adds G8RReg to sym@got@tlsld@l.
GET_TLSLD_ADDR	G8RC = GET_TLSLD_ADDR X3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(sym@tlsld).
ADDIS_DTPREL_HA	G8RC = ADDIS_DTPREL_HA X3, Symbol, Chain - For the local-dynamic TLS model, produces an ADDIS8 instruction that adds X3 to sym@dtprel@ha. The Chain operand is needed to tie this in place following a copy to X3 from the result of a GET_TLSLD_ADDR.
ADDI_DTPREL_L	G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction that adds G8RReg to sym@got@dtprel@l.
VADD_SPLAT	VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimize a BUILD_VECTOR into operations on splats. This is necessary to avoid losing these optimizations due to constant folding.
SC	CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned operand identifies the operating system entry point.
STBRX	CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction. It byte-swaps the low "Type" bits of the GPRC input, then stores it through Ptr. Type can be either i16 or i32.
LBRX	GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction. It loads "Type" bits, byte swaps it, then puts it in the bottom bits of the GPRC. TYPE can be either i16 or i32.
STFIWX	STFIWX - The STFIWX instruction. The first operand is an input token chain, then an f64 value to store, then an address to store it to.
LFIWAX	GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit integer value into the destination 64-bit register.
LFIWZX	GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit integer value into the destination 64-bit register.
ADDIS_TOC_HA	G8RC = ADDIS_TOC_HA X2, Symbol - For medium and large code model, produces an ADDIS8 instruction that adds the TOC base register to sym@toc@ha.
LD_TOC_L	G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, produces a LD instruction with base register G8RReg and offset sym@toc@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
ADDI_TOC_L	G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces an ADDI8 instruction that adds G8RReg to sym@toc@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.

Definition at line 27 of file PPCISelLowering.h.