Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
ade7758_core.c
Go to the documentation of this file.
1 /*
2  * ADE7758 Poly Phase Multifunction Energy Metering IC driver
3  *
4  * Copyright 2010-2011 Analog Devices Inc.
5  *
6  * Licensed under the GPL-2.
7  */
8 
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/delay.h>
12 #include <linux/mutex.h>
13 #include <linux/device.h>
14 #include <linux/kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/slab.h>
17 #include <linux/sysfs.h>
18 #include <linux/list.h>
19 #include <linux/module.h>
20 
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include "meter.h"
25 #include "ade7758.h"
26 
27 int ade7758_spi_write_reg_8(struct device *dev,
28  u8 reg_address,
29  u8 val)
30 {
31  int ret;
32  struct iio_dev *indio_dev = dev_to_iio_dev(dev);
33  struct ade7758_state *st = iio_priv(indio_dev);
34 
35  mutex_lock(&st->buf_lock);
36  st->tx[0] = ADE7758_WRITE_REG(reg_address);
37  st->tx[1] = val;
38 
39  ret = spi_write(st->us, st->tx, 2);
40  mutex_unlock(&st->buf_lock);
41 
42  return ret;
43 }
44 
45 static int ade7758_spi_write_reg_16(struct device *dev,
46  u8 reg_address,
47  u16 value)
48 {
49  int ret;
50  struct spi_message msg;
51  struct iio_dev *indio_dev = dev_to_iio_dev(dev);
52  struct ade7758_state *st = iio_priv(indio_dev);
53  struct spi_transfer xfers[] = {
54  {
55  .tx_buf = st->tx,
56  .bits_per_word = 8,
57  .len = 3,
58  }
59  };
60 
61  mutex_lock(&st->buf_lock);
62  st->tx[0] = ADE7758_WRITE_REG(reg_address);
63  st->tx[1] = (value >> 8) & 0xFF;
64  st->tx[2] = value & 0xFF;
65 
66  spi_message_init(&msg);
67  spi_message_add_tail(xfers, &msg);
68  ret = spi_sync(st->us, &msg);
69  mutex_unlock(&st->buf_lock);
70 
71  return ret;
72 }
73 
74 static int ade7758_spi_write_reg_24(struct device *dev,
75  u8 reg_address,
76  u32 value)
77 {
78  int ret;
79  struct spi_message msg;
80  struct iio_dev *indio_dev = dev_to_iio_dev(dev);
81  struct ade7758_state *st = iio_priv(indio_dev);
82  struct spi_transfer xfers[] = {
83  {
84  .tx_buf = st->tx,
85  .bits_per_word = 8,
86  .len = 4,
87  }
88  };
89 
90  mutex_lock(&st->buf_lock);
91  st->tx[0] = ADE7758_WRITE_REG(reg_address);
92  st->tx[1] = (value >> 16) & 0xFF;
93  st->tx[2] = (value >> 8) & 0xFF;
94  st->tx[3] = value & 0xFF;
95 
96  spi_message_init(&msg);
97  spi_message_add_tail(xfers, &msg);
98  ret = spi_sync(st->us, &msg);
99  mutex_unlock(&st->buf_lock);
100 
101  return ret;
102 }
103 
104 int ade7758_spi_read_reg_8(struct device *dev,
105  u8 reg_address,
106  u8 *val)
107 {
108  struct spi_message msg;
109  struct iio_dev *indio_dev = dev_to_iio_dev(dev);
110  struct ade7758_state *st = iio_priv(indio_dev);
111  int ret;
112  struct spi_transfer xfers[] = {
113  {
114  .tx_buf = st->tx,
115  .bits_per_word = 8,
116  .len = 1,
117  .delay_usecs = 4,
118  },
119  {
120  .tx_buf = &st->tx[1],
121  .rx_buf = st->rx,
122  .bits_per_word = 8,
123  .len = 1,
124  },
125  };
126 
127  mutex_lock(&st->buf_lock);
128  st->tx[0] = ADE7758_READ_REG(reg_address);
129  st->tx[1] = 0;
130 
131  spi_message_init(&msg);
132  spi_message_add_tail(&xfers[0], &msg);
133  spi_message_add_tail(&xfers[1], &msg);
134  ret = spi_sync(st->us, &msg);
135  if (ret) {
136  dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X",
137  reg_address);
138  goto error_ret;
139  }
140  *val = st->rx[0];
141 
142 error_ret:
143  mutex_unlock(&st->buf_lock);
144  return ret;
145 }
146 
147 static int ade7758_spi_read_reg_16(struct device *dev,
148  u8 reg_address,
149  u16 *val)
150 {
151  struct spi_message msg;
152  struct iio_dev *indio_dev = dev_to_iio_dev(dev);
153  struct ade7758_state *st = iio_priv(indio_dev);
154  int ret;
155  struct spi_transfer xfers[] = {
156  {
157  .tx_buf = st->tx,
158  .bits_per_word = 8,
159  .len = 1,
160  .delay_usecs = 4,
161  },
162  {
163  .tx_buf = &st->tx[1],
164  .rx_buf = st->rx,
165  .bits_per_word = 8,
166  .len = 2,
167  },
168  };
169 
170 
171  mutex_lock(&st->buf_lock);
172  st->tx[0] = ADE7758_READ_REG(reg_address);
173  st->tx[1] = 0;
174  st->tx[2] = 0;
175 
176  spi_message_init(&msg);
177  spi_message_add_tail(&xfers[0], &msg);
178  spi_message_add_tail(&xfers[1], &msg);
179  ret = spi_sync(st->us, &msg);
180  if (ret) {
181  dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X",
182  reg_address);
183  goto error_ret;
184  }
185 
186  *val = (st->rx[0] << 8) | st->rx[1];
187 
188 error_ret:
189  mutex_unlock(&st->buf_lock);
190  return ret;
191 }
192 
193 static int ade7758_spi_read_reg_24(struct device *dev,
194  u8 reg_address,
195  u32 *val)
196 {
197  struct spi_message msg;
198  struct iio_dev *indio_dev = dev_to_iio_dev(dev);
199  struct ade7758_state *st = iio_priv(indio_dev);
200  int ret;
201  struct spi_transfer xfers[] = {
202  {
203  .tx_buf = st->tx,
204  .bits_per_word = 8,
205  .len = 1,
206  .delay_usecs = 4,
207  },
208  {
209  .tx_buf = &st->tx[1],
210  .rx_buf = st->rx,
211  .bits_per_word = 8,
212  .len = 3,
213  },
214  };
215 
216  mutex_lock(&st->buf_lock);
217  st->tx[0] = ADE7758_READ_REG(reg_address);
218  st->tx[1] = 0;
219  st->tx[2] = 0;
220  st->tx[3] = 0;
221 
222  spi_message_init(&msg);
223  spi_message_add_tail(&xfers[0], &msg);
224  spi_message_add_tail(&xfers[1], &msg);
225  ret = spi_sync(st->us, &msg);
226  if (ret) {
227  dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X",
228  reg_address);
229  goto error_ret;
230  }
231  *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2];
232 
233 error_ret:
234  mutex_unlock(&st->buf_lock);
235  return ret;
236 }
237 
238 static ssize_t ade7758_read_8bit(struct device *dev,
239  struct device_attribute *attr,
240  char *buf)
241 {
242  int ret;
243  u8 val = 0;
244  struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
245 
246  ret = ade7758_spi_read_reg_8(dev, this_attr->address, &val);
247  if (ret)
248  return ret;
249 
250  return sprintf(buf, "%u\n", val);
251 }
252 
253 static ssize_t ade7758_read_16bit(struct device *dev,
254  struct device_attribute *attr,
255  char *buf)
256 {
257  int ret;
258  u16 val = 0;
259  struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
260 
261  ret = ade7758_spi_read_reg_16(dev, this_attr->address, &val);
262  if (ret)
263  return ret;
264 
265  return sprintf(buf, "%u\n", val);
266 }
267 
268 static ssize_t ade7758_read_24bit(struct device *dev,
269  struct device_attribute *attr,
270  char *buf)
271 {
272  int ret;
273  u32 val = 0;
274  struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
275 
276  ret = ade7758_spi_read_reg_24(dev, this_attr->address, &val);
277  if (ret)
278  return ret;
279 
280  return sprintf(buf, "%u\n", val & 0xFFFFFF);
281 }
282 
283 static ssize_t ade7758_write_8bit(struct device *dev,
284  struct device_attribute *attr,
285  const char *buf,
286  size_t len)
287 {
288  struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
289  int ret;
290  long val;
291 
292  ret = strict_strtol(buf, 10, &val);
293  if (ret)
294  goto error_ret;
295  ret = ade7758_spi_write_reg_8(dev, this_attr->address, val);
296 
297 error_ret:
298  return ret ? ret : len;
299 }
300 
301 static ssize_t ade7758_write_16bit(struct device *dev,
302  struct device_attribute *attr,
303  const char *buf,
304  size_t len)
305 {
306  struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
307  int ret;
308  long val;
309 
310  ret = strict_strtol(buf, 10, &val);
311  if (ret)
312  goto error_ret;
313  ret = ade7758_spi_write_reg_16(dev, this_attr->address, val);
314 
315 error_ret:
316  return ret ? ret : len;
317 }
318 
319 static int ade7758_reset(struct device *dev)
320 {
321  int ret;
322  u8 val;
323  ade7758_spi_read_reg_8(dev,
324  ADE7758_OPMODE,
325  &val);
326  val |= 1 << 6; /* Software Chip Reset */
327  ret = ade7758_spi_write_reg_8(dev,
328  ADE7758_OPMODE,
329  val);
330 
331  return ret;
332 }
333 
334 static ssize_t ade7758_write_reset(struct device *dev,
335  struct device_attribute *attr,
336  const char *buf, size_t len)
337 {
338  if (len < 1)
339  return -1;
340  switch (buf[0]) {
341  case '1':
342  case 'y':
343  case 'Y':
344  return ade7758_reset(dev);
345  }
346  return len;
347 }
348 
349 static IIO_DEV_ATTR_VPEAK(S_IWUSR | S_IRUGO,
350  ade7758_read_8bit,
351  ade7758_write_8bit,
352  ADE7758_VPEAK);
353 static IIO_DEV_ATTR_IPEAK(S_IWUSR | S_IRUGO,
354  ade7758_read_8bit,
355  ade7758_write_8bit,
356  ADE7758_VPEAK);
357 static IIO_DEV_ATTR_APHCAL(S_IWUSR | S_IRUGO,
358  ade7758_read_8bit,
359  ade7758_write_8bit,
360  ADE7758_APHCAL);
361 static IIO_DEV_ATTR_BPHCAL(S_IWUSR | S_IRUGO,
362  ade7758_read_8bit,
363  ade7758_write_8bit,
364  ADE7758_BPHCAL);
365 static IIO_DEV_ATTR_CPHCAL(S_IWUSR | S_IRUGO,
366  ade7758_read_8bit,
367  ade7758_write_8bit,
368  ADE7758_CPHCAL);
369 static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO,
370  ade7758_read_8bit,
371  ade7758_write_8bit,
372  ADE7758_WDIV);
373 static IIO_DEV_ATTR_VADIV(S_IWUSR | S_IRUGO,
374  ade7758_read_8bit,
375  ade7758_write_8bit,
376  ADE7758_VADIV);
377 static IIO_DEV_ATTR_AIRMS(S_IRUGO,
378  ade7758_read_24bit,
379  NULL,
380  ADE7758_AIRMS);
381 static IIO_DEV_ATTR_BIRMS(S_IRUGO,
382  ade7758_read_24bit,
383  NULL,
384  ADE7758_BIRMS);
385 static IIO_DEV_ATTR_CIRMS(S_IRUGO,
386  ade7758_read_24bit,
387  NULL,
388  ADE7758_CIRMS);
389 static IIO_DEV_ATTR_AVRMS(S_IRUGO,
390  ade7758_read_24bit,
391  NULL,
392  ADE7758_AVRMS);
393 static IIO_DEV_ATTR_BVRMS(S_IRUGO,
394  ade7758_read_24bit,
395  NULL,
396  ADE7758_BVRMS);
397 static IIO_DEV_ATTR_CVRMS(S_IRUGO,
398  ade7758_read_24bit,
399  NULL,
400  ADE7758_CVRMS);
401 static IIO_DEV_ATTR_AIRMSOS(S_IWUSR | S_IRUGO,
402  ade7758_read_16bit,
403  ade7758_write_16bit,
404  ADE7758_AIRMSOS);
405 static IIO_DEV_ATTR_BIRMSOS(S_IWUSR | S_IRUGO,
406  ade7758_read_16bit,
407  ade7758_write_16bit,
408  ADE7758_BIRMSOS);
409 static IIO_DEV_ATTR_CIRMSOS(S_IWUSR | S_IRUGO,
410  ade7758_read_16bit,
411  ade7758_write_16bit,
412  ADE7758_CIRMSOS);
413 static IIO_DEV_ATTR_AVRMSOS(S_IWUSR | S_IRUGO,
414  ade7758_read_16bit,
415  ade7758_write_16bit,
416  ADE7758_AVRMSOS);
417 static IIO_DEV_ATTR_BVRMSOS(S_IWUSR | S_IRUGO,
418  ade7758_read_16bit,
419  ade7758_write_16bit,
420  ADE7758_BVRMSOS);
421 static IIO_DEV_ATTR_CVRMSOS(S_IWUSR | S_IRUGO,
422  ade7758_read_16bit,
423  ade7758_write_16bit,
424  ADE7758_CVRMSOS);
425 static IIO_DEV_ATTR_AIGAIN(S_IWUSR | S_IRUGO,
426  ade7758_read_16bit,
427  ade7758_write_16bit,
428  ADE7758_AIGAIN);
429 static IIO_DEV_ATTR_BIGAIN(S_IWUSR | S_IRUGO,
430  ade7758_read_16bit,
431  ade7758_write_16bit,
432  ADE7758_BIGAIN);
433 static IIO_DEV_ATTR_CIGAIN(S_IWUSR | S_IRUGO,
434  ade7758_read_16bit,
435  ade7758_write_16bit,
436  ADE7758_CIGAIN);
437 static IIO_DEV_ATTR_AVRMSGAIN(S_IWUSR | S_IRUGO,
438  ade7758_read_16bit,
439  ade7758_write_16bit,
440  ADE7758_AVRMSGAIN);
441 static IIO_DEV_ATTR_BVRMSGAIN(S_IWUSR | S_IRUGO,
442  ade7758_read_16bit,
443  ade7758_write_16bit,
444  ADE7758_BVRMSGAIN);
445 static IIO_DEV_ATTR_CVRMSGAIN(S_IWUSR | S_IRUGO,
446  ade7758_read_16bit,
447  ade7758_write_16bit,
448  ADE7758_CVRMSGAIN);
449 
450 int ade7758_set_irq(struct device *dev, bool enable)
451 {
452  int ret;
453  u32 irqen;
454  ret = ade7758_spi_read_reg_24(dev, ADE7758_MASK, &irqen);
455  if (ret)
456  goto error_ret;
457 
458  if (enable)
459  irqen |= 1 << 16; /* Enables an interrupt when a data is
460  present in the waveform register */
461  else
462  irqen &= ~(1 << 16);
463 
464  ret = ade7758_spi_write_reg_24(dev, ADE7758_MASK, irqen);
465  if (ret)
466  goto error_ret;
467 
468 error_ret:
469  return ret;
470 }
471 
472 /* Power down the device */
473 static int ade7758_stop_device(struct device *dev)
474 {
475  int ret;
476  u8 val;
477  ade7758_spi_read_reg_8(dev,
478  ADE7758_OPMODE,
479  &val);
480  val |= 7 << 3; /* ADE7758 powered down */
481  ret = ade7758_spi_write_reg_8(dev,
482  ADE7758_OPMODE,
483  val);
484 
485  return ret;
486 }
487 
488 static int ade7758_initial_setup(struct iio_dev *indio_dev)
489 {
490  struct ade7758_state *st = iio_priv(indio_dev);
491  struct device *dev = &indio_dev->dev;
492  int ret;
493 
494  /* use low spi speed for init */
495  st->us->mode = SPI_MODE_1;
496  spi_setup(st->us);
497 
498  /* Disable IRQ */
499  ret = ade7758_set_irq(dev, false);
500  if (ret) {
501  dev_err(dev, "disable irq failed");
502  goto err_ret;
503  }
504 
505  ade7758_reset(dev);
506  msleep(ADE7758_STARTUP_DELAY);
507 
508 err_ret:
509  return ret;
510 }
511 
512 static ssize_t ade7758_read_frequency(struct device *dev,
513  struct device_attribute *attr,
514  char *buf)
515 {
516  int ret, len = 0;
517  u8 t;
518  int sps;
519  ret = ade7758_spi_read_reg_8(dev,
520  ADE7758_WAVMODE,
521  &t);
522  if (ret)
523  return ret;
524 
525  t = (t >> 5) & 0x3;
526  sps = 26040 / (1 << t);
527 
528  len = sprintf(buf, "%d SPS\n", sps);
529  return len;
530 }
531 
532 static ssize_t ade7758_write_frequency(struct device *dev,
533  struct device_attribute *attr,
534  const char *buf,
535  size_t len)
536 {
537  struct iio_dev *indio_dev = dev_to_iio_dev(dev);
538  unsigned long val;
539  int ret;
540  u8 reg, t;
541 
542  ret = strict_strtol(buf, 10, &val);
543  if (ret)
544  return ret;
545 
546  mutex_lock(&indio_dev->mlock);
547 
548  switch (val) {
549  case 26040:
550  t = 0;
551  break;
552  case 13020:
553  t = 1;
554  break;
555  case 6510:
556  t = 2;
557  break;
558  case 3255:
559  t = 3;
560  break;
561  default:
562  ret = -EINVAL;
563  goto out;
564  }
565 
566  ret = ade7758_spi_read_reg_8(dev,
567  ADE7758_WAVMODE,
568  &reg);
569  if (ret)
570  goto out;
571 
572  reg &= ~(5 << 3);
573  reg |= t << 5;
574 
575  ret = ade7758_spi_write_reg_8(dev,
576  ADE7758_WAVMODE,
577  reg);
578 
579 out:
580  mutex_unlock(&indio_dev->mlock);
581 
582  return ret ? ret : len;
583 }
584 
585 static IIO_DEV_ATTR_TEMP_RAW(ade7758_read_8bit);
586 static IIO_CONST_ATTR(in_temp_offset, "129 C");
587 static IIO_CONST_ATTR(in_temp_scale, "4 C");
588 
589 static IIO_DEV_ATTR_AWATTHR(ade7758_read_16bit,
590  ADE7758_AWATTHR);
591 static IIO_DEV_ATTR_BWATTHR(ade7758_read_16bit,
592  ADE7758_BWATTHR);
593 static IIO_DEV_ATTR_CWATTHR(ade7758_read_16bit,
594  ADE7758_CWATTHR);
595 static IIO_DEV_ATTR_AVARHR(ade7758_read_16bit,
596  ADE7758_AVARHR);
597 static IIO_DEV_ATTR_BVARHR(ade7758_read_16bit,
598  ADE7758_BVARHR);
599 static IIO_DEV_ATTR_CVARHR(ade7758_read_16bit,
600  ADE7758_CVARHR);
601 static IIO_DEV_ATTR_AVAHR(ade7758_read_16bit,
602  ADE7758_AVAHR);
603 static IIO_DEV_ATTR_BVAHR(ade7758_read_16bit,
604  ADE7758_BVAHR);
605 static IIO_DEV_ATTR_CVAHR(ade7758_read_16bit,
606  ADE7758_CVAHR);
607 
608 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
609  ade7758_read_frequency,
610  ade7758_write_frequency);
611 
612 static IIO_DEV_ATTR_RESET(ade7758_write_reset);
613 
614 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("26040 13020 6510 3255");
615 
616 static struct attribute *ade7758_attributes[] = {
617  &iio_dev_attr_in_temp_raw.dev_attr.attr,
618  &iio_const_attr_in_temp_offset.dev_attr.attr,
619  &iio_const_attr_in_temp_scale.dev_attr.attr,
620  &iio_dev_attr_sampling_frequency.dev_attr.attr,
621  &iio_const_attr_sampling_frequency_available.dev_attr.attr,
622  &iio_dev_attr_reset.dev_attr.attr,
623  &iio_dev_attr_awatthr.dev_attr.attr,
624  &iio_dev_attr_bwatthr.dev_attr.attr,
625  &iio_dev_attr_cwatthr.dev_attr.attr,
626  &iio_dev_attr_avarhr.dev_attr.attr,
627  &iio_dev_attr_bvarhr.dev_attr.attr,
628  &iio_dev_attr_cvarhr.dev_attr.attr,
629  &iio_dev_attr_avahr.dev_attr.attr,
630  &iio_dev_attr_bvahr.dev_attr.attr,
631  &iio_dev_attr_cvahr.dev_attr.attr,
632  &iio_dev_attr_vpeak.dev_attr.attr,
633  &iio_dev_attr_ipeak.dev_attr.attr,
634  &iio_dev_attr_aphcal.dev_attr.attr,
635  &iio_dev_attr_bphcal.dev_attr.attr,
636  &iio_dev_attr_cphcal.dev_attr.attr,
637  &iio_dev_attr_wdiv.dev_attr.attr,
638  &iio_dev_attr_vadiv.dev_attr.attr,
639  &iio_dev_attr_airms.dev_attr.attr,
640  &iio_dev_attr_birms.dev_attr.attr,
641  &iio_dev_attr_cirms.dev_attr.attr,
642  &iio_dev_attr_avrms.dev_attr.attr,
643  &iio_dev_attr_bvrms.dev_attr.attr,
644  &iio_dev_attr_cvrms.dev_attr.attr,
645  &iio_dev_attr_aigain.dev_attr.attr,
646  &iio_dev_attr_bigain.dev_attr.attr,
647  &iio_dev_attr_cigain.dev_attr.attr,
648  &iio_dev_attr_avrmsgain.dev_attr.attr,
649  &iio_dev_attr_bvrmsgain.dev_attr.attr,
650  &iio_dev_attr_cvrmsgain.dev_attr.attr,
651  &iio_dev_attr_airmsos.dev_attr.attr,
652  &iio_dev_attr_birmsos.dev_attr.attr,
653  &iio_dev_attr_cirmsos.dev_attr.attr,
654  &iio_dev_attr_avrmsos.dev_attr.attr,
655  &iio_dev_attr_bvrmsos.dev_attr.attr,
656  &iio_dev_attr_cvrmsos.dev_attr.attr,
657  NULL,
658 };
659 
660 static const struct attribute_group ade7758_attribute_group = {
661  .attrs = ade7758_attributes,
662 };
663 
664 static const struct iio_chan_spec ade7758_channels[] = {
665  {
666  .type = IIO_VOLTAGE,
667  .indexed = 1,
668  .channel = 0,
669  .extend_name = "raw",
670  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
671  IIO_CHAN_INFO_SCALE_SHARED_BIT,
672  .address = AD7758_WT(AD7758_PHASE_A, AD7758_VOLTAGE),
673  .scan_index = 0,
674  .scan_type = {
675  .sign = 's',
676  .realbits = 24,
677  .storagebits = 32,
678  },
679  }, {
680  .type = IIO_CURRENT,
681  .indexed = 1,
682  .channel = 0,
683  .extend_name = "raw",
684  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
685  IIO_CHAN_INFO_SCALE_SHARED_BIT,
686  .address = AD7758_WT(AD7758_PHASE_A, AD7758_CURRENT),
687  .scan_index = 1,
688  .scan_type = {
689  .sign = 's',
690  .realbits = 24,
691  .storagebits = 32,
692  },
693  }, {
694  .type = IIO_POWER,
695  .indexed = 1,
696  .channel = 0,
697  .extend_name = "apparent_raw",
698  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
699  IIO_CHAN_INFO_SCALE_SHARED_BIT,
700  .address = AD7758_WT(AD7758_PHASE_A, AD7758_APP_PWR),
701  .scan_index = 2,
702  .scan_type = {
703  .sign = 's',
704  .realbits = 24,
705  .storagebits = 32,
706  },
707  }, {
708  .type = IIO_POWER,
709  .indexed = 1,
710  .channel = 0,
711  .extend_name = "active_raw",
712  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
713  IIO_CHAN_INFO_SCALE_SHARED_BIT,
714  .address = AD7758_WT(AD7758_PHASE_A, AD7758_ACT_PWR),
715  .scan_index = 3,
716  .scan_type = {
717  .sign = 's',
718  .realbits = 24,
719  .storagebits = 32,
720  },
721  }, {
722  .type = IIO_POWER,
723  .indexed = 1,
724  .channel = 0,
725  .extend_name = "reactive_raw",
726  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
727  IIO_CHAN_INFO_SCALE_SHARED_BIT,
728  .address = AD7758_WT(AD7758_PHASE_A, AD7758_REACT_PWR),
729  .scan_index = 4,
730  .scan_type = {
731  .sign = 's',
732  .realbits = 24,
733  .storagebits = 32,
734  },
735  }, {
736  .type = IIO_VOLTAGE,
737  .indexed = 1,
738  .channel = 1,
739  .extend_name = "raw",
740  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
741  IIO_CHAN_INFO_SCALE_SHARED_BIT,
742  .address = AD7758_WT(AD7758_PHASE_B, AD7758_VOLTAGE),
743  .scan_index = 5,
744  .scan_type = {
745  .sign = 's',
746  .realbits = 24,
747  .storagebits = 32,
748  },
749  }, {
750  .type = IIO_CURRENT,
751  .indexed = 1,
752  .channel = 1,
753  .extend_name = "raw",
754  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
755  IIO_CHAN_INFO_SCALE_SHARED_BIT,
756  .address = AD7758_WT(AD7758_PHASE_B, AD7758_CURRENT),
757  .scan_index = 6,
758  .scan_type = {
759  .sign = 's',
760  .realbits = 24,
761  .storagebits = 32,
762  },
763  }, {
764  .type = IIO_POWER,
765  .indexed = 1,
766  .channel = 1,
767  .extend_name = "apparent_raw",
768  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
769  IIO_CHAN_INFO_SCALE_SHARED_BIT,
770  .address = AD7758_WT(AD7758_PHASE_B, AD7758_APP_PWR),
771  .scan_index = 7,
772  .scan_type = {
773  .sign = 's',
774  .realbits = 24,
775  .storagebits = 32,
776  },
777  }, {
778  .type = IIO_POWER,
779  .indexed = 1,
780  .channel = 1,
781  .extend_name = "active_raw",
782  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
783  IIO_CHAN_INFO_SCALE_SHARED_BIT,
784  .address = AD7758_WT(AD7758_PHASE_B, AD7758_ACT_PWR),
785  .scan_index = 8,
786  .scan_type = {
787  .sign = 's',
788  .realbits = 24,
789  .storagebits = 32,
790  },
791  }, {
792  .type = IIO_POWER,
793  .indexed = 1,
794  .channel = 1,
795  .extend_name = "reactive_raw",
796  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
797  IIO_CHAN_INFO_SCALE_SHARED_BIT,
798  .address = AD7758_WT(AD7758_PHASE_B, AD7758_REACT_PWR),
799  .scan_index = 9,
800  .scan_type = {
801  .sign = 's',
802  .realbits = 24,
803  .storagebits = 32,
804  },
805  }, {
806  .type = IIO_VOLTAGE,
807  .indexed = 1,
808  .channel = 2,
809  .extend_name = "raw",
810  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
811  IIO_CHAN_INFO_SCALE_SHARED_BIT,
812  .address = AD7758_WT(AD7758_PHASE_C, AD7758_VOLTAGE),
813  .scan_index = 10,
814  .scan_type = {
815  .sign = 's',
816  .realbits = 24,
817  .storagebits = 32,
818  },
819  }, {
820  .type = IIO_CURRENT,
821  .indexed = 1,
822  .channel = 2,
823  .extend_name = "raw",
824  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
825  IIO_CHAN_INFO_SCALE_SHARED_BIT,
826  .address = AD7758_WT(AD7758_PHASE_C, AD7758_CURRENT),
827  .scan_index = 11,
828  .scan_type = {
829  .sign = 's',
830  .realbits = 24,
831  .storagebits = 32,
832  },
833  }, {
834  .type = IIO_POWER,
835  .indexed = 1,
836  .channel = 2,
837  .extend_name = "apparent_raw",
838  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
839  IIO_CHAN_INFO_SCALE_SHARED_BIT,
840  .address = AD7758_WT(AD7758_PHASE_C, AD7758_APP_PWR),
841  .scan_index = 12,
842  .scan_type = {
843  .sign = 's',
844  .realbits = 24,
845  .storagebits = 32,
846  },
847  }, {
848  .type = IIO_POWER,
849  .indexed = 1,
850  .channel = 2,
851  .extend_name = "active_raw",
852  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
853  IIO_CHAN_INFO_SCALE_SHARED_BIT,
854  .address = AD7758_WT(AD7758_PHASE_C, AD7758_ACT_PWR),
855  .scan_index = 13,
856  .scan_type = {
857  .sign = 's',
858  .realbits = 24,
859  .storagebits = 32,
860  },
861  }, {
862  .type = IIO_POWER,
863  .indexed = 1,
864  .channel = 2,
865  .extend_name = "reactive_raw",
866  .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
867  IIO_CHAN_INFO_SCALE_SHARED_BIT,
868  .address = AD7758_WT(AD7758_PHASE_C, AD7758_REACT_PWR),
869  .scan_index = 14,
870  .scan_type = {
871  .sign = 's',
872  .realbits = 24,
873  .storagebits = 32,
874  },
875  },
876  IIO_CHAN_SOFT_TIMESTAMP(15),
877 };
878 
879 static const struct iio_info ade7758_info = {
880  .attrs = &ade7758_attribute_group,
881  .driver_module = THIS_MODULE,
882 };
883 
884 static int __devinit ade7758_probe(struct spi_device *spi)
885 {
886  int ret;
887  struct ade7758_state *st;
888  struct iio_dev *indio_dev = iio_device_alloc(sizeof(*st));
889 
890  if (indio_dev == NULL) {
891  ret = -ENOMEM;
892  goto error_ret;
893  }
894 
895  st = iio_priv(indio_dev);
896  /* this is only used for removal purposes */
897  spi_set_drvdata(spi, indio_dev);
898 
899  /* Allocate the comms buffers */
900  st->rx = kcalloc(ADE7758_MAX_RX, sizeof(*st->rx), GFP_KERNEL);
901  if (st->rx == NULL) {
902  ret = -ENOMEM;
903  goto error_free_dev;
904  }
905  st->tx = kcalloc(ADE7758_MAX_TX, sizeof(*st->tx), GFP_KERNEL);
906  if (st->tx == NULL) {
907  ret = -ENOMEM;
908  goto error_free_rx;
909  }
910  st->us = spi;
911  st->ade7758_ring_channels = &ade7758_channels[0];
912  mutex_init(&st->buf_lock);
913 
914  indio_dev->name = spi->dev.driver->name;
915  indio_dev->dev.parent = &spi->dev;
916  indio_dev->info = &ade7758_info;
917  indio_dev->modes = INDIO_DIRECT_MODE;
918 
919  ret = ade7758_configure_ring(indio_dev);
920  if (ret)
921  goto error_free_tx;
922 
923  ret = iio_buffer_register(indio_dev,
924  &ade7758_channels[0],
925  ARRAY_SIZE(ade7758_channels));
926  if (ret) {
927  dev_err(&spi->dev, "failed to initialize the ring\n");
928  goto error_unreg_ring_funcs;
929  }
930 
931  /* Get the device into a sane initial state */
932  ret = ade7758_initial_setup(indio_dev);
933  if (ret)
934  goto error_uninitialize_ring;
935 
936  if (spi->irq) {
937  ret = ade7758_probe_trigger(indio_dev);
938  if (ret)
939  goto error_uninitialize_ring;
940  }
941 
942  ret = iio_device_register(indio_dev);
943  if (ret)
944  goto error_remove_trigger;
945 
946  return 0;
947 
948 error_remove_trigger:
949  if (spi->irq)
950  ade7758_remove_trigger(indio_dev);
951 error_uninitialize_ring:
952  ade7758_uninitialize_ring(indio_dev);
953 error_unreg_ring_funcs:
954  ade7758_unconfigure_ring(indio_dev);
955 error_free_tx:
956  kfree(st->tx);
957 error_free_rx:
958  kfree(st->rx);
959 error_free_dev:
960  iio_device_free(indio_dev);
961 error_ret:
962  return ret;
963 }
964 
965 static int __devexit ade7758_remove(struct spi_device *spi)
966 {
967  struct iio_dev *indio_dev = spi_get_drvdata(spi);
968  struct ade7758_state *st = iio_priv(indio_dev);
969 
970  iio_device_unregister(indio_dev);
971  ade7758_stop_device(&indio_dev->dev);
972  ade7758_remove_trigger(indio_dev);
973  ade7758_uninitialize_ring(indio_dev);
974  ade7758_unconfigure_ring(indio_dev);
975  kfree(st->tx);
976  kfree(st->rx);
977 
978  iio_device_free(indio_dev);
979 
980  return 0;
981 }
982 
983 static const struct spi_device_id ade7758_id[] = {
984  {"ade7758", 0},
985  {}
986 };
987 MODULE_DEVICE_TABLE(spi, ade7758_id);
988 
989 static struct spi_driver ade7758_driver = {
990  .driver = {
991  .name = "ade7758",
992  .owner = THIS_MODULE,
993  },
994  .probe = ade7758_probe,
995  .remove = __devexit_p(ade7758_remove),
996  .id_table = ade7758_id,
997 };
998 module_spi_driver(ade7758_driver);
999 
1000 MODULE_AUTHOR("Barry Song <[email protected]>");
1001 MODULE_DESCRIPTION("Analog Devices ADE7758 Polyphase Multifunction Energy Metering IC Driver");
1002 MODULE_LICENSE("GPL v2");
Generated on Thu Jan 10 2013 14:28:50 for Linux Kernel by   doxygen 1.8.2