#include "../comedidev.h"
#include <linux/delay.h>
#include "8255.h"
#include "8253.h"

Data Structures
struct	diosubd_data

struct	dio_boardtype

struct	pci_dio_private

Macros
#define	PCI_VENDOR_ID_ADVANTECH 0x13fe

#define	MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */

#define	MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */

#define	MAX_DIO_SUBDEVG

#define	MAX_8254_SUBDEVS

#define	SIZE_8254 4 /* 8254 IO space length */

#define	SIZE_8255 4 /* 8255 IO space length */

#define	PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */

#define	PCI1730_IDI 0 /* R: Isolated digital input 0-15 */

#define	PCI1730_IDO 0 /* W: Isolated digital output 0-15 */

#define	PCI1730_DI 2 /* R: Digital input 0-15 */

#define	PCI1730_DO 2 /* W: Digital output 0-15 */

#define	PCI1733_IDI 0 /* R: Isolated digital input 0-31 */

#define	PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */

#define	PCI1730_3_INT_RF

#define	PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */

#define	PCI1734_IDO 0 /* W: Isolated digital output 0-31 */

#define	PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */

#define	PCI1735_DI 0 /* R: Digital input 0-31 */

#define	PCI1735_DO 0 /* W: Digital output 0-31 */

#define	PCI1735_C8254 4 /* R/W: 8254 counter */

#define	PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */

#define	PCI1736_IDI 0 /* R: Isolated digital input 0-15 */

#define	PCI1736_IDO 0 /* W: Isolated digital output 0-15 */

#define	PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */

#define	PCI1736_3_INT_RF

#define	PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */

#define	PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */

#define	PCI1736_MAINREG 0 /* Normal register (2) doesn't work */

#define	PCI1739_DIO 0 /* R/W: begin of 8255 registers block */

#define	PCI1739_ICR 32 /* W: Interrupt control register */

#define	PCI1739_ISR 32 /* R: Interrupt status register */

#define	PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */

#define	PCI1750_IDI 0 /* R: Isolated digital input 0-15 */

#define	PCI1750_IDO 0 /* W: Isolated digital output 0-15 */

#define	PCI1750_ICR 32 /* W: Interrupt control register */

#define	PCI1750_ISR 32 /* R: Interrupt status register */

#define	PCI1751_DIO 0 /* R/W: begin of 8255 registers block */

#define	PCI1751_CNT 24 /* R/W: begin of 8254 registers block */

#define	PCI1751_ICR 32 /* W: Interrupt control register */

#define	PCI1751_ISR 32 /* R: Interrupt status register */

#define	PCI1753_DIO 0 /* R/W: begin of 8255 registers block */

#define	PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */

#define	PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */

#define	PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */

#define	PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */

#define	PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */

#define	PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */

#define	PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */

#define	PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */

#define	PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */

#define	PCI1752_IDO 0 /* R/W: Digital output 0-31 */

#define	PCI1752_IDO2 4 /* R/W: Digital output 32-63 */

#define	PCI1754_IDI 0 /* R: Digital input 0-31 */

#define	PCI1754_IDI2 4 /* R: Digital input 32-64 */

#define	PCI1756_IDI 0 /* R: Digital input 0-31 */

#define	PCI1756_IDO 4 /* R/W: Digital output 0-31 */

#define	PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */

#define	PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */

#define	PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */

#define	PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */

#define	PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */

#define	PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */

#define	PCI1762_RO 0 /* R/W: Relays status/output */

#define	PCI1762_IDI 2 /* R: Isolated input status */

#define	PCI1762_BOARDID 4 /* R: Board I/D switch */

#define	PCI1762_ICR 6 /* W: Interrupt control register */

#define	PCI1762_ISR 6 /* R: Interrupt status register */

#define	OMB0 0x0c /* W: Mailbox outgoing registers */

#define	OMB1 0x0d

#define	OMB2 0x0e

#define	OMB3 0x0f

#define	IMB0 0x1c /* R: Mailbox incoming registers */

#define	IMB1 0x1d

#define	IMB2 0x1e

#define	IMB3 0x1f

#define	INTCSR0 0x38 /* R/W: Interrupt control registers */

#define	INTCSR1 0x39

#define	INTCSR2 0x3a

#define	INTCSR3 0x3b

#define	CMD_ClearIMB2

#define	CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */

#define	CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */

#define	CMD_ReadCurrentStatus

#define	CMD_ReadFirmwareVersion

#define	CMD_ReadHardwareVersion

#define	CMD_EnableIDIFilters

#define	CMD_EnableIDIPatternMatch

#define	CMD_SetIDIPatternMatch

#define	CMD_EnableIDICounters

#define	CMD_ResetIDICounters

#define	CMD_OverflowIDICounters

#define	CMD_MatchIntIDICounters

#define	CMD_EdgeIDICounters

#define	CMD_GetIDICntCurValue

#define	CMD_SetIDI0CntResetValue

#define	CMD_SetIDI1CntResetValue

#define	CMD_SetIDI2CntResetValue

#define	CMD_SetIDI3CntResetValue

#define	CMD_SetIDI4CntResetValue

#define	CMD_SetIDI5CntResetValue

#define	CMD_SetIDI6CntResetValue

#define	CMD_SetIDI7CntResetValue

#define	CMD_SetIDI0CntMatchValue

#define	CMD_SetIDI1CntMatchValue

#define	CMD_SetIDI2CntMatchValue

#define	CMD_SetIDI3CntMatchValue

#define	CMD_SetIDI4CntMatchValue

#define	CMD_SetIDI5CntMatchValue

#define	CMD_SetIDI6CntMatchValue

#define	CMD_SetIDI7CntMatchValue

#define	OMBCMD_RETRY 0x03 /* 3 times try request before error */

Enumerations
enum	hw_cards_id { TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736, TYPE_PCI1739, TYPE_PCI1750, TYPE_PCI1751, TYPE_PCI1752, TYPE_PCI1753, TYPE_PCI1753E, TYPE_PCI1754, TYPE_PCI1756, TYPE_PCI1760, TYPE_PCI1762 }

enum	hw_io_access { IO_8b, IO_16b }

Functions
	MODULE_DEVICE_TABLE (pci, adv_pci_dio_pci_table)

	module_comedi_pci_driver (adv_pci_dio_driver, adv_pci_dio_pci_driver)

	MODULE_AUTHOR ("Comedi http://www.comedi.org")

	MODULE_DESCRIPTION ("Comedi low-level driver")

	MODULE_LICENSE ("GPL")

Macro Definition Documentation

#define CMD_ClearIMB2

Value:

0x00 /* Clear IMB2 status and return actual

* DI status in IMB3 */

Definition at line 163 of file adv_pci_dio.c.

#define CMD_EdgeIDICounters

Value:

0x2c /* Set IDI up counters count edge (bit=0

* - rising, =1 - falling) */

Definition at line 176 of file adv_pci_dio.c.

#define CMD_EnableIDICounters

Value:

0x28 /* Enable IDI counters based on bits in

* OMB0 */

Definition at line 172 of file adv_pci_dio.c.

#define CMD_EnableIDIFilters

Value:

0x20 /* Enable IDI filters based on bits in

* OMB0 */

Definition at line 169 of file adv_pci_dio.c.

#define CMD_EnableIDIPatternMatch

Value:

0x21 /* Enable IDI pattern match based on

* bits in OMB0 */

Definition at line 170 of file adv_pci_dio.c.

#define CMD_GetIDICntCurValue

Value:

0x2f /* Read IDI{OMB0} up counter current

* value */

Definition at line 177 of file adv_pci_dio.c.

#define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */

Definition at line 165 of file adv_pci_dio.c.

#define CMD_MatchIntIDICounters

Value:

0x2b /* Enable IDI counters match value

* interrupts based on bits in OMB0 */

Definition at line 175 of file adv_pci_dio.c.

#define CMD_OverflowIDICounters

Value:

0x2a /* Enable IDI counters overflow

* interrupts based on bits in OMB0 */

Definition at line 174 of file adv_pci_dio.c.

#define CMD_ReadCurrentStatus

Value:

0x07 /* Read the current status of the

* register in OMB0, result in IMB0 */

Definition at line 166 of file adv_pci_dio.c.

#define CMD_ReadFirmwareVersion

Value:

0x0e /* Read the firmware ver., result in

* IMB1.IMB0 */

Definition at line 167 of file adv_pci_dio.c.

#define CMD_ReadHardwareVersion

Value:

0x0f /* Read the hardware ver., result in

* IMB1.IMB0 */

Definition at line 168 of file adv_pci_dio.c.

#define CMD_ResetIDICounters

Value:

0x29 /* Reset IDI counters based on bits in

* OMB0 to its reset values */

Definition at line 173 of file adv_pci_dio.c.

#define CMD_SetIDI0CntMatchValue

Value:

0x48 /* Set IDI0 Counter Match Value

* 256*OMB1+OMB0 */

Definition at line 186 of file adv_pci_dio.c.

#define CMD_SetIDI0CntResetValue

Value:

0x40 /* Set IDI0 Counter Reset Value

* 256*OMB1+OMB0 */

Definition at line 178 of file adv_pci_dio.c.

#define CMD_SetIDI1CntMatchValue

Value:

0x49 /* Set IDI1 Counter Match Value

* 256*OMB1+OMB0 */

Definition at line 187 of file adv_pci_dio.c.

#define CMD_SetIDI1CntResetValue

Value:

0x41 /* Set IDI1 Counter Reset Value

* 256*OMB1+OMB0 */

Definition at line 179 of file adv_pci_dio.c.

#define CMD_SetIDI2CntMatchValue

Value:

0x4a /* Set IDI2 Counter Match Value

* 256*OMB1+OMB0 */

Definition at line 188 of file adv_pci_dio.c.

#define CMD_SetIDI2CntResetValue

Value:

0x42 /* Set IDI2 Counter Reset Value

* 256*OMB1+OMB0 */

Definition at line 180 of file adv_pci_dio.c.

#define CMD_SetIDI3CntMatchValue

Value:

0x4b /* Set IDI3 Counter Match Value

* 256*OMB1+OMB0 */

Definition at line 189 of file adv_pci_dio.c.

#define CMD_SetIDI3CntResetValue

Value:

0x43 /* Set IDI3 Counter Reset Value

* 256*OMB1+OMB0 */

Definition at line 181 of file adv_pci_dio.c.

#define CMD_SetIDI4CntMatchValue

Value:

0x4c /* Set IDI4 Counter Match Value

* 256*OMB1+OMB0 */

Definition at line 190 of file adv_pci_dio.c.

#define CMD_SetIDI4CntResetValue

Value:

0x44 /* Set IDI4 Counter Reset Value

* 256*OMB1+OMB0 */

Definition at line 182 of file adv_pci_dio.c.

#define CMD_SetIDI5CntMatchValue

Value:

0x4d /* Set IDI5 Counter Match Value

* 256*OMB1+OMB0 */

Definition at line 191 of file adv_pci_dio.c.

#define CMD_SetIDI5CntResetValue

Value:

0x45 /* Set IDI5 Counter Reset Value

* 256*OMB1+OMB0 */

Definition at line 183 of file adv_pci_dio.c.

#define CMD_SetIDI6CntMatchValue

Value:

0x4e /* Set IDI6 Counter Match Value

* 256*OMB1+OMB0 */

Definition at line 192 of file adv_pci_dio.c.

#define CMD_SetIDI6CntResetValue

Value:

0x46 /* Set IDI6 Counter Reset Value

* 256*OMB1+OMB0 */

Definition at line 184 of file adv_pci_dio.c.

#define CMD_SetIDI7CntMatchValue

Value:

0x4f /* Set IDI7 Counter Match Value

* 256*OMB1+OMB0 */

Definition at line 193 of file adv_pci_dio.c.

#define CMD_SetIDI7CntResetValue

Value:

0x47 /* Set IDI7 Counter Reset Value

* 256*OMB1+OMB0 */

Definition at line 185 of file adv_pci_dio.c.

#define CMD_SetIDIPatternMatch

Value:

0x22 /* Enable IDI pattern match based on

* bits in OMB0 */

Definition at line 171 of file adv_pci_dio.c.

#define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */

Definition at line 164 of file adv_pci_dio.c.

#define IMB0 0x1c /* R: Mailbox incoming registers */

Definition at line 153 of file adv_pci_dio.c.

#define IMB1 0x1d

Definition at line 154 of file adv_pci_dio.c.

#define IMB2 0x1e

Definition at line 155 of file adv_pci_dio.c.

#define IMB3 0x1f

Definition at line 156 of file adv_pci_dio.c.

#define INTCSR0 0x38 /* R/W: Interrupt control registers */

Definition at line 157 of file adv_pci_dio.c.

#define INTCSR1 0x39

Definition at line 158 of file adv_pci_dio.c.

#define INTCSR2 0x3a

Definition at line 159 of file adv_pci_dio.c.

#define INTCSR3 0x3b

Definition at line 160 of file adv_pci_dio.c.

#define MAX_8254_SUBDEVS

Value:

1 /* max number of 8254 counter subdevs per

* card */

Definition at line 62 of file adv_pci_dio.c.

#define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */

Definition at line 59 of file adv_pci_dio.c.

#define MAX_DIO_SUBDEVG

Value:

2 /* max number of DIO subdevices group per

* card */

Definition at line 61 of file adv_pci_dio.c.

#define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */

Definition at line 60 of file adv_pci_dio.c.

#define OMB0 0x0c /* W: Mailbox outgoing registers */

Definition at line 149 of file adv_pci_dio.c.

#define OMB1 0x0d

Definition at line 150 of file adv_pci_dio.c.

#define OMB2 0x0e

Definition at line 151 of file adv_pci_dio.c.

#define OMB3 0x0f

Definition at line 152 of file adv_pci_dio.c.

#define OMBCMD_RETRY 0x03 /* 3 times try request before error */

Definition at line 195 of file adv_pci_dio.c.

#define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */

Definition at line 80 of file adv_pci_dio.c.

#define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */

Definition at line 78 of file adv_pci_dio.c.

#define PCI1730_3_INT_RF

Value:

0x0c /* R/W: set falling/raising edge for

* interrupts */

Definition at line 79 of file adv_pci_dio.c.

#define PCI1730_DI 2 /* R: Digital input 0-15 */

Definition at line 75 of file adv_pci_dio.c.

#define PCI1730_DO 2 /* W: Digital output 0-15 */

Definition at line 76 of file adv_pci_dio.c.

#define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */

Definition at line 73 of file adv_pci_dio.c.

#define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */

Definition at line 74 of file adv_pci_dio.c.

#define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */

Definition at line 77 of file adv_pci_dio.c.

#define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */

Definition at line 81 of file adv_pci_dio.c.

#define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */

Definition at line 88 of file adv_pci_dio.c.

#define PCI1735_C8254 4 /* R/W: 8254 counter */

Definition at line 87 of file adv_pci_dio.c.

#define PCI1735_DI 0 /* R: Digital input 0-31 */

Definition at line 85 of file adv_pci_dio.c.

#define PCI1735_DO 0 /* W: Digital output 0-31 */

Definition at line 86 of file adv_pci_dio.c.

#define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */

Definition at line 95 of file adv_pci_dio.c.

#define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */

Definition at line 93 of file adv_pci_dio.c.

#define PCI1736_3_INT_RF

Value:

0x0c /* R/W: set falling/raising edge for

* interrupts */

Definition at line 94 of file adv_pci_dio.c.

#define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */

Definition at line 96 of file adv_pci_dio.c.

#define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */

Definition at line 91 of file adv_pci_dio.c.

#define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */

Definition at line 92 of file adv_pci_dio.c.

#define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */

Definition at line 97 of file adv_pci_dio.c.

#define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */

Definition at line 103 of file adv_pci_dio.c.

#define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */

Definition at line 100 of file adv_pci_dio.c.

#define PCI1739_ICR 32 /* W: Interrupt control register */

Definition at line 101 of file adv_pci_dio.c.

#define PCI1739_ISR 32 /* R: Interrupt status register */

Definition at line 102 of file adv_pci_dio.c.

#define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */

Definition at line 82 of file adv_pci_dio.c.

#define PCI1750_ICR 32 /* W: Interrupt control register */

Definition at line 108 of file adv_pci_dio.c.

#define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */

Definition at line 106 of file adv_pci_dio.c.

#define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */

Definition at line 107 of file adv_pci_dio.c.

#define PCI1750_ISR 32 /* R: Interrupt status register */

Definition at line 109 of file adv_pci_dio.c.

#define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */

Definition at line 113 of file adv_pci_dio.c.

#define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */

Definition at line 112 of file adv_pci_dio.c.

#define PCI1751_ICR 32 /* W: Interrupt control register */

Definition at line 114 of file adv_pci_dio.c.

#define PCI1751_ISR 32 /* R: Interrupt status register */

Definition at line 115 of file adv_pci_dio.c.

#define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */

Definition at line 138 of file adv_pci_dio.c.

#define PCI1752_IDO 0 /* R/W: Digital output 0-31 */

Definition at line 128 of file adv_pci_dio.c.

#define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */

Definition at line 129 of file adv_pci_dio.c.

#define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */

Definition at line 116 of file adv_pci_dio.c.

#define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */

Definition at line 117 of file adv_pci_dio.c.

#define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */

Definition at line 118 of file adv_pci_dio.c.

#define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */

Definition at line 119 of file adv_pci_dio.c.

#define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */

Definition at line 120 of file adv_pci_dio.c.

#define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */

Definition at line 121 of file adv_pci_dio.c.

#define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */

Definition at line 122 of file adv_pci_dio.c.

#define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */

Definition at line 123 of file adv_pci_dio.c.

#define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */

Definition at line 124 of file adv_pci_dio.c.

#define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */

Definition at line 125 of file adv_pci_dio.c.

#define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */

Definition at line 134 of file adv_pci_dio.c.

#define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */

Definition at line 135 of file adv_pci_dio.c.

#define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */

Definition at line 136 of file adv_pci_dio.c.

#define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */

Definition at line 137 of file adv_pci_dio.c.

#define PCI1754_IDI 0 /* R: Digital input 0-31 */

Definition at line 130 of file adv_pci_dio.c.

#define PCI1754_IDI2 4 /* R: Digital input 32-64 */

Definition at line 131 of file adv_pci_dio.c.

#define PCI1756_IDI 0 /* R: Digital input 0-31 */

Definition at line 132 of file adv_pci_dio.c.

#define PCI1756_IDO 4 /* R/W: Digital output 0-31 */

Definition at line 133 of file adv_pci_dio.c.

#define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */

Definition at line 139 of file adv_pci_dio.c.

#define PCI1762_BOARDID 4 /* R: Board I/D switch */

Definition at line 144 of file adv_pci_dio.c.

#define PCI1762_ICR 6 /* W: Interrupt control register */

Definition at line 145 of file adv_pci_dio.c.

#define PCI1762_IDI 2 /* R: Isolated input status */

Definition at line 143 of file adv_pci_dio.c.

#define PCI1762_ISR 6 /* R: Interrupt status register */

Definition at line 146 of file adv_pci_dio.c.

#define PCI1762_RO 0 /* R/W: Relays status/output */

Definition at line 142 of file adv_pci_dio.c.

#define PCI_VENDOR_ID_ADVANTECH 0x13fe

Definition at line 39 of file adv_pci_dio.c.

#define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */

Definition at line 69 of file adv_pci_dio.c.

#define SIZE_8254 4 /* 8254 IO space length */

Definition at line 66 of file adv_pci_dio.c.

#define SIZE_8255 4 /* 8255 IO space length */

Definition at line 67 of file adv_pci_dio.c.

Enumeration Type Documentation

enum hw_cards_id

Enumerator:

TYPE_PCI1730
TYPE_PCI1733
TYPE_PCI1734
TYPE_PCI1735
TYPE_PCI1736
TYPE_PCI1739
TYPE_PCI1750
TYPE_PCI1751
TYPE_PCI1752
TYPE_PCI1753
TYPE_PCI1753E
TYPE_PCI1754
TYPE_PCI1756
TYPE_PCI1760
TYPE_PCI1762

Definition at line 42 of file adv_pci_dio.c.

enum hw_io_access

Enumerator:

IO_8b
IO_16b

Definition at line 55 of file adv_pci_dio.c.

Function Documentation

MODULE_AUTHOR ( "Comedi http://www.comedi.org" )

module_comedi_pci_driver	(	adv_pci_dio_driver	,
		adv_pci_dio_pci_driver
	)

MODULE_DESCRIPTION ( "Comedi low-level driver" )

MODULE_DEVICE_TABLE	(	pci	,
		adv_pci_dio_pci_table
	)

MODULE_LICENSE ( "GPL" )

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation