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adv_pci_dio.c
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1 /*
2  * comedi/drivers/adv_pci_dio.c
3  *
4  * Author: Michal Dobes <[email protected]>
5  *
6  * Hardware driver for Advantech PCI DIO cards.
7 */
8 /*
9 Driver: adv_pci_dio
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11  PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12  PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
13 Author: Michal Dobes <[email protected]>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15  PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16  PCI-1751, PCI-1752, PCI-1753,
17  PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
18  PCI-1760, PCI-1762
19 Status: untested
20 Updated: Mon, 09 Jan 2012 12:40:46 +0000
21 
22 This driver supports now only insn interface for DI/DO/DIO.
23 
24 Configuration options:
25  [0] - PCI bus of device (optional)
26  [1] - PCI slot of device (optional)
27  If bus/slot is not specified, the first available PCI
28  device will be used.
29 
30 */
31 
32 #include "../comedidev.h"
33 
34 #include <linux/delay.h>
35 
36 #include "8255.h"
37 #include "8253.h"
38 
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 
41 /* hardware types of the cards */
42 enum hw_cards_id {
43  TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736,
44  TYPE_PCI1739,
45  TYPE_PCI1750,
46  TYPE_PCI1751,
47  TYPE_PCI1752,
48  TYPE_PCI1753, TYPE_PCI1753E,
49  TYPE_PCI1754, TYPE_PCI1756,
50  TYPE_PCI1760,
51  TYPE_PCI1762
52 };
53 
54 /* which I/O instructions to use */
55 enum hw_io_access {
56  IO_8b, IO_16b
57 };
58 
59 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
60 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
61 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
62  * card */
63 #define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
64  * card */
65  /* (could be more than one 8254 per
66  * subdevice) */
67 
68 #define SIZE_8254 4 /* 8254 IO space length */
69 #define SIZE_8255 4 /* 8255 IO space length */
70 
71 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
72 
73 /* Register offset definitions */
74 /* Advantech PCI-1730/3/4 */
75 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
76 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
77 #define PCI1730_DI 2 /* R: Digital input 0-15 */
78 #define PCI1730_DO 2 /* W: Digital output 0-15 */
79 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
80 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
81 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
82  * interrupts */
83 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
84 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
85 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
86 
87 /* Advantech PCI-1735U */
88 #define PCI1735_DI 0 /* R: Digital input 0-31 */
89 #define PCI1735_DO 0 /* W: Digital output 0-31 */
90 #define PCI1735_C8254 4 /* R/W: 8254 counter */
91 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
92 
93 /* Advantech PCI-1736UP */
94 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
95 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
96 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
97 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
98  * interrupts */
99 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
100 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
101 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
102 
103 /* Advantech PCI-1739U */
104 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
105 #define PCI1739_ICR 32 /* W: Interrupt control register */
106 #define PCI1739_ISR 32 /* R: Interrupt status register */
107 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
108 
109 /* Advantech PCI-1750 */
110 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
111 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
112 #define PCI1750_ICR 32 /* W: Interrupt control register */
113 #define PCI1750_ISR 32 /* R: Interrupt status register */
114 
115 /* Advantech PCI-1751/3/3E */
116 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
117 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
118 #define PCI1751_ICR 32 /* W: Interrupt control register */
119 #define PCI1751_ISR 32 /* R: Interrupt status register */
120 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
121 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
122 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
123 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
124 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
125 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
126 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
127 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
128 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
129 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
130 
131 /* Advantech PCI-1752/4/6 */
132 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
133 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
134 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
135 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
136 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
137 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
138 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
139 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
140 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
141 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
142 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
143 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
144 
145 /* Advantech PCI-1762 registers */
146 #define PCI1762_RO 0 /* R/W: Relays status/output */
147 #define PCI1762_IDI 2 /* R: Isolated input status */
148 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
149 #define PCI1762_ICR 6 /* W: Interrupt control register */
150 #define PCI1762_ISR 6 /* R: Interrupt status register */
151 
152 /* Advantech PCI-1760 registers */
153 #define OMB0 0x0c /* W: Mailbox outgoing registers */
154 #define OMB1 0x0d
155 #define OMB2 0x0e
156 #define OMB3 0x0f
157 #define IMB0 0x1c /* R: Mailbox incoming registers */
158 #define IMB1 0x1d
159 #define IMB2 0x1e
160 #define IMB3 0x1f
161 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
162 #define INTCSR1 0x39
163 #define INTCSR2 0x3a
164 #define INTCSR3 0x3b
165 
166 /* PCI-1760 mailbox commands */
167 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
168  * DI status in IMB3 */
169 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
170 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
171 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
172  * register in OMB0, result in IMB0 */
173 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
174  * IMB1.IMB0 */
175 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
176  * IMB1.IMB0 */
177 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
178  * OMB0 */
179 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
180  * bits in OMB0 */
181 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
182  * bits in OMB0 */
183 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
184  * OMB0 */
185 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
186  * OMB0 to its reset values */
187 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
188  * interrupts based on bits in OMB0 */
189 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
190  * interrupts based on bits in OMB0 */
191 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
192  * - rising, =1 - falling) */
193 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
194  * value */
195 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
196  * 256*OMB1+OMB0 */
197 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
198  * 256*OMB1+OMB0 */
199 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
200  * 256*OMB1+OMB0 */
201 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
202  * 256*OMB1+OMB0 */
203 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
204  * 256*OMB1+OMB0 */
205 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
206  * 256*OMB1+OMB0 */
207 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
208  * 256*OMB1+OMB0 */
209 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
210  * 256*OMB1+OMB0 */
211 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
212  * 256*OMB1+OMB0 */
213 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
214  * 256*OMB1+OMB0 */
215 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
216  * 256*OMB1+OMB0 */
217 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
218  * 256*OMB1+OMB0 */
219 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
220  * 256*OMB1+OMB0 */
221 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
222  * 256*OMB1+OMB0 */
223 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
224  * 256*OMB1+OMB0 */
225 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
226  * 256*OMB1+OMB0 */
227 
228 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
229 
230 struct diosubd_data {
231  int chans; /* num of chans */
232  int addr; /* PCI address ofset */
233  int regs; /* number of registers to read or 8255
234  subdevices or 8254 chips */
235  unsigned int specflags; /* addon subdevice flags */
236 };
237 
238 struct dio_boardtype {
239  const char *name; /* board name */
240  int vendor_id; /* vendor/device PCI ID */
241  int device_id;
242  int main_pci_region; /* main I/O PCI region */
243  enum hw_cards_id cardtype;
244  int nsubdevs;
245  struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */
246  struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */
247  struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */
248  struct diosubd_data boardid; /* card supports board ID switch */
249  struct diosubd_data s8254[MAX_8254_SUBDEVS]; /* 8254 subdevices */
250  enum hw_io_access io_access;
251 };
252 
253 static const struct dio_boardtype boardtypes[] = {
254  {
255  .name = "pci1730",
256  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
257  .device_id = 0x1730,
258  .main_pci_region = PCIDIO_MAINREG,
259  .cardtype = TYPE_PCI1730,
260  .nsubdevs = 5,
261  .sdi[0] = { 16, PCI1730_DI, 2, 0, },
262  .sdi[1] = { 16, PCI1730_IDI, 2, 0, },
263  .sdo[0] = { 16, PCI1730_DO, 2, 0, },
264  .sdo[1] = { 16, PCI1730_IDO, 2, 0, },
265  .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
266  .io_access = IO_8b,
267  }, {
268  .name = "pci1733",
269  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
270  .device_id = 0x1733,
271  .main_pci_region = PCIDIO_MAINREG,
272  .cardtype = TYPE_PCI1733,
273  .nsubdevs = 2,
274  .sdi[1] = { 32, PCI1733_IDI, 4, 0, },
275  .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
276  .io_access = IO_8b,
277  }, {
278  .name = "pci1734",
279  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
280  .device_id = 0x1734,
281  .main_pci_region = PCIDIO_MAINREG,
282  .cardtype = TYPE_PCI1734,
283  .nsubdevs = 2,
284  .sdo[1] = { 32, PCI1734_IDO, 4, 0, },
285  .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
286  .io_access = IO_8b,
287  }, {
288  .name = "pci1735",
289  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
290  .device_id = 0x1735,
291  .main_pci_region = PCIDIO_MAINREG,
292  .cardtype = TYPE_PCI1735,
293  .nsubdevs = 4,
294  .sdi[0] = { 32, PCI1735_DI, 4, 0, },
295  .sdo[0] = { 32, PCI1735_DO, 4, 0, },
296  .boardid = { 4, PCI1735_BOARDID, 1, SDF_INTERNAL, },
297  .s8254[0] = { 3, PCI1735_C8254, 1, 0, },
298  .io_access = IO_8b,
299  }, {
300  .name = "pci1736",
301  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
302  .device_id = 0x1736,
303  .main_pci_region = PCI1736_MAINREG,
304  .cardtype = TYPE_PCI1736,
305  .nsubdevs = 3,
306  .sdi[1] = { 16, PCI1736_IDI, 2, 0, },
307  .sdo[1] = { 16, PCI1736_IDO, 2, 0, },
308  .boardid = { 4, PCI1736_BOARDID, 1, SDF_INTERNAL, },
309  .io_access = IO_8b,
310  }, {
311  .name = "pci1739",
312  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
313  .device_id = 0x1739,
314  .main_pci_region = PCIDIO_MAINREG,
315  .cardtype = TYPE_PCI1739,
316  .nsubdevs = 2,
317  .sdio[0] = { 48, PCI1739_DIO, 2, 0, },
318  .io_access = IO_8b,
319  }, {
320  .name = "pci1750",
321  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
322  .device_id = 0x1750,
323  .main_pci_region = PCIDIO_MAINREG,
324  .cardtype = TYPE_PCI1750,
325  .nsubdevs = 2,
326  .sdi[1] = { 16, PCI1750_IDI, 2, 0, },
327  .sdo[1] = { 16, PCI1750_IDO, 2, 0, },
328  .io_access = IO_8b,
329  }, {
330  .name = "pci1751",
331  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
332  .device_id = 0x1751,
333  .main_pci_region = PCIDIO_MAINREG,
334  .cardtype = TYPE_PCI1751,
335  .nsubdevs = 3,
336  .sdio[0] = { 48, PCI1751_DIO, 2, 0, },
337  .s8254[0] = { 3, PCI1751_CNT, 1, 0, },
338  .io_access = IO_8b,
339  }, {
340  .name = "pci1752",
341  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
342  .device_id = 0x1752,
343  .main_pci_region = PCIDIO_MAINREG,
344  .cardtype = TYPE_PCI1752,
345  .nsubdevs = 3,
346  .sdo[0] = { 32, PCI1752_IDO, 2, 0, },
347  .sdo[1] = { 32, PCI1752_IDO2, 2, 0, },
348  .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
349  .io_access = IO_16b,
350  }, {
351  .name = "pci1753",
352  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
353  .device_id = 0x1753,
354  .main_pci_region = PCIDIO_MAINREG,
355  .cardtype = TYPE_PCI1753,
356  .nsubdevs = 4,
357  .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
358  .io_access = IO_8b,
359  }, {
360  .name = "pci1753e",
361  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
362  .device_id = 0x1753,
363  .main_pci_region = PCIDIO_MAINREG,
364  .cardtype = TYPE_PCI1753E,
365  .nsubdevs = 8,
366  .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
367  .sdio[1] = { 96, PCI1753E_DIO, 4, 0, },
368  .io_access = IO_8b,
369  }, {
370  .name = "pci1754",
371  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
372  .device_id = 0x1754,
373  .main_pci_region = PCIDIO_MAINREG,
374  .cardtype = TYPE_PCI1754,
375  .nsubdevs = 3,
376  .sdi[0] = { 32, PCI1754_IDI, 2, 0, },
377  .sdi[1] = { 32, PCI1754_IDI2, 2, 0, },
378  .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
379  .io_access = IO_16b,
380  }, {
381  .name = "pci1756",
382  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
383  .device_id = 0x1756,
384  .main_pci_region = PCIDIO_MAINREG,
385  .cardtype = TYPE_PCI1756,
386  .nsubdevs = 3,
387  .sdi[1] = { 32, PCI1756_IDI, 2, 0, },
388  .sdo[1] = { 32, PCI1756_IDO, 2, 0, },
389  .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
390  .io_access = IO_16b,
391  }, {
392  /* This card has its own 'attach' */
393  .name = "pci1760",
394  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
395  .device_id = 0x1760,
396  .main_pci_region = 0,
397  .cardtype = TYPE_PCI1760,
398  .nsubdevs = 4,
399  .io_access = IO_8b,
400  }, {
401  .name = "pci1762",
402  .vendor_id = PCI_VENDOR_ID_ADVANTECH,
403  .device_id = 0x1762,
404  .main_pci_region = PCIDIO_MAINREG,
405  .cardtype = TYPE_PCI1762,
406  .nsubdevs = 3,
407  .sdi[1] = { 16, PCI1762_IDI, 1, 0, },
408  .sdo[1] = { 16, PCI1762_RO, 1, 0, },
409  .boardid = { 4, PCI1762_BOARDID, 1, SDF_INTERNAL, },
410  .io_access = IO_16b,
411  },
412 };
413 
414 struct pci_dio_private {
415  char valid; /* card is usable */
416  char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
417  /* PCI-1760 specific data */
418  unsigned char IDICntEnable; /* counter's counting enable status */
419  unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
420  * status */
421  unsigned char IDICntMatchEnable; /* counter's match interrupts
422  * enable status */
423  unsigned char IDICntEdge; /* counter's count edge value
424  * (bit=0 - rising, =1 - falling) */
425  unsigned short CntResValue[8]; /* counters' reset value */
426  unsigned short CntMatchValue[8]; /* counters' match interrupt value */
427  unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
428  unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */
429  unsigned char IDIPatMatchValue; /* IDI's pattern match value */
430  unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */
431  unsigned short IDIFiltrHigh[8]; /* IDI's filter value high signal */
432 };
433 
434 /*
435 ==============================================================================
436 */
437 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
438  struct comedi_subdevice *s,
439  struct comedi_insn *insn, unsigned int *data)
440 {
441  const struct diosubd_data *d = (const struct diosubd_data *)s->private;
442  int i;
443 
444  data[1] = 0;
445  for (i = 0; i < d->regs; i++)
446  data[1] |= inb(dev->iobase + d->addr + i) << (8 * i);
447 
448 
449  return insn->n;
450 }
451 
452 /*
453 ==============================================================================
454 */
455 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
456  struct comedi_subdevice *s,
457  struct comedi_insn *insn, unsigned int *data)
458 {
459  const struct diosubd_data *d = (const struct diosubd_data *)s->private;
460  int i;
461 
462  data[1] = 0;
463  for (i = 0; i < d->regs; i++)
464  data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i);
465 
466  return insn->n;
467 }
468 
469 /*
470 ==============================================================================
471 */
472 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
473  struct comedi_subdevice *s,
474  struct comedi_insn *insn, unsigned int *data)
475 {
476  const struct diosubd_data *d = (const struct diosubd_data *)s->private;
477  int i;
478 
479  if (data[0]) {
480  s->state &= ~data[0];
481  s->state |= (data[0] & data[1]);
482  for (i = 0; i < d->regs; i++)
483  outb((s->state >> (8 * i)) & 0xff,
484  dev->iobase + d->addr + i);
485  }
486  data[1] = s->state;
487 
488  return insn->n;
489 }
490 
491 /*
492 ==============================================================================
493 */
494 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
495  struct comedi_subdevice *s,
496  struct comedi_insn *insn, unsigned int *data)
497 {
498  const struct diosubd_data *d = (const struct diosubd_data *)s->private;
499  int i;
500 
501  if (data[0]) {
502  s->state &= ~data[0];
503  s->state |= (data[0] & data[1]);
504  for (i = 0; i < d->regs; i++)
505  outw((s->state >> (16 * i)) & 0xffff,
506  dev->iobase + d->addr + 2 * i);
507  }
508  data[1] = s->state;
509 
510  return insn->n;
511 }
512 
513 /*
514 ==============================================================================
515 */
516 static int pci_8254_insn_read(struct comedi_device *dev,
517  struct comedi_subdevice *s,
518  struct comedi_insn *insn, unsigned int *data)
519 {
520  const struct diosubd_data *d = (const struct diosubd_data *)s->private;
521  unsigned int chan, chip, chipchan;
522  unsigned long flags;
523 
524  chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
525  chip = chan / 3; /* chip on subdevice */
526  chipchan = chan - (3 * chip); /* channel on chip on subdevice */
527  spin_lock_irqsave(&s->spin_lock, flags);
528  data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip),
529  0, chipchan);
530  spin_unlock_irqrestore(&s->spin_lock, flags);
531  return 1;
532 }
533 
534 /*
535 ==============================================================================
536 */
537 static int pci_8254_insn_write(struct comedi_device *dev,
538  struct comedi_subdevice *s,
539  struct comedi_insn *insn, unsigned int *data)
540 {
541  const struct diosubd_data *d = (const struct diosubd_data *)s->private;
542  unsigned int chan, chip, chipchan;
543  unsigned long flags;
544 
545  chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
546  chip = chan / 3; /* chip on subdevice */
547  chipchan = chan - (3 * chip); /* channel on chip on subdevice */
548  spin_lock_irqsave(&s->spin_lock, flags);
549  i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip),
550  0, chipchan, data[0]);
551  spin_unlock_irqrestore(&s->spin_lock, flags);
552  return 1;
553 }
554 
555 /*
556 ==============================================================================
557 */
558 static int pci_8254_insn_config(struct comedi_device *dev,
559  struct comedi_subdevice *s,
560  struct comedi_insn *insn, unsigned int *data)
561 {
562  const struct diosubd_data *d = (const struct diosubd_data *)s->private;
563  unsigned int chan, chip, chipchan;
564  unsigned long iobase;
565  int ret = 0;
566  unsigned long flags;
567 
568  chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
569  chip = chan / 3; /* chip on subdevice */
570  chipchan = chan - (3 * chip); /* channel on chip on subdevice */
571  iobase = dev->iobase + d->addr + (SIZE_8254 * chip);
572  spin_lock_irqsave(&s->spin_lock, flags);
573  switch (data[0]) {
574  case INSN_CONFIG_SET_COUNTER_MODE:
575  ret = i8254_set_mode(iobase, 0, chipchan, data[1]);
576  if (ret < 0)
577  ret = -EINVAL;
578  break;
579  case INSN_CONFIG_8254_READ_STATUS:
580  data[1] = i8254_status(iobase, 0, chipchan);
581  break;
582  default:
583  ret = -EINVAL;
584  break;
585  }
586  spin_unlock_irqrestore(&s->spin_lock, flags);
587  return ret < 0 ? ret : insn->n;
588 }
589 
590 /*
591 ==============================================================================
592 */
593 static int pci1760_unchecked_mbxrequest(struct comedi_device *dev,
594  unsigned char *omb, unsigned char *imb,
595  int repeats)
596 {
597  int cnt, tout, ok = 0;
598 
599  for (cnt = 0; cnt < repeats; cnt++) {
600  outb(omb[0], dev->iobase + OMB0);
601  outb(omb[1], dev->iobase + OMB1);
602  outb(omb[2], dev->iobase + OMB2);
603  outb(omb[3], dev->iobase + OMB3);
604  for (tout = 0; tout < 251; tout++) {
605  imb[2] = inb(dev->iobase + IMB2);
606  if (imb[2] == omb[2]) {
607  imb[0] = inb(dev->iobase + IMB0);
608  imb[1] = inb(dev->iobase + IMB1);
609  imb[3] = inb(dev->iobase + IMB3);
610  ok = 1;
611  break;
612  }
613  udelay(1);
614  }
615  if (ok)
616  return 0;
617  }
618 
619  comedi_error(dev, "PCI-1760 mailbox request timeout!");
620  return -ETIME;
621 }
622 
623 static int pci1760_clear_imb2(struct comedi_device *dev)
624 {
625  unsigned char omb[4] = { 0x0, 0x0, CMD_ClearIMB2, 0x0 };
626  unsigned char imb[4];
627  /* check if imb2 is already clear */
628  if (inb(dev->iobase + IMB2) == CMD_ClearIMB2)
629  return 0;
630  return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
631 }
632 
633 static int pci1760_mbxrequest(struct comedi_device *dev,
634  unsigned char *omb, unsigned char *imb)
635 {
636  if (omb[2] == CMD_ClearIMB2) {
637  comedi_error(dev,
638  "bug! this function should not be used for CMD_ClearIMB2 command");
639  return -EINVAL;
640  }
641  if (inb(dev->iobase + IMB2) == omb[2]) {
642  int retval;
643  retval = pci1760_clear_imb2(dev);
644  if (retval < 0)
645  return retval;
646  }
647  return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
648 }
649 
650 /*
651 ==============================================================================
652 */
653 static int pci1760_insn_bits_di(struct comedi_device *dev,
654  struct comedi_subdevice *s,
655  struct comedi_insn *insn, unsigned int *data)
656 {
657  data[1] = inb(dev->iobase + IMB3);
658 
659  return insn->n;
660 }
661 
662 /*
663 ==============================================================================
664 */
665 static int pci1760_insn_bits_do(struct comedi_device *dev,
666  struct comedi_subdevice *s,
667  struct comedi_insn *insn, unsigned int *data)
668 {
669  int ret;
670  unsigned char omb[4] = {
671  0x00,
672  0x00,
673  CMD_SetRelaysOutput,
674  0x00
675  };
676  unsigned char imb[4];
677 
678  if (data[0]) {
679  s->state &= ~data[0];
680  s->state |= (data[0] & data[1]);
681  omb[0] = s->state;
682  ret = pci1760_mbxrequest(dev, omb, imb);
683  if (!ret)
684  return ret;
685  }
686  data[1] = s->state;
687 
688  return insn->n;
689 }
690 
691 /*
692 ==============================================================================
693 */
694 static int pci1760_insn_cnt_read(struct comedi_device *dev,
695  struct comedi_subdevice *s,
696  struct comedi_insn *insn, unsigned int *data)
697 {
698  int ret, n;
699  unsigned char omb[4] = {
700  CR_CHAN(insn->chanspec) & 0x07,
701  0x00,
702  CMD_GetIDICntCurValue,
703  0x00
704  };
705  unsigned char imb[4];
706 
707  for (n = 0; n < insn->n; n++) {
708  ret = pci1760_mbxrequest(dev, omb, imb);
709  if (!ret)
710  return ret;
711  data[n] = (imb[1] << 8) + imb[0];
712  }
713 
714  return n;
715 }
716 
717 /*
718 ==============================================================================
719 */
720 static int pci1760_insn_cnt_write(struct comedi_device *dev,
721  struct comedi_subdevice *s,
722  struct comedi_insn *insn, unsigned int *data)
723 {
724  struct pci_dio_private *devpriv = dev->private;
725  int ret;
726  unsigned char chan = CR_CHAN(insn->chanspec) & 0x07;
727  unsigned char bitmask = 1 << chan;
728  unsigned char omb[4] = {
729  data[0] & 0xff,
730  (data[0] >> 8) & 0xff,
731  CMD_SetIDI0CntResetValue + chan,
732  0x00
733  };
734  unsigned char imb[4];
735 
736  /* Set reset value if different */
737  if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
738  ret = pci1760_mbxrequest(dev, omb, imb);
739  if (!ret)
740  return ret;
741  devpriv->CntResValue[chan] = data[0] & 0xffff;
742  }
743 
744  omb[0] = bitmask; /* reset counter to it reset value */
745  omb[2] = CMD_ResetIDICounters;
746  ret = pci1760_mbxrequest(dev, omb, imb);
747  if (!ret)
748  return ret;
749 
750  /* start counter if it don't run */
751  if (!(bitmask & devpriv->IDICntEnable)) {
752  omb[0] = bitmask;
753  omb[2] = CMD_EnableIDICounters;
754  ret = pci1760_mbxrequest(dev, omb, imb);
755  if (!ret)
756  return ret;
757  devpriv->IDICntEnable |= bitmask;
758  }
759  return 1;
760 }
761 
762 /*
763 ==============================================================================
764 */
765 static int pci1760_reset(struct comedi_device *dev)
766 {
767  struct pci_dio_private *devpriv = dev->private;
768  int i;
769  unsigned char omb[4] = { 0x00, 0x00, 0x00, 0x00 };
770  unsigned char imb[4];
771 
772  outb(0, dev->iobase + INTCSR0); /* disable IRQ */
773  outb(0, dev->iobase + INTCSR1);
774  outb(0, dev->iobase + INTCSR2);
775  outb(0, dev->iobase + INTCSR3);
776  devpriv->GlobalIrqEnabled = 0;
777 
778  omb[0] = 0x00;
779  omb[2] = CMD_SetRelaysOutput; /* reset relay outputs */
780  pci1760_mbxrequest(dev, omb, imb);
781 
782  omb[0] = 0x00;
783  omb[2] = CMD_EnableIDICounters; /* disable IDI up counters */
784  pci1760_mbxrequest(dev, omb, imb);
785  devpriv->IDICntEnable = 0;
786 
787  omb[0] = 0x00;
788  omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
789  * interrupts */
790  pci1760_mbxrequest(dev, omb, imb);
791  devpriv->IDICntOverEnable = 0;
792 
793  omb[0] = 0x00;
794  omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
795  * interrupts */
796  pci1760_mbxrequest(dev, omb, imb);
797  devpriv->IDICntMatchEnable = 0;
798 
799  omb[0] = 0x00;
800  omb[1] = 0x80;
801  for (i = 0; i < 8; i++) { /* set IDI up counters match value */
802  omb[2] = CMD_SetIDI0CntMatchValue + i;
803  pci1760_mbxrequest(dev, omb, imb);
804  devpriv->CntMatchValue[i] = 0x8000;
805  }
806 
807  omb[0] = 0x00;
808  omb[1] = 0x00;
809  for (i = 0; i < 8; i++) { /* set IDI up counters reset value */
810  omb[2] = CMD_SetIDI0CntResetValue + i;
811  pci1760_mbxrequest(dev, omb, imb);
812  devpriv->CntResValue[i] = 0x0000;
813  }
814 
815  omb[0] = 0xff;
816  omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
817  * values */
818  pci1760_mbxrequest(dev, omb, imb);
819 
820  omb[0] = 0x00;
821  omb[2] = CMD_EdgeIDICounters; /* set IDI up counters count edge */
822  pci1760_mbxrequest(dev, omb, imb);
823  devpriv->IDICntEdge = 0x00;
824 
825  omb[0] = 0x00;
826  omb[2] = CMD_EnableIDIFilters; /* disable all digital in filters */
827  pci1760_mbxrequest(dev, omb, imb);
828  devpriv->IDIFiltersEn = 0x00;
829 
830  omb[0] = 0x00;
831  omb[2] = CMD_EnableIDIPatternMatch; /* disable pattern matching */
832  pci1760_mbxrequest(dev, omb, imb);
833  devpriv->IDIPatMatchEn = 0x00;
834 
835  omb[0] = 0x00;
836  omb[2] = CMD_SetIDIPatternMatch; /* set pattern match value */
837  pci1760_mbxrequest(dev, omb, imb);
838  devpriv->IDIPatMatchValue = 0x00;
839 
840  return 0;
841 }
842 
843 /*
844 ==============================================================================
845 */
846 static int pci_dio_reset(struct comedi_device *dev)
847 {
848  const struct dio_boardtype *this_board = comedi_board(dev);
849 
850  switch (this_board->cardtype) {
851  case TYPE_PCI1730:
852  outb(0, dev->iobase + PCI1730_DO); /* clear outputs */
853  outb(0, dev->iobase + PCI1730_DO + 1);
854  outb(0, dev->iobase + PCI1730_IDO);
855  outb(0, dev->iobase + PCI1730_IDO + 1);
856  /* NO break there! */
857  case TYPE_PCI1733:
858  /* disable interrupts */
859  outb(0, dev->iobase + PCI1730_3_INT_EN);
860  /* clear interrupts */
861  outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
862  /* set rising edge trigger */
863  outb(0, dev->iobase + PCI1730_3_INT_RF);
864  break;
865  case TYPE_PCI1734:
866  outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
867  outb(0, dev->iobase + PCI1734_IDO + 1);
868  outb(0, dev->iobase + PCI1734_IDO + 2);
869  outb(0, dev->iobase + PCI1734_IDO + 3);
870  break;
871  case TYPE_PCI1735:
872  outb(0, dev->iobase + PCI1735_DO); /* clear outputs */
873  outb(0, dev->iobase + PCI1735_DO + 1);
874  outb(0, dev->iobase + PCI1735_DO + 2);
875  outb(0, dev->iobase + PCI1735_DO + 3);
876  i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 0, I8254_MODE0);
877  i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 1, I8254_MODE0);
878  i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 2, I8254_MODE0);
879  break;
880 
881  case TYPE_PCI1736:
882  outb(0, dev->iobase + PCI1736_IDO);
883  outb(0, dev->iobase + PCI1736_IDO + 1);
884  /* disable interrupts */
885  outb(0, dev->iobase + PCI1736_3_INT_EN);
886  /* clear interrupts */
887  outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
888  /* set rising edge trigger */
889  outb(0, dev->iobase + PCI1736_3_INT_RF);
890  break;
891 
892  case TYPE_PCI1739:
893  /* disable & clear interrupts */
894  outb(0x88, dev->iobase + PCI1739_ICR);
895  break;
896 
897  case TYPE_PCI1750:
898  case TYPE_PCI1751:
899  /* disable & clear interrupts */
900  outb(0x88, dev->iobase + PCI1750_ICR);
901  break;
902  case TYPE_PCI1752:
903  outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
904  * function */
905  outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
906  outw(0, dev->iobase + PCI1752_IDO + 2);
907  outw(0, dev->iobase + PCI1752_IDO2);
908  outw(0, dev->iobase + PCI1752_IDO2 + 2);
909  break;
910  case TYPE_PCI1753E:
911  outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
912  * interrupts */
913  outb(0x80, dev->iobase + PCI1753E_ICR1);
914  outb(0x80, dev->iobase + PCI1753E_ICR2);
915  outb(0x80, dev->iobase + PCI1753E_ICR3);
916  /* NO break there! */
917  case TYPE_PCI1753:
918  outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
919  * interrupts */
920  outb(0x80, dev->iobase + PCI1753_ICR1);
921  outb(0x80, dev->iobase + PCI1753_ICR2);
922  outb(0x80, dev->iobase + PCI1753_ICR3);
923  break;
924  case TYPE_PCI1754:
925  outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
926  * interrupts */
927  outw(0x08, dev->iobase + PCI1754_6_ICR1);
928  outw(0x08, dev->iobase + PCI1754_ICR2);
929  outw(0x08, dev->iobase + PCI1754_ICR3);
930  break;
931  case TYPE_PCI1756:
932  outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
933  * function */
934  outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
935  * interrupts */
936  outw(0x08, dev->iobase + PCI1754_6_ICR1);
937  outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
938  outw(0, dev->iobase + PCI1756_IDO + 2);
939  break;
940  case TYPE_PCI1760:
941  pci1760_reset(dev);
942  break;
943  case TYPE_PCI1762:
944  outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
945  * interrupts */
946  break;
947  }
948 
949  return 0;
950 }
951 
952 /*
953 ==============================================================================
954 */
955 static int pci1760_attach(struct comedi_device *dev)
956 {
957  struct comedi_subdevice *s;
958 
959  s = &dev->subdevices[0];
960  s->type = COMEDI_SUBD_DI;
961  s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON;
962  s->n_chan = 8;
963  s->maxdata = 1;
964  s->len_chanlist = 8;
965  s->range_table = &range_digital;
966  s->insn_bits = pci1760_insn_bits_di;
967 
968  s = &dev->subdevices[1];
969  s->type = COMEDI_SUBD_DO;
970  s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
971  s->n_chan = 8;
972  s->maxdata = 1;
973  s->len_chanlist = 8;
974  s->range_table = &range_digital;
975  s->state = 0;
976  s->insn_bits = pci1760_insn_bits_do;
977 
978  s = &dev->subdevices[2];
979  s->type = COMEDI_SUBD_TIMER;
980  s->subdev_flags = SDF_WRITABLE | SDF_LSAMPL;
981  s->n_chan = 2;
982  s->maxdata = 0xffffffff;
983  s->len_chanlist = 2;
984 /* s->insn_config=pci1760_insn_pwm_cfg; */
985 
986  s = &dev->subdevices[3];
987  s->type = COMEDI_SUBD_COUNTER;
988  s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
989  s->n_chan = 8;
990  s->maxdata = 0xffff;
991  s->len_chanlist = 8;
992  s->insn_read = pci1760_insn_cnt_read;
993  s->insn_write = pci1760_insn_cnt_write;
994 /* s->insn_config=pci1760_insn_cnt_cfg; */
995 
996  return 0;
997 }
998 
999 /*
1000 ==============================================================================
1001 */
1002 static int pci_dio_add_di(struct comedi_device *dev,
1003  struct comedi_subdevice *s,
1004  const struct diosubd_data *d)
1005 {
1006  const struct dio_boardtype *this_board = comedi_board(dev);
1007 
1008  s->type = COMEDI_SUBD_DI;
1009  s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | d->specflags;
1010  if (d->chans > 16)
1011  s->subdev_flags |= SDF_LSAMPL;
1012  s->n_chan = d->chans;
1013  s->maxdata = 1;
1014  s->len_chanlist = d->chans;
1015  s->range_table = &range_digital;
1016  switch (this_board->io_access) {
1017  case IO_8b:
1018  s->insn_bits = pci_dio_insn_bits_di_b;
1019  break;
1020  case IO_16b:
1021  s->insn_bits = pci_dio_insn_bits_di_w;
1022  break;
1023  }
1024  s->private = (void *)d;
1025 
1026  return 0;
1027 }
1028 
1029 /*
1030 ==============================================================================
1031 */
1032 static int pci_dio_add_do(struct comedi_device *dev,
1033  struct comedi_subdevice *s,
1034  const struct diosubd_data *d)
1035 {
1036  const struct dio_boardtype *this_board = comedi_board(dev);
1037 
1038  s->type = COMEDI_SUBD_DO;
1039  s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
1040  if (d->chans > 16)
1041  s->subdev_flags |= SDF_LSAMPL;
1042  s->n_chan = d->chans;
1043  s->maxdata = 1;
1044  s->len_chanlist = d->chans;
1045  s->range_table = &range_digital;
1046  s->state = 0;
1047  switch (this_board->io_access) {
1048  case IO_8b:
1049  s->insn_bits = pci_dio_insn_bits_do_b;
1050  break;
1051  case IO_16b:
1052  s->insn_bits = pci_dio_insn_bits_do_w;
1053  break;
1054  }
1055  s->private = (void *)d;
1056 
1057  return 0;
1058 }
1059 
1060 /*
1061 ==============================================================================
1062 */
1063 static int pci_dio_add_8254(struct comedi_device *dev,
1064  struct comedi_subdevice *s,
1065  const struct diosubd_data *d)
1066 {
1067  s->type = COMEDI_SUBD_COUNTER;
1068  s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1069  s->n_chan = d->chans;
1070  s->maxdata = 65535;
1071  s->len_chanlist = d->chans;
1072  s->insn_read = pci_8254_insn_read;
1073  s->insn_write = pci_8254_insn_write;
1074  s->insn_config = pci_8254_insn_config;
1075  s->private = (void *)d;
1076 
1077  return 0;
1078 }
1079 
1080 static const void *pci_dio_find_boardinfo(struct comedi_device *dev,
1081  struct pci_dev *pcidev)
1082 {
1083  const struct dio_boardtype *this_board;
1084  int i;
1085 
1086  for (i = 0; i < ARRAY_SIZE(boardtypes); ++i) {
1087  this_board = &boardtypes[i];
1088  if (this_board->vendor_id == pcidev->vendor &&
1089  this_board->device_id == pcidev->device)
1090  return this_board;
1091  }
1092  return NULL;
1093 }
1094 
1095 static int pci_dio_attach_pci(struct comedi_device *dev,
1096  struct pci_dev *pcidev)
1097 {
1098  const struct dio_boardtype *this_board;
1099  struct pci_dio_private *devpriv;
1100  struct comedi_subdevice *s;
1101  int ret, subdev, i, j;
1102 
1103  comedi_set_hw_dev(dev, &pcidev->dev);
1104 
1105  this_board = pci_dio_find_boardinfo(dev, pcidev);
1106  if (!this_board)
1107  return -ENODEV;
1108  dev->board_ptr = this_board;
1109  dev->board_name = this_board->name;
1110 
1111  ret = alloc_private(dev, sizeof(*devpriv));
1112  if (ret < 0)
1113  return ret;
1114  devpriv = dev->private;
1115 
1116  ret = comedi_pci_enable(pcidev, dev->board_name);
1117  if (ret)
1118  return ret;
1119  dev->iobase = pci_resource_start(pcidev, this_board->main_pci_region);
1120 
1121  ret = comedi_alloc_subdevices(dev, this_board->nsubdevs);
1122  if (ret)
1123  return ret;
1124 
1125  subdev = 0;
1126  for (i = 0; i < MAX_DI_SUBDEVS; i++)
1127  if (this_board->sdi[i].chans) {
1128  s = &dev->subdevices[subdev];
1129  pci_dio_add_di(dev, s, &this_board->sdi[i]);
1130  subdev++;
1131  }
1132 
1133  for (i = 0; i < MAX_DO_SUBDEVS; i++)
1134  if (this_board->sdo[i].chans) {
1135  s = &dev->subdevices[subdev];
1136  pci_dio_add_do(dev, s, &this_board->sdo[i]);
1137  subdev++;
1138  }
1139 
1140  for (i = 0; i < MAX_DIO_SUBDEVG; i++)
1141  for (j = 0; j < this_board->sdio[i].regs; j++) {
1142  s = &dev->subdevices[subdev];
1143  subdev_8255_init(dev, s, NULL,
1144  dev->iobase +
1145  this_board->sdio[i].addr +
1146  SIZE_8255 * j);
1147  subdev++;
1148  }
1149 
1150  if (this_board->boardid.chans) {
1151  s = &dev->subdevices[subdev];
1152  s->type = COMEDI_SUBD_DI;
1153  pci_dio_add_di(dev, s, &this_board->boardid);
1154  subdev++;
1155  }
1156 
1157  for (i = 0; i < MAX_8254_SUBDEVS; i++)
1158  if (this_board->s8254[i].chans) {
1159  s = &dev->subdevices[subdev];
1160  pci_dio_add_8254(dev, s, &this_board->s8254[i]);
1161  subdev++;
1162  }
1163 
1164  if (this_board->cardtype == TYPE_PCI1760)
1165  pci1760_attach(dev);
1166 
1167  devpriv->valid = 1;
1168 
1169  pci_dio_reset(dev);
1170 
1171  return 0;
1172 }
1173 
1174 static void pci_dio_detach(struct comedi_device *dev)
1175 {
1176  struct pci_dio_private *devpriv = dev->private;
1177  struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1178  struct comedi_subdevice *s;
1179  int i;
1180 
1181  if (devpriv) {
1182  if (devpriv->valid)
1183  pci_dio_reset(dev);
1184  }
1185  if (dev->subdevices) {
1186  for (i = 0; i < dev->n_subdevices; i++) {
1187  s = &dev->subdevices[i];
1188  if (s->type == COMEDI_SUBD_DIO)
1189  subdev_8255_cleanup(dev, s);
1190  s->private = NULL;
1191  }
1192  }
1193  if (pcidev) {
1194  if (dev->iobase)
1195  comedi_pci_disable(pcidev);
1196  }
1197 }
1198 
1199 static struct comedi_driver adv_pci_dio_driver = {
1200  .driver_name = "adv_pci_dio",
1201  .module = THIS_MODULE,
1202  .attach_pci = pci_dio_attach_pci,
1203  .detach = pci_dio_detach,
1204 };
1205 
1206 static int __devinit adv_pci_dio_pci_probe(struct pci_dev *dev,
1207  const struct pci_device_id *ent)
1208 {
1209  return comedi_pci_auto_config(dev, &adv_pci_dio_driver);
1210 }
1211 
1212 static void __devexit adv_pci_dio_pci_remove(struct pci_dev *dev)
1213 {
1214  comedi_pci_auto_unconfig(dev);
1215 }
1216 
1217 static DEFINE_PCI_DEVICE_TABLE(adv_pci_dio_pci_table) = {
1218  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1730) },
1219  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1733) },
1220  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1734) },
1221  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1735) },
1222  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1736) },
1223  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1739) },
1224  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1750) },
1225  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1751) },
1226  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1752) },
1227  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1753) },
1228  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1754) },
1229  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1756) },
1230  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1760) },
1231  { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1762) },
1232  { 0 }
1233 };
1234 MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
1235 
1236 static struct pci_driver adv_pci_dio_pci_driver = {
1237  .name = "adv_pci_dio",
1238  .id_table = adv_pci_dio_pci_table,
1239  .probe = adv_pci_dio_pci_probe,
1240  .remove = __devexit_p(adv_pci_dio_pci_remove),
1241 };
1242 module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
1243 
1244 MODULE_AUTHOR("Comedi http://www.comedi.org");
1245 MODULE_DESCRIPTION("Comedi low-level driver");
1246 MODULE_LICENSE("GPL");
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