12 #include <linux/kernel.h>
16 #include <linux/device.h>
18 #include <linux/sched.h>
19 #include <linux/serial_core.h>
22 #include <linux/export.h>
26 #include <asm/proc-fns.h>
27 #include <asm/exception.h>
32 #include <asm/cacheflush.h>
34 #include <mach/regs-irq.h>
36 #include <mach/regs-gpio.h>
40 #include <plat/clock.h>
54 #define L2_AUX_VAL 0x7C470001
55 #define L2_AUX_MASK 0xC200ffff
57 static const char name_exynos4210[] =
"EXYNOS4210";
58 static const char name_exynos4212[] =
"EXYNOS4212";
59 static const char name_exynos4412[] =
"EXYNOS4412";
60 static const char name_exynos5250[] =
"EXYNOS5250";
62 static void exynos4_map_io(
void);
63 static void exynos5_map_io(
void);
64 static void exynos4_init_clocks(
int xtal);
65 static void exynos5_init_clocks(
int xtal);
67 static int exynos_init(
void);
73 .map_io = exynos4_map_io,
74 .init_clocks = exynos4_init_clocks,
75 .init_uarts = exynos_init_uarts,
77 .name = name_exynos4210,
81 .map_io = exynos4_map_io,
82 .init_clocks = exynos4_init_clocks,
83 .init_uarts = exynos_init_uarts,
85 .name = name_exynos4212,
89 .map_io = exynos4_map_io,
90 .init_clocks = exynos4_init_clocks,
91 .init_uarts = exynos_init_uarts,
93 .name = name_exynos4412,
97 .map_io = exynos5_map_io,
98 .init_clocks = exynos5_init_clocks,
99 .init_uarts = exynos_init_uarts,
101 .name = name_exynos5250,
107 static struct map_desc exynos_iodesc[] __initdata = {
116 static struct map_desc exynos4_iodesc[] __initdata = {
200 static struct map_desc exynos4_iodesc0[] __initdata = {
209 static struct map_desc exynos4_iodesc1[] __initdata = {
218 static struct map_desc exynos5_iodesc[] __initdata = {
252 .length = 144 *
SZ_1K,
316 static void __init exynos4_map_io(
void)
326 exynos4_default_sdhci0();
327 exynos4_default_sdhci1();
328 exynos4_default_sdhci2();
329 exynos4_default_sdhci3();
331 s3c_adc_setname(
"samsung-adc-v3");
333 s3c_fimc_setname(0,
"exynos4-fimc");
334 s3c_fimc_setname(1,
"exynos4-fimc");
335 s3c_fimc_setname(2,
"exynos4-fimc");
336 s3c_fimc_setname(3,
"exynos4-fimc");
338 s3c_sdhci_setname(0,
"exynos4-sdhci");
339 s3c_sdhci_setname(1,
"exynos4-sdhci");
340 s3c_sdhci_setname(2,
"exynos4-sdhci");
341 s3c_sdhci_setname(3,
"exynos4-sdhci");
344 s3c_i2c0_setname(
"s3c2440-i2c");
345 s3c_i2c1_setname(
"s3c2440-i2c");
346 s3c_i2c2_setname(
"s3c2440-i2c");
348 s5p_fb_setname(0,
"exynos4-fb");
349 s5p_hdmi_setname(
"exynos4-hdmi");
351 s3c64xx_spi_setname(
"exynos4210-spi");
354 static void __init exynos5_map_io(
void)
363 s3c_sdhci_setname(0,
"exynos4-sdhci");
364 s3c_sdhci_setname(1,
"exynos4-sdhci");
365 s3c_sdhci_setname(2,
"exynos4-sdhci");
366 s3c_sdhci_setname(3,
"exynos4-sdhci");
369 s3c_i2c0_setname(
"s3c2440-i2c");
370 s3c_i2c1_setname(
"s3c2440-i2c");
371 s3c_i2c2_setname(
"s3c2440-i2c");
373 s3c64xx_spi_setname(
"exynos4210-spi");
376 static void __init exynos4_init_clocks(
int xtal)
392 static void __init exynos5_init_clocks(
int xtal)
403 #define COMBINER_ENABLE_SET 0x0
404 #define COMBINER_ENABLE_CLEAR 0x4
405 #define COMBINER_INT_STATUS 0xC
415 static struct irq_domain *combiner_irq_domain;
421 irq_data_get_irq_chip_data(data);
423 return combiner_data->
base;
433 static void combiner_unmask_irq(
struct irq_data *data)
440 static void combiner_handle_cascade_irq(
unsigned int irq,
struct irq_desc *
desc)
447 chained_irq_enter(chip, desc);
449 spin_lock(&irq_controller_lock);
451 spin_unlock(&irq_controller_lock);
457 combiner_irq =
__ffs(status);
459 cascade_irq = combiner_irq + (chip_data->
irq_offset & ~31);
466 chained_irq_exit(chip, desc);
469 static struct irq_chip combiner_chip = {
471 .irq_mask = combiner_mask_irq,
472 .irq_unmask = combiner_unmask_irq,
475 static void __init combiner_cascade_irq(
unsigned int combiner_nr,
unsigned int irq)
484 if (combiner_nr >= max_nr)
488 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
491 static void __init combiner_init_one(
unsigned int combiner_nr,
494 combiner_data[combiner_nr].base = base;
497 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
505 static int combiner_irq_domain_xlate(
struct irq_domain *
d,
507 const u32 *intspec,
unsigned int intsize,
508 unsigned long *out_hwirq,
509 unsigned int *out_type)
523 static int combiner_irq_domain_xlate(
struct irq_domain *d,
525 const u32 *intspec,
unsigned int intsize,
526 unsigned long *out_hwirq,
527 unsigned int *out_type)
533 static int combiner_irq_domain_map(
struct irq_domain *d,
unsigned int irq,
544 .xlate = combiner_irq_domain_xlate,
545 .map = combiner_irq_domain_map,
548 static void __init combiner_init(
void __iomem *combiner_base,
551 int i, irq, irq_base;
552 unsigned int max_nr, nr_irq;
555 if (of_property_read_u32(np,
"samsung,combiner-nr", &max_nr)) {
556 pr_warning(
"%s: number of combiners not specified, "
557 "setting default as %d.\n",
567 irq_base = irq_alloc_descs(
COMBINER_IRQ(0, 0), 1, nr_irq, 0);
570 pr_warning(
"%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
574 &combiner_irq_domain_ops, &combiner_data);
575 if (
WARN_ON(!combiner_irq_domain)) {
576 pr_warning(
"%s: irq domain init failed\n", __func__);
580 for (i = 0; i < max_nr; i++) {
581 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
587 combiner_cascade_irq(i, irq);
597 if (!combiner_base) {
598 pr_err(
"%s: failed to map combiner registers\n", __func__);
602 combiner_init(combiner_base, np);
607 static const struct of_device_id exynos4_dt_irq_match[] = {
609 { .compatible =
"samsung,exynos4210-combiner",
610 .data = combiner_of_init, },
617 unsigned int gic_bank_offset;
621 if (!of_have_populated_dt())
628 if (!of_have_populated_dt())
653 .name =
"exynos-core",
654 .dev_name =
"exynos-core",
657 static struct device exynos4_dev = {
661 static int __init exynos_core_init(
void)
667 #ifdef CONFIG_CACHE_L2X0
668 static int __init exynos4_l2x0_cache_init(
void)
721 static int __init exynos_init(
void)
735 for (ucnt = 0; ucnt <
no; ucnt++, tcfg++)
744 static void __iomem *exynos_eint_base;
748 static unsigned int eint0_15_data[16];
750 static inline int exynos4_irq_to_gpio(
unsigned int irq)
774 static inline int exynos5_irq_to_gpio(
unsigned int irq)
798 static unsigned int exynos4_eint0_15_src_int[16] = {
817 static unsigned int exynos5_eint0_15_src_int[16] = {
835 static inline void exynos_irq_eint_mask(
struct irq_data *data)
839 spin_lock(&eint_lock);
843 spin_unlock(&eint_lock);
846 static void exynos_irq_eint_unmask(
struct irq_data *data)
850 spin_lock(&eint_lock);
854 spin_unlock(&eint_lock);
857 static inline void exynos_irq_eint_ack(
struct irq_data *data)
863 static void exynos_irq_eint_maskack(
struct irq_data *data)
865 exynos_irq_eint_mask(data);
866 exynos_irq_eint_ack(data);
869 static int exynos_irq_eint_set_type(
struct irq_data *data,
unsigned int type)
902 shift = (offs & 0x7) * 4;
905 spin_lock(&eint_lock);
908 ctrl |= newvalue << shift;
910 spin_unlock(&eint_lock);
920 static struct irq_chip exynos_irq_eint = {
921 .name =
"exynos-eint",
922 .irq_mask = exynos_irq_eint_mask,
923 .irq_unmask = exynos_irq_eint_unmask,
924 .irq_mask_ack = exynos_irq_eint_maskack,
925 .irq_ack = exynos_irq_eint_ack,
926 .irq_set_type = exynos_irq_eint_set_type,
941 static inline void exynos_irq_demux_eint(
unsigned int start)
952 irq = fls(status) - 1;
954 status &= ~(1 << irq);
958 static void exynos_irq_demux_eint16_31(
unsigned int irq,
struct irq_desc *desc)
960 struct irq_chip *chip = irq_get_chip(irq);
961 chained_irq_enter(chip, desc);
962 exynos_irq_demux_eint(
IRQ_EINT(16));
963 exynos_irq_demux_eint(
IRQ_EINT(24));
964 chained_irq_exit(chip, desc);
967 static void exynos_irq_eint0_15(
unsigned int irq,
struct irq_desc *desc)
970 struct irq_chip *chip = irq_get_chip(irq);
972 chained_irq_enter(chip, desc);
981 chained_irq_exit(chip, desc);
984 static int __init exynos_init_irq_eint(
void)
988 #ifdef CONFIG_PINCTRL_SAMSUNG
1001 const char *pctrl_compat =
"samsung,pinctrl-exynos4210";
1002 const char *wkup_compat =
"samsung,exynos4210-wakeup-eint";
1004 for_each_compatible_node(pctrl_np,
NULL, pctrl_compat) {
1019 if (exynos_eint_base ==
NULL) {
1020 pr_err(
"unable to ioremap for EINT base address\n");
1024 for (irq = 0 ; irq <= 31 ; irq++) {
1025 irq_set_chip_and_handler(
IRQ_EINT(irq), &exynos_irq_eint,
1032 for (irq = 0 ; irq <= 15 ; irq++) {
1033 eint0_15_data[irq] =
IRQ_EINT(irq);
1037 &eint0_15_data[irq]);
1038 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1039 exynos_irq_eint0_15);
1042 &eint0_15_data[irq]);
1043 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1044 exynos_irq_eint0_15);