23 #include <linux/kernel.h>
24 #include <linux/module.h>
58 #define RG_TRX_STATUS (0x01)
59 #define SR_TRX_STATUS 0x01, 0x1f, 0
60 #define SR_RESERVED_01_3 0x01, 0x20, 5
61 #define SR_CCA_STATUS 0x01, 0x40, 6
62 #define SR_CCA_DONE 0x01, 0x80, 7
63 #define RG_TRX_STATE (0x02)
64 #define SR_TRX_CMD 0x02, 0x1f, 0
65 #define SR_TRAC_STATUS 0x02, 0xe0, 5
66 #define RG_TRX_CTRL_0 (0x03)
67 #define SR_CLKM_CTRL 0x03, 0x07, 0
68 #define SR_CLKM_SHA_SEL 0x03, 0x08, 3
69 #define SR_PAD_IO_CLKM 0x03, 0x30, 4
70 #define SR_PAD_IO 0x03, 0xc0, 6
71 #define RG_TRX_CTRL_1 (0x04)
72 #define SR_IRQ_POLARITY 0x04, 0x01, 0
73 #define SR_IRQ_MASK_MODE 0x04, 0x02, 1
74 #define SR_SPI_CMD_MODE 0x04, 0x0c, 2
75 #define SR_RX_BL_CTRL 0x04, 0x10, 4
76 #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
77 #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
78 #define SR_PA_EXT_EN 0x04, 0x80, 7
79 #define RG_PHY_TX_PWR (0x05)
80 #define SR_TX_PWR 0x05, 0x0f, 0
81 #define SR_PA_LT 0x05, 0x30, 4
82 #define SR_PA_BUF_LT 0x05, 0xc0, 6
83 #define RG_PHY_RSSI (0x06)
84 #define SR_RSSI 0x06, 0x1f, 0
85 #define SR_RND_VALUE 0x06, 0x60, 5
86 #define SR_RX_CRC_VALID 0x06, 0x80, 7
87 #define RG_PHY_ED_LEVEL (0x07)
88 #define SR_ED_LEVEL 0x07, 0xff, 0
89 #define RG_PHY_CC_CCA (0x08)
90 #define SR_CHANNEL 0x08, 0x1f, 0
91 #define SR_CCA_MODE 0x08, 0x60, 5
92 #define SR_CCA_REQUEST 0x08, 0x80, 7
93 #define RG_CCA_THRES (0x09)
94 #define SR_CCA_ED_THRES 0x09, 0x0f, 0
95 #define SR_RESERVED_09_1 0x09, 0xf0, 4
96 #define RG_RX_CTRL (0x0a)
97 #define SR_PDT_THRES 0x0a, 0x0f, 0
98 #define SR_RESERVED_0a_1 0x0a, 0xf0, 4
99 #define RG_SFD_VALUE (0x0b)
100 #define SR_SFD_VALUE 0x0b, 0xff, 0
101 #define RG_TRX_CTRL_2 (0x0c)
102 #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
103 #define SR_RESERVED_0c_2 0x0c, 0x7c, 2
104 #define SR_RX_SAFE_MODE 0x0c, 0x80, 7
105 #define RG_ANT_DIV (0x0d)
106 #define SR_ANT_CTRL 0x0d, 0x03, 0
107 #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
108 #define SR_ANT_DIV_EN 0x0d, 0x08, 3
109 #define SR_RESERVED_0d_2 0x0d, 0x70, 4
110 #define SR_ANT_SEL 0x0d, 0x80, 7
111 #define RG_IRQ_MASK (0x0e)
112 #define SR_IRQ_MASK 0x0e, 0xff, 0
113 #define RG_IRQ_STATUS (0x0f)
114 #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
115 #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
116 #define SR_IRQ_2_RX_START 0x0f, 0x04, 2
117 #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
118 #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
119 #define SR_IRQ_5_AMI 0x0f, 0x20, 5
120 #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
121 #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
122 #define RG_VREG_CTRL (0x10)
123 #define SR_RESERVED_10_6 0x10, 0x03, 0
124 #define SR_DVDD_OK 0x10, 0x04, 2
125 #define SR_DVREG_EXT 0x10, 0x08, 3
126 #define SR_RESERVED_10_3 0x10, 0x30, 4
127 #define SR_AVDD_OK 0x10, 0x40, 6
128 #define SR_AVREG_EXT 0x10, 0x80, 7
129 #define RG_BATMON (0x11)
130 #define SR_BATMON_VTH 0x11, 0x0f, 0
131 #define SR_BATMON_HR 0x11, 0x10, 4
132 #define SR_BATMON_OK 0x11, 0x20, 5
133 #define SR_RESERVED_11_1 0x11, 0xc0, 6
134 #define RG_XOSC_CTRL (0x12)
135 #define SR_XTAL_TRIM 0x12, 0x0f, 0
136 #define SR_XTAL_MODE 0x12, 0xf0, 4
137 #define RG_RX_SYN (0x15)
138 #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
139 #define SR_RESERVED_15_2 0x15, 0x70, 4
140 #define SR_RX_PDT_DIS 0x15, 0x80, 7
141 #define RG_XAH_CTRL_1 (0x17)
142 #define SR_RESERVED_17_8 0x17, 0x01, 0
143 #define SR_AACK_PROM_MODE 0x17, 0x02, 1
144 #define SR_AACK_ACK_TIME 0x17, 0x04, 2
145 #define SR_RESERVED_17_5 0x17, 0x08, 3
146 #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
147 #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
148 #define SR_RESERVED_17_2 0x17, 0x40, 6
149 #define SR_RESERVED_17_1 0x17, 0x80, 7
150 #define RG_FTN_CTRL (0x18)
151 #define SR_RESERVED_18_2 0x18, 0x7f, 0
152 #define SR_FTN_START 0x18, 0x80, 7
153 #define RG_PLL_CF (0x1a)
154 #define SR_RESERVED_1a_2 0x1a, 0x7f, 0
155 #define SR_PLL_CF_START 0x1a, 0x80, 7
156 #define RG_PLL_DCU (0x1b)
157 #define SR_RESERVED_1b_3 0x1b, 0x3f, 0
158 #define SR_RESERVED_1b_2 0x1b, 0x40, 6
159 #define SR_PLL_DCU_START 0x1b, 0x80, 7
160 #define RG_PART_NUM (0x1c)
161 #define SR_PART_NUM 0x1c, 0xff, 0
162 #define RG_VERSION_NUM (0x1d)
163 #define SR_VERSION_NUM 0x1d, 0xff, 0
164 #define RG_MAN_ID_0 (0x1e)
165 #define SR_MAN_ID_0 0x1e, 0xff, 0
166 #define RG_MAN_ID_1 (0x1f)
167 #define SR_MAN_ID_1 0x1f, 0xff, 0
168 #define RG_SHORT_ADDR_0 (0x20)
169 #define SR_SHORT_ADDR_0 0x20, 0xff, 0
170 #define RG_SHORT_ADDR_1 (0x21)
171 #define SR_SHORT_ADDR_1 0x21, 0xff, 0
172 #define RG_PAN_ID_0 (0x22)
173 #define SR_PAN_ID_0 0x22, 0xff, 0
174 #define RG_PAN_ID_1 (0x23)
175 #define SR_PAN_ID_1 0x23, 0xff, 0
176 #define RG_IEEE_ADDR_0 (0x24)
177 #define SR_IEEE_ADDR_0 0x24, 0xff, 0
178 #define RG_IEEE_ADDR_1 (0x25)
179 #define SR_IEEE_ADDR_1 0x25, 0xff, 0
180 #define RG_IEEE_ADDR_2 (0x26)
181 #define SR_IEEE_ADDR_2 0x26, 0xff, 0
182 #define RG_IEEE_ADDR_3 (0x27)
183 #define SR_IEEE_ADDR_3 0x27, 0xff, 0
184 #define RG_IEEE_ADDR_4 (0x28)
185 #define SR_IEEE_ADDR_4 0x28, 0xff, 0
186 #define RG_IEEE_ADDR_5 (0x29)
187 #define SR_IEEE_ADDR_5 0x29, 0xff, 0
188 #define RG_IEEE_ADDR_6 (0x2a)
189 #define SR_IEEE_ADDR_6 0x2a, 0xff, 0
190 #define RG_IEEE_ADDR_7 (0x2b)
191 #define SR_IEEE_ADDR_7 0x2b, 0xff, 0
192 #define RG_XAH_CTRL_0 (0x2c)
193 #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
194 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
195 #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
196 #define RG_CSMA_SEED_0 (0x2d)
197 #define SR_CSMA_SEED_0 0x2d, 0xff, 0
198 #define RG_CSMA_SEED_1 (0x2e)
199 #define SR_CSMA_SEED_1 0x2e, 0x07, 0
200 #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
201 #define SR_AACK_DIS_ACK 0x2e, 0x10, 4
202 #define SR_AACK_SET_PD 0x2e, 0x20, 5
203 #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
204 #define RG_CSMA_BE (0x2f)
205 #define SR_MIN_BE 0x2f, 0x0f, 0
206 #define SR_MAX_BE 0x2f, 0xf0, 4
209 #define CMD_REG_MASK 0x3f
210 #define CMD_WRITE 0x40
213 #define IRQ_BAT_LOW (1 << 7)
214 #define IRQ_TRX_UR (1 << 6)
215 #define IRQ_AMI (1 << 5)
216 #define IRQ_CCA_ED (1 << 4)
217 #define IRQ_TRX_END (1 << 3)
218 #define IRQ_RX_START (1 << 2)
219 #define IRQ_PLL_UNL (1 << 1)
220 #define IRQ_PLL_LOCK (1 << 0)
222 #define STATE_P_ON 0x00
223 #define STATE_BUSY_RX 0x01
224 #define STATE_BUSY_TX 0x02
225 #define STATE_FORCE_TRX_OFF 0x03
226 #define STATE_FORCE_TX_ON 0x04
228 #define STATE_RX_ON 0x06
230 #define STATE_TRX_OFF 0x08
231 #define STATE_TX_ON 0x09
233 #define STATE_SLEEP 0x0F
234 #define STATE_BUSY_RX_AACK 0x11
235 #define STATE_BUSY_TX_ARET 0x12
236 #define STATE_BUSY_RX_AACK_ON 0x16
237 #define STATE_BUSY_TX_ARET_ON 0x19
238 #define STATE_RX_ON_NOCLK 0x1C
239 #define STATE_RX_AACK_ON_NOCLK 0x1D
240 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
241 #define STATE_TRANSITION_IN_PROGRESS 0x1F
256 dev_vdbg(&lp->
spi->dev,
"buf[0] = %02x\n", buf[0]);
257 dev_vdbg(&lp->
spi->dev,
"buf[1] = %02x\n", buf[1]);
258 spi_message_init(&msg);
259 spi_message_add_tail(&xfer, &msg);
267 dev_vdbg(&lp->
spi->dev,
"buf[0] = %02x\n", buf[0]);
268 dev_vdbg(&lp->
spi->dev,
"buf[1] = %02x\n", buf[1]);
288 dev_vdbg(&lp->
spi->dev,
"buf[0] = %02x\n", buf[0]);
289 spi_message_init(&
msg);
290 spi_message_add_tail(&xfer, &
msg);
298 dev_vdbg(&lp->
spi->dev,
"buf[0] = %02x\n", buf[0]);
299 dev_vdbg(&lp->
spi->dev,
"buf[1] = %02x\n", buf[1]);
309 u8 addr,
u8 mask,
int shift,
u8 *data)
314 status = __at86rf230_read_subreg(lp, addr, mask, shift, data);
322 u8 addr,
u8 mask,
int shift,
u8 data)
328 status = __at86rf230_read_subreg(lp, addr, 0xff, 0, &val);
333 val |= (data << shift) & mask;
335 status = __at86rf230_write(lp, addr, val);
362 dev_vdbg(&lp->
spi->dev,
"buf[0] = %02x\n", buf[0]);
363 dev_vdbg(&lp->
spi->dev,
"buf[1] = %02x\n", buf[1]);
365 spi_message_init(&
msg);
366 spi_message_add_tail(&xfer_head, &
msg);
367 spi_message_add_tail(&xfer_buf, &
msg);
375 dev_vdbg(&lp->
spi->dev,
"buf[0] = %02x\n", buf[0]);
376 dev_vdbg(&lp->
spi->dev,
"buf[1] = %02x\n", buf[1]);
408 spi_message_init(&
msg);
409 spi_message_add_tail(&xfer_head, &
msg);
414 xfer_buf.
len = *(buf + 1) + 1;
420 spi_message_init(&
msg);
421 spi_message_add_tail(&xfer_head1, &
msg);
422 spi_message_add_tail(&xfer_buf, &
msg);
430 dev_vdbg(&lp->
spi->dev,
"buf[0] = %02x\n", buf[0]);
431 dev_vdbg(&lp->
spi->dev,
"buf[1] = %02x\n", buf[1]);
434 if (lqi && (*len > lp->
buf[1]))
435 *lqi = data[lp->
buf[1]];
466 desired_status =
state;
474 if (val == desired_status)
478 rc = at86rf230_write_subreg(lp,
SR_TRX_CMD, state);
489 if (val == desired_status)
492 pr_err(
"unexpected state change: %d, asked for %d\n", val, state);
496 pr_err(
"error: %d\n", rc);
532 rc = at86rf230_write_subreg(lp,
SR_CHANNEL, channel);
546 spin_lock(&lp->
lock);
548 spin_unlock(&lp->
lock);
551 spin_unlock(&lp->
lock);
562 spin_unlock_irqrestore(&lp->
lock, flags);
564 rc = at86rf230_write_fbuf(lp, skb->
data, skb->
len);
576 rc = at86rf230_start(dev);
581 at86rf230_start(dev);
583 pr_err(
"error: %d\n", rc);
587 spin_unlock_irqrestore(&lp->
lock, flags);
594 u8 len = 128, lqi = 0;
602 if (at86rf230_read_fbuf(lp,
skb_put(skb, len), &len, &lqi))
612 dev_dbg(&lp->
spi->dev,
"READ_FBUF: %d %x\n", len, lqi);
616 pr_debug(
"received frame is too small\n");
624 .xmit = at86rf230_xmit,
626 .set_channel = at86rf230_channel,
627 .start = at86rf230_start,
628 .stop = at86rf230_stop,
639 rc = at86rf230_read_subreg(lp,
RG_IRQ_STATUS, 0xff, 0, &val);
649 status &= ~IRQ_TRX_END;
652 spin_unlock_irqrestore(&lp->
lock, flags);
655 spin_unlock_irqrestore(&lp->
lock, flags);
662 spin_unlock_irqrestore(&lp->
lock, flags);
667 static irqreturn_t at86rf230_isr(
int irq,
void *data)
673 spin_lock(&lp->
lock);
675 spin_unlock(&lp->
lock);
704 rc = at86rf230_write_subreg(lp,
SR_IRQ_MASK, 0xff);
735 rc = at86rf230_read_subreg(lp,
SR_DVDD_OK, &status);
743 rc = at86rf230_read_subreg(lp,
SR_AVDD_OK, &status);
785 u8 man_id_0, man_id_1;
808 dev->
phy->channels_supported[0] = 0x7FFF800;
816 spi_set_drvdata(spi, lp);
818 rc = at86rf230_fill_data(spi);
826 if (gpio_is_valid(lp->
slp_tr)) {
836 if (gpio_is_valid(lp->
slp_tr)) {
849 rc = at86rf230_read_subreg(lp,
SR_MAN_ID_0, &man_id_0);
852 rc = at86rf230_read_subreg(lp,
SR_MAN_ID_1, &man_id_1);
856 if (man_id_1 != 0x00 || man_id_0 != 0x1f) {
857 dev_err(&spi->
dev,
"Non-Atmel dev found (MAN_ID %02x %02x)\n",
891 rc = at86rf230_hw_init(lp);
896 dev_name(&spi->
dev), lp);
911 if (gpio_is_valid(lp->
slp_tr))
917 spi_set_drvdata(spi,
NULL);
932 if (gpio_is_valid(lp->
slp_tr))
936 spi_set_drvdata(spi,
NULL);
940 dev_dbg(&spi->
dev,
"unregistered at86rf230\n");
949 .probe = at86rf230_probe,
951 .suspend = at86rf230_suspend,
952 .resume = at86rf230_resume,