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at91sam9g45_devices.c
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1 /*
2  * On-Chip devices setup code for the AT91SAM9G45 family
3  *
4  * Copyright (C) 2009 Atmel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14 
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
17 #include <linux/clk.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c-gpio.h>
20 #include <linux/atmel-mci.h>
21 #include <linux/platform_data/atmel-aes.h>
22 
23 #include <linux/platform_data/at91_adc.h>
24 
25 #include <linux/fb.h>
26 #include <video/atmel_lcdc.h>
27 
28 #include <mach/at91_adc.h>
29 #include <mach/board.h>
30 #include <mach/at91sam9g45.h>
31 #include <mach/at91sam9g45_matrix.h>
32 #include <mach/at91_matrix.h>
33 #include <mach/at91sam9_smc.h>
34 #include <linux/platform_data/dma-atmel.h>
35 #include <mach/atmel-mci.h>
36 
37 #include <media/atmel-isi.h>
38 
39 #include "generic.h"
40 #include "clock.h"
41 
42 
43 /* --------------------------------------------------------------------
44  * HDMAC - AHB DMA Controller
45  * -------------------------------------------------------------------- */
46 
47 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
48 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
49 
50 static struct resource hdmac_resources[] = {
51  [0] = {
52  .start = AT91SAM9G45_BASE_DMA,
53  .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
54  .flags = IORESOURCE_MEM,
55  },
56  [1] = {
57  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
58  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
59  .flags = IORESOURCE_IRQ,
60  },
61 };
62 
63 static struct platform_device at_hdmac_device = {
64  .name = "at91sam9g45_dma",
65  .id = -1,
66  .dev = {
67  .dma_mask = &hdmac_dmamask,
68  .coherent_dma_mask = DMA_BIT_MASK(32),
69  },
70  .resource = hdmac_resources,
71  .num_resources = ARRAY_SIZE(hdmac_resources),
72 };
73 
74 void __init at91_add_device_hdmac(void)
75 {
76  platform_device_register(&at_hdmac_device);
77 }
78 #else
79 void __init at91_add_device_hdmac(void) {}
80 #endif
81 
82 
83 /* --------------------------------------------------------------------
84  * USB Host (OHCI)
85  * -------------------------------------------------------------------- */
86 
87 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
88 static u64 ohci_dmamask = DMA_BIT_MASK(32);
89 static struct at91_usbh_data usbh_ohci_data;
90 
91 static struct resource usbh_ohci_resources[] = {
92  [0] = {
93  .start = AT91SAM9G45_OHCI_BASE,
94  .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
95  .flags = IORESOURCE_MEM,
96  },
97  [1] = {
98  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
99  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
100  .flags = IORESOURCE_IRQ,
101  },
102 };
103 
104 static struct platform_device at91_usbh_ohci_device = {
105  .name = "at91_ohci",
106  .id = -1,
107  .dev = {
108  .dma_mask = &ohci_dmamask,
109  .coherent_dma_mask = DMA_BIT_MASK(32),
110  .platform_data = &usbh_ohci_data,
111  },
112  .resource = usbh_ohci_resources,
113  .num_resources = ARRAY_SIZE(usbh_ohci_resources),
114 };
115 
116 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
117 {
118  int i;
119 
120  if (!data)
121  return;
122 
123  /* Enable VBus control for UHP ports */
124  for (i = 0; i < data->ports; i++) {
125  if (gpio_is_valid(data->vbus_pin[i]))
126  at91_set_gpio_output(data->vbus_pin[i],
127  data->vbus_pin_active_low[i]);
128  }
129 
130  /* Enable overcurrent notification */
131  for (i = 0; i < data->ports; i++) {
132  if (gpio_is_valid(data->overcurrent_pin[i]))
133  at91_set_gpio_input(data->overcurrent_pin[i], 1);
134  }
135 
136  usbh_ohci_data = *data;
137  platform_device_register(&at91_usbh_ohci_device);
138 }
139 #else
140 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
141 #endif
142 
143 
144 /* --------------------------------------------------------------------
145  * USB Host HS (EHCI)
146  * Needs an OHCI host for low and full speed management
147  * -------------------------------------------------------------------- */
148 
149 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
150 static u64 ehci_dmamask = DMA_BIT_MASK(32);
151 static struct at91_usbh_data usbh_ehci_data;
152 
153 static struct resource usbh_ehci_resources[] = {
154  [0] = {
155  .start = AT91SAM9G45_EHCI_BASE,
156  .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
157  .flags = IORESOURCE_MEM,
158  },
159  [1] = {
160  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
161  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
162  .flags = IORESOURCE_IRQ,
163  },
164 };
165 
166 static struct platform_device at91_usbh_ehci_device = {
167  .name = "atmel-ehci",
168  .id = -1,
169  .dev = {
170  .dma_mask = &ehci_dmamask,
171  .coherent_dma_mask = DMA_BIT_MASK(32),
172  .platform_data = &usbh_ehci_data,
173  },
174  .resource = usbh_ehci_resources,
175  .num_resources = ARRAY_SIZE(usbh_ehci_resources),
176 };
177 
178 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
179 {
180  int i;
181 
182  if (!data)
183  return;
184 
185  /* Enable VBus control for UHP ports */
186  for (i = 0; i < data->ports; i++) {
187  if (gpio_is_valid(data->vbus_pin[i]))
188  at91_set_gpio_output(data->vbus_pin[i],
189  data->vbus_pin_active_low[i]);
190  }
191 
192  usbh_ehci_data = *data;
193  platform_device_register(&at91_usbh_ehci_device);
194 }
195 #else
196 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
197 #endif
198 
199 
200 /* --------------------------------------------------------------------
201  * USB HS Device (Gadget)
202  * -------------------------------------------------------------------- */
203 
204 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
205 static struct resource usba_udc_resources[] = {
206  [0] = {
207  .start = AT91SAM9G45_UDPHS_FIFO,
208  .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
209  .flags = IORESOURCE_MEM,
210  },
211  [1] = {
212  .start = AT91SAM9G45_BASE_UDPHS,
213  .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
214  .flags = IORESOURCE_MEM,
215  },
216  [2] = {
217  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
218  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
219  .flags = IORESOURCE_IRQ,
220  },
221 };
222 
223 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
224  [idx] = { \
225  .name = nam, \
226  .index = idx, \
227  .fifo_size = maxpkt, \
228  .nr_banks = maxbk, \
229  .can_dma = dma, \
230  .can_isoc = isoc, \
231  }
232 
233 static struct usba_ep_data usba_udc_ep[] __initdata = {
234  EP("ep0", 0, 64, 1, 0, 0),
235  EP("ep1", 1, 1024, 2, 1, 1),
236  EP("ep2", 2, 1024, 2, 1, 1),
237  EP("ep3", 3, 1024, 3, 1, 0),
238  EP("ep4", 4, 1024, 3, 1, 0),
239  EP("ep5", 5, 1024, 3, 1, 1),
240  EP("ep6", 6, 1024, 3, 1, 1),
241 };
242 
243 #undef EP
244 
245 /*
246  * pdata doesn't have room for any endpoints, so we need to
247  * append room for the ones we need right after it.
248  */
249 static struct {
250  struct usba_platform_data pdata;
251  struct usba_ep_data ep[7];
252 } usba_udc_data;
253 
254 static struct platform_device at91_usba_udc_device = {
255  .name = "atmel_usba_udc",
256  .id = -1,
257  .dev = {
258  .platform_data = &usba_udc_data.pdata,
259  },
260  .resource = usba_udc_resources,
261  .num_resources = ARRAY_SIZE(usba_udc_resources),
262 };
263 
264 void __init at91_add_device_usba(struct usba_platform_data *data)
265 {
266  usba_udc_data.pdata.vbus_pin = -EINVAL;
267  usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
268  memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
269 
270  if (data && gpio_is_valid(data->vbus_pin)) {
271  at91_set_gpio_input(data->vbus_pin, 0);
272  at91_set_deglitch(data->vbus_pin, 1);
273  usba_udc_data.pdata.vbus_pin = data->vbus_pin;
274  }
275 
276  /* Pullup pin is handled internally by USB device peripheral */
277 
278  platform_device_register(&at91_usba_udc_device);
279 }
280 #else
281 void __init at91_add_device_usba(struct usba_platform_data *data) {}
282 #endif
283 
284 
285 /* --------------------------------------------------------------------
286  * Ethernet
287  * -------------------------------------------------------------------- */
288 
289 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
290 static u64 eth_dmamask = DMA_BIT_MASK(32);
291 static struct macb_platform_data eth_data;
292 
293 static struct resource eth_resources[] = {
294  [0] = {
295  .start = AT91SAM9G45_BASE_EMAC,
296  .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
297  .flags = IORESOURCE_MEM,
298  },
299  [1] = {
300  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
301  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
302  .flags = IORESOURCE_IRQ,
303  },
304 };
305 
306 static struct platform_device at91sam9g45_eth_device = {
307  .name = "macb",
308  .id = -1,
309  .dev = {
310  .dma_mask = &eth_dmamask,
311  .coherent_dma_mask = DMA_BIT_MASK(32),
312  .platform_data = &eth_data,
313  },
314  .resource = eth_resources,
315  .num_resources = ARRAY_SIZE(eth_resources),
316 };
317 
318 void __init at91_add_device_eth(struct macb_platform_data *data)
319 {
320  if (!data)
321  return;
322 
323  if (gpio_is_valid(data->phy_irq_pin)) {
324  at91_set_gpio_input(data->phy_irq_pin, 0);
325  at91_set_deglitch(data->phy_irq_pin, 1);
326  }
327 
328  /* Pins used for MII and RMII */
329  at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
330  at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
331  at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
332  at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
333  at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
334  at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
335  at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
336  at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
337  at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
338  at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
339 
340  if (!data->is_rmii) {
341  at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
342  at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
343  at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
344  at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
345  at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
346  at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
347  at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
348  at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
349  }
350 
351  eth_data = *data;
352  platform_device_register(&at91sam9g45_eth_device);
353 }
354 #else
355 void __init at91_add_device_eth(struct macb_platform_data *data) {}
356 #endif
357 
358 
359 /* --------------------------------------------------------------------
360  * MMC / SD
361  * -------------------------------------------------------------------- */
362 
363 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
364 static u64 mmc_dmamask = DMA_BIT_MASK(32);
365 static struct mci_platform_data mmc0_data, mmc1_data;
366 
367 static struct resource mmc0_resources[] = {
368  [0] = {
369  .start = AT91SAM9G45_BASE_MCI0,
370  .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
371  .flags = IORESOURCE_MEM,
372  },
373  [1] = {
374  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
375  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
376  .flags = IORESOURCE_IRQ,
377  },
378 };
379 
380 static struct platform_device at91sam9g45_mmc0_device = {
381  .name = "atmel_mci",
382  .id = 0,
383  .dev = {
384  .dma_mask = &mmc_dmamask,
385  .coherent_dma_mask = DMA_BIT_MASK(32),
386  .platform_data = &mmc0_data,
387  },
388  .resource = mmc0_resources,
389  .num_resources = ARRAY_SIZE(mmc0_resources),
390 };
391 
392 static struct resource mmc1_resources[] = {
393  [0] = {
394  .start = AT91SAM9G45_BASE_MCI1,
395  .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
396  .flags = IORESOURCE_MEM,
397  },
398  [1] = {
399  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
400  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
401  .flags = IORESOURCE_IRQ,
402  },
403 };
404 
405 static struct platform_device at91sam9g45_mmc1_device = {
406  .name = "atmel_mci",
407  .id = 1,
408  .dev = {
409  .dma_mask = &mmc_dmamask,
410  .coherent_dma_mask = DMA_BIT_MASK(32),
411  .platform_data = &mmc1_data,
412  },
413  .resource = mmc1_resources,
414  .num_resources = ARRAY_SIZE(mmc1_resources),
415 };
416 
417 /* Consider only one slot : slot 0 */
418 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
419 {
420 
421  if (!data)
422  return;
423 
424  /* Must have at least one usable slot */
425  if (!data->slot[0].bus_width)
426  return;
427 
428 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
429  {
430  struct at_dma_slave *atslave;
431  struct mci_dma_data *alt_atslave;
432 
433  alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
434  atslave = &alt_atslave->sdata;
435 
436  /* DMA slave channel configuration */
437  atslave->dma_dev = &at_hdmac_device.dev;
438  atslave->cfg = ATC_FIFOCFG_HALFFIFO
439  | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
440  if (mmc_id == 0) /* MCI0 */
441  atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
442  | ATC_DST_PER(AT_DMA_ID_MCI0);
443 
444  else /* MCI1 */
445  atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
446  | ATC_DST_PER(AT_DMA_ID_MCI1);
447 
448  data->dma_slave = alt_atslave;
449  }
450 #endif
451 
452 
453  /* input/irq */
454  if (gpio_is_valid(data->slot[0].detect_pin)) {
455  at91_set_gpio_input(data->slot[0].detect_pin, 1);
456  at91_set_deglitch(data->slot[0].detect_pin, 1);
457  }
458  if (gpio_is_valid(data->slot[0].wp_pin))
459  at91_set_gpio_input(data->slot[0].wp_pin, 1);
460 
461  if (mmc_id == 0) { /* MCI0 */
462 
463  /* CLK */
464  at91_set_A_periph(AT91_PIN_PA0, 0);
465 
466  /* CMD */
467  at91_set_A_periph(AT91_PIN_PA1, 1);
468 
469  /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
470  at91_set_A_periph(AT91_PIN_PA2, 1);
471  if (data->slot[0].bus_width == 4) {
472  at91_set_A_periph(AT91_PIN_PA3, 1);
473  at91_set_A_periph(AT91_PIN_PA4, 1);
474  at91_set_A_periph(AT91_PIN_PA5, 1);
475  if (data->slot[0].bus_width == 8) {
476  at91_set_A_periph(AT91_PIN_PA6, 1);
477  at91_set_A_periph(AT91_PIN_PA7, 1);
478  at91_set_A_periph(AT91_PIN_PA8, 1);
479  at91_set_A_periph(AT91_PIN_PA9, 1);
480  }
481  }
482 
483  mmc0_data = *data;
484  platform_device_register(&at91sam9g45_mmc0_device);
485 
486  } else { /* MCI1 */
487 
488  /* CLK */
489  at91_set_A_periph(AT91_PIN_PA31, 0);
490 
491  /* CMD */
492  at91_set_A_periph(AT91_PIN_PA22, 1);
493 
494  /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
495  at91_set_A_periph(AT91_PIN_PA23, 1);
496  if (data->slot[0].bus_width == 4) {
497  at91_set_A_periph(AT91_PIN_PA24, 1);
498  at91_set_A_periph(AT91_PIN_PA25, 1);
499  at91_set_A_periph(AT91_PIN_PA26, 1);
500  if (data->slot[0].bus_width == 8) {
501  at91_set_A_periph(AT91_PIN_PA27, 1);
502  at91_set_A_periph(AT91_PIN_PA28, 1);
503  at91_set_A_periph(AT91_PIN_PA29, 1);
504  at91_set_A_periph(AT91_PIN_PA30, 1);
505  }
506  }
507 
508  mmc1_data = *data;
509  platform_device_register(&at91sam9g45_mmc1_device);
510 
511  }
512 }
513 #else
514 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
515 #endif
516 
517 
518 /* --------------------------------------------------------------------
519  * NAND / SmartMedia
520  * -------------------------------------------------------------------- */
521 
522 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
523 static struct atmel_nand_data nand_data;
524 
525 #define NAND_BASE AT91_CHIPSELECT_3
526 
527 static struct resource nand_resources[] = {
528  [0] = {
529  .start = NAND_BASE,
530  .end = NAND_BASE + SZ_256M - 1,
531  .flags = IORESOURCE_MEM,
532  },
533  [1] = {
534  .start = AT91SAM9G45_BASE_ECC,
535  .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
536  .flags = IORESOURCE_MEM,
537  }
538 };
539 
540 static struct platform_device at91sam9g45_nand_device = {
541  .name = "atmel_nand",
542  .id = -1,
543  .dev = {
544  .platform_data = &nand_data,
545  },
546  .resource = nand_resources,
547  .num_resources = ARRAY_SIZE(nand_resources),
548 };
549 
550 void __init at91_add_device_nand(struct atmel_nand_data *data)
551 {
552  unsigned long csa;
553 
554  if (!data)
555  return;
556 
557  csa = at91_matrix_read(AT91_MATRIX_EBICSA);
558  at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
559 
560  /* enable pin */
561  if (gpio_is_valid(data->enable_pin))
562  at91_set_gpio_output(data->enable_pin, 1);
563 
564  /* ready/busy pin */
565  if (gpio_is_valid(data->rdy_pin))
566  at91_set_gpio_input(data->rdy_pin, 1);
567 
568  /* card detect pin */
569  if (gpio_is_valid(data->det_pin))
570  at91_set_gpio_input(data->det_pin, 1);
571 
572  nand_data = *data;
573  platform_device_register(&at91sam9g45_nand_device);
574 }
575 #else
576 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
577 #endif
578 
579 
580 /* --------------------------------------------------------------------
581  * TWI (i2c)
582  * -------------------------------------------------------------------- */
583 
584 /*
585  * Prefer the GPIO code since the TWI controller isn't robust
586  * (gets overruns and underruns under load) and can only issue
587  * repeated STARTs in one scenario (the driver doesn't yet handle them).
588  */
589 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
590 static struct i2c_gpio_platform_data pdata_i2c0 = {
591  .sda_pin = AT91_PIN_PA20,
592  .sda_is_open_drain = 1,
593  .scl_pin = AT91_PIN_PA21,
594  .scl_is_open_drain = 1,
595  .udelay = 5, /* ~100 kHz */
596 };
597 
598 static struct platform_device at91sam9g45_twi0_device = {
599  .name = "i2c-gpio",
600  .id = 0,
601  .dev.platform_data = &pdata_i2c0,
602 };
603 
604 static struct i2c_gpio_platform_data pdata_i2c1 = {
605  .sda_pin = AT91_PIN_PB10,
606  .sda_is_open_drain = 1,
607  .scl_pin = AT91_PIN_PB11,
608  .scl_is_open_drain = 1,
609  .udelay = 5, /* ~100 kHz */
610 };
611 
612 static struct platform_device at91sam9g45_twi1_device = {
613  .name = "i2c-gpio",
614  .id = 1,
615  .dev.platform_data = &pdata_i2c1,
616 };
617 
618 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
619 {
620  i2c_register_board_info(i2c_id, devices, nr_devices);
621 
622  if (i2c_id == 0) {
623  at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
624  at91_set_multi_drive(AT91_PIN_PA20, 1);
625 
626  at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
627  at91_set_multi_drive(AT91_PIN_PA21, 1);
628 
629  platform_device_register(&at91sam9g45_twi0_device);
630  } else {
631  at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
632  at91_set_multi_drive(AT91_PIN_PB10, 1);
633 
634  at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
635  at91_set_multi_drive(AT91_PIN_PB11, 1);
636 
637  platform_device_register(&at91sam9g45_twi1_device);
638  }
639 }
640 
641 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
642 static struct resource twi0_resources[] = {
643  [0] = {
644  .start = AT91SAM9G45_BASE_TWI0,
645  .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
646  .flags = IORESOURCE_MEM,
647  },
648  [1] = {
649  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
650  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
651  .flags = IORESOURCE_IRQ,
652  },
653 };
654 
655 static struct platform_device at91sam9g45_twi0_device = {
656  .name = "i2c-at91sam9g10",
657  .id = 0,
658  .resource = twi0_resources,
659  .num_resources = ARRAY_SIZE(twi0_resources),
660 };
661 
662 static struct resource twi1_resources[] = {
663  [0] = {
664  .start = AT91SAM9G45_BASE_TWI1,
665  .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
666  .flags = IORESOURCE_MEM,
667  },
668  [1] = {
669  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
670  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
671  .flags = IORESOURCE_IRQ,
672  },
673 };
674 
675 static struct platform_device at91sam9g45_twi1_device = {
676  .name = "i2c-at91sam9g10",
677  .id = 1,
678  .resource = twi1_resources,
679  .num_resources = ARRAY_SIZE(twi1_resources),
680 };
681 
682 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
683 {
684  i2c_register_board_info(i2c_id, devices, nr_devices);
685 
686  /* pins used for TWI interface */
687  if (i2c_id == 0) {
688  at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
689  at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
690 
691  platform_device_register(&at91sam9g45_twi0_device);
692  } else {
693  at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
694  at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
695 
696  platform_device_register(&at91sam9g45_twi1_device);
697  }
698 }
699 #else
700 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
701 #endif
702 
703 
704 /* --------------------------------------------------------------------
705  * SPI
706  * -------------------------------------------------------------------- */
707 
708 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
709 static u64 spi_dmamask = DMA_BIT_MASK(32);
710 
711 static struct resource spi0_resources[] = {
712  [0] = {
713  .start = AT91SAM9G45_BASE_SPI0,
714  .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
715  .flags = IORESOURCE_MEM,
716  },
717  [1] = {
718  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
719  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
720  .flags = IORESOURCE_IRQ,
721  },
722 };
723 
724 static struct platform_device at91sam9g45_spi0_device = {
725  .name = "atmel_spi",
726  .id = 0,
727  .dev = {
728  .dma_mask = &spi_dmamask,
729  .coherent_dma_mask = DMA_BIT_MASK(32),
730  },
731  .resource = spi0_resources,
732  .num_resources = ARRAY_SIZE(spi0_resources),
733 };
734 
735 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
736 
737 static struct resource spi1_resources[] = {
738  [0] = {
739  .start = AT91SAM9G45_BASE_SPI1,
740  .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
741  .flags = IORESOURCE_MEM,
742  },
743  [1] = {
744  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
745  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
746  .flags = IORESOURCE_IRQ,
747  },
748 };
749 
750 static struct platform_device at91sam9g45_spi1_device = {
751  .name = "atmel_spi",
752  .id = 1,
753  .dev = {
754  .dma_mask = &spi_dmamask,
755  .coherent_dma_mask = DMA_BIT_MASK(32),
756  },
757  .resource = spi1_resources,
758  .num_resources = ARRAY_SIZE(spi1_resources),
759 };
760 
761 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
762 
763 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
764 {
765  int i;
766  unsigned long cs_pin;
767  short enable_spi0 = 0;
768  short enable_spi1 = 0;
769 
770  /* Choose SPI chip-selects */
771  for (i = 0; i < nr_devices; i++) {
772  if (devices[i].controller_data)
773  cs_pin = (unsigned long) devices[i].controller_data;
774  else if (devices[i].bus_num == 0)
775  cs_pin = spi0_standard_cs[devices[i].chip_select];
776  else
777  cs_pin = spi1_standard_cs[devices[i].chip_select];
778 
779  if (!gpio_is_valid(cs_pin))
780  continue;
781 
782  if (devices[i].bus_num == 0)
783  enable_spi0 = 1;
784  else
785  enable_spi1 = 1;
786 
787  /* enable chip-select pin */
788  at91_set_gpio_output(cs_pin, 1);
789 
790  /* pass chip-select pin to driver */
791  devices[i].controller_data = (void *) cs_pin;
792  }
793 
794  spi_register_board_info(devices, nr_devices);
795 
796  /* Configure SPI bus(es) */
797  if (enable_spi0) {
798  at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
799  at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
800  at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
801 
802  platform_device_register(&at91sam9g45_spi0_device);
803  }
804  if (enable_spi1) {
805  at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
806  at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
807  at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
808 
809  platform_device_register(&at91sam9g45_spi1_device);
810  }
811 }
812 #else
813 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
814 #endif
815 
816 
817 /* --------------------------------------------------------------------
818  * AC97
819  * -------------------------------------------------------------------- */
820 
821 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
822 static u64 ac97_dmamask = DMA_BIT_MASK(32);
823 static struct ac97c_platform_data ac97_data;
824 
825 static struct resource ac97_resources[] = {
826  [0] = {
827  .start = AT91SAM9G45_BASE_AC97C,
828  .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
829  .flags = IORESOURCE_MEM,
830  },
831  [1] = {
832  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
833  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
834  .flags = IORESOURCE_IRQ,
835  },
836 };
837 
838 static struct platform_device at91sam9g45_ac97_device = {
839  .name = "atmel_ac97c",
840  .id = 0,
841  .dev = {
842  .dma_mask = &ac97_dmamask,
843  .coherent_dma_mask = DMA_BIT_MASK(32),
844  .platform_data = &ac97_data,
845  },
846  .resource = ac97_resources,
847  .num_resources = ARRAY_SIZE(ac97_resources),
848 };
849 
850 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
851 {
852  if (!data)
853  return;
854 
855  at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
856  at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
857  at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
858  at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
859 
860  /* reset */
861  if (gpio_is_valid(data->reset_pin))
862  at91_set_gpio_output(data->reset_pin, 0);
863 
864  ac97_data = *data;
865  platform_device_register(&at91sam9g45_ac97_device);
866 }
867 #else
868 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
869 #endif
870 
871 /* --------------------------------------------------------------------
872  * Image Sensor Interface
873  * -------------------------------------------------------------------- */
874 #if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
875 static u64 isi_dmamask = DMA_BIT_MASK(32);
876 static struct isi_platform_data isi_data;
877 
878 struct resource isi_resources[] = {
879  [0] = {
880  .start = AT91SAM9G45_BASE_ISI,
881  .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
882  .flags = IORESOURCE_MEM,
883  },
884  [1] = {
885  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
886  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
887  .flags = IORESOURCE_IRQ,
888  },
889 };
890 
891 static struct platform_device at91sam9g45_isi_device = {
892  .name = "atmel_isi",
893  .id = 0,
894  .dev = {
895  .dma_mask = &isi_dmamask,
896  .coherent_dma_mask = DMA_BIT_MASK(32),
897  .platform_data = &isi_data,
898  },
899  .resource = isi_resources,
900  .num_resources = ARRAY_SIZE(isi_resources),
901 };
902 
903 static struct clk_lookup isi_mck_lookups[] = {
904  CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
905 };
906 
907 void __init at91_add_device_isi(struct isi_platform_data *data,
908  bool use_pck_as_mck)
909 {
910  struct clk *pck;
911  struct clk *parent;
912 
913  if (!data)
914  return;
915  isi_data = *data;
916 
917  at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
918  at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
919  at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
920  at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
921  at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
922  at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
923  at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
924  at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
925  at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
926  at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
927  at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
928  at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
929  at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
930  at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
931  at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
932 
933  platform_device_register(&at91sam9g45_isi_device);
934 
935  if (use_pck_as_mck) {
936  at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
937 
938  pck = clk_get(NULL, "pck1");
939  parent = clk_get(NULL, "plla");
940 
941  BUG_ON(IS_ERR(pck) || IS_ERR(parent));
942 
943  if (clk_set_parent(pck, parent)) {
944  pr_err("Failed to set PCK's parent\n");
945  } else {
946  /* Register PCK as ISI_MCK */
947  isi_mck_lookups[0].clk = pck;
948  clkdev_add_table(isi_mck_lookups,
949  ARRAY_SIZE(isi_mck_lookups));
950  }
951 
952  clk_put(pck);
953  clk_put(parent);
954  }
955 }
956 #else
957 void __init at91_add_device_isi(struct isi_platform_data *data,
958  bool use_pck_as_mck) {}
959 #endif
960 
961 
962 /* --------------------------------------------------------------------
963  * LCD Controller
964  * -------------------------------------------------------------------- */
965 
966 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
967 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
968 static struct atmel_lcdfb_info lcdc_data;
969 
970 static struct resource lcdc_resources[] = {
971  [0] = {
972  .start = AT91SAM9G45_LCDC_BASE,
973  .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
974  .flags = IORESOURCE_MEM,
975  },
976  [1] = {
977  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
978  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
979  .flags = IORESOURCE_IRQ,
980  },
981 };
982 
983 static struct platform_device at91_lcdc_device = {
984  .name = "atmel_lcdfb",
985  .id = 0,
986  .dev = {
987  .dma_mask = &lcdc_dmamask,
988  .coherent_dma_mask = DMA_BIT_MASK(32),
989  .platform_data = &lcdc_data,
990  },
991  .resource = lcdc_resources,
992  .num_resources = ARRAY_SIZE(lcdc_resources),
993 };
994 
995 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
996 {
997  if (!data)
998  return;
999 
1000  at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
1001 
1002  at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
1003  at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
1004  at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
1005  at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
1006  at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
1007  at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
1008  at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
1009  at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
1010  at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
1011  at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
1012  at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
1013  at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
1014  at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
1015  at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
1016  at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
1017  at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
1018  at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
1019  at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
1020  at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
1021  at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
1022  at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
1023  at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
1024  at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
1025  at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
1026  at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
1027  at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
1028  at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
1029  at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
1030  at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
1031 
1032  lcdc_data = *data;
1033  platform_device_register(&at91_lcdc_device);
1034 }
1035 #else
1036 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1037 #endif
1038 
1039 
1040 /* --------------------------------------------------------------------
1041  * Timer/Counter block
1042  * -------------------------------------------------------------------- */
1043 
1044 #ifdef CONFIG_ATMEL_TCLIB
1045 static struct resource tcb0_resources[] = {
1046  [0] = {
1047  .start = AT91SAM9G45_BASE_TCB0,
1048  .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1049  .flags = IORESOURCE_MEM,
1050  },
1051  [1] = {
1052  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1053  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1054  .flags = IORESOURCE_IRQ,
1055  },
1056 };
1057 
1058 static struct platform_device at91sam9g45_tcb0_device = {
1059  .name = "atmel_tcb",
1060  .id = 0,
1061  .resource = tcb0_resources,
1062  .num_resources = ARRAY_SIZE(tcb0_resources),
1063 };
1064 
1065 /* TCB1 begins with TC3 */
1066 static struct resource tcb1_resources[] = {
1067  [0] = {
1068  .start = AT91SAM9G45_BASE_TCB1,
1069  .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1070  .flags = IORESOURCE_MEM,
1071  },
1072  [1] = {
1073  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1074  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1075  .flags = IORESOURCE_IRQ,
1076  },
1077 };
1078 
1079 static struct platform_device at91sam9g45_tcb1_device = {
1080  .name = "atmel_tcb",
1081  .id = 1,
1082  .resource = tcb1_resources,
1083  .num_resources = ARRAY_SIZE(tcb1_resources),
1084 };
1085 
1086 static void __init at91_add_device_tc(void)
1087 {
1088  platform_device_register(&at91sam9g45_tcb0_device);
1089  platform_device_register(&at91sam9g45_tcb1_device);
1090 }
1091 #else
1092 static void __init at91_add_device_tc(void) { }
1093 #endif
1094 
1095 
1096 /* --------------------------------------------------------------------
1097  * RTC
1098  * -------------------------------------------------------------------- */
1099 
1100 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1101 static struct resource rtc_resources[] = {
1102  [0] = {
1103  .start = AT91SAM9G45_BASE_RTC,
1104  .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1105  .flags = IORESOURCE_MEM,
1106  },
1107  [1] = {
1108  .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1109  .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1110  .flags = IORESOURCE_IRQ,
1111  },
1112 };
1113 
1114 static struct platform_device at91sam9g45_rtc_device = {
1115  .name = "at91_rtc",
1116  .id = -1,
1117  .resource = rtc_resources,
1118  .num_resources = ARRAY_SIZE(rtc_resources),
1119 };
1120 
1121 static void __init at91_add_device_rtc(void)
1122 {
1123  platform_device_register(&at91sam9g45_rtc_device);
1124 }
1125 #else
1126 static void __init at91_add_device_rtc(void) {}
1127 #endif
1128 
1129 
1130 /* --------------------------------------------------------------------
1131  * Touchscreen
1132  * -------------------------------------------------------------------- */
1133 
1134 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1135 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1136 static struct at91_tsadcc_data tsadcc_data;
1137 
1138 static struct resource tsadcc_resources[] = {
1139  [0] = {
1140  .start = AT91SAM9G45_BASE_TSC,
1141  .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1142  .flags = IORESOURCE_MEM,
1143  },
1144  [1] = {
1145  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1146  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1147  .flags = IORESOURCE_IRQ,
1148  }
1149 };
1150 
1151 static struct platform_device at91sam9g45_tsadcc_device = {
1152  .name = "atmel_tsadcc",
1153  .id = -1,
1154  .dev = {
1155  .dma_mask = &tsadcc_dmamask,
1156  .coherent_dma_mask = DMA_BIT_MASK(32),
1157  .platform_data = &tsadcc_data,
1158  },
1159  .resource = tsadcc_resources,
1160  .num_resources = ARRAY_SIZE(tsadcc_resources),
1161 };
1162 
1163 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1164 {
1165  if (!data)
1166  return;
1167 
1168  at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
1169  at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
1170  at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
1171  at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
1172 
1173  tsadcc_data = *data;
1174  platform_device_register(&at91sam9g45_tsadcc_device);
1175 }
1176 #else
1177 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1178 #endif
1179 
1180 
1181 /* --------------------------------------------------------------------
1182  * ADC
1183  * -------------------------------------------------------------------- */
1184 
1185 #if IS_ENABLED(CONFIG_AT91_ADC)
1186 static struct at91_adc_data adc_data;
1187 
1188 static struct resource adc_resources[] = {
1189  [0] = {
1190  .start = AT91SAM9G45_BASE_TSC,
1191  .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1192  .flags = IORESOURCE_MEM,
1193  },
1194  [1] = {
1195  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1196  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1197  .flags = IORESOURCE_IRQ,
1198  }
1199 };
1200 
1201 static struct platform_device at91_adc_device = {
1202  .name = "at91_adc",
1203  .id = -1,
1204  .dev = {
1205  .platform_data = &adc_data,
1206  },
1207  .resource = adc_resources,
1208  .num_resources = ARRAY_SIZE(adc_resources),
1209 };
1210 
1211 static struct at91_adc_trigger at91_adc_triggers[] = {
1212  [0] = {
1213  .name = "external-rising",
1214  .value = 1,
1215  .is_external = true,
1216  },
1217  [1] = {
1218  .name = "external-falling",
1219  .value = 2,
1220  .is_external = true,
1221  },
1222  [2] = {
1223  .name = "external-any",
1224  .value = 3,
1225  .is_external = true,
1226  },
1227  [3] = {
1228  .name = "continuous",
1229  .value = 6,
1230  .is_external = false,
1231  },
1232 };
1233 
1234 static struct at91_adc_reg_desc at91_adc_register_g45 = {
1235  .channel_base = AT91_ADC_CHR(0),
1236  .drdy_mask = AT91_ADC_DRDY,
1237  .status_register = AT91_ADC_SR,
1238  .trigger_register = 0x08,
1239 };
1240 
1241 void __init at91_add_device_adc(struct at91_adc_data *data)
1242 {
1243  if (!data)
1244  return;
1245 
1246  if (test_bit(0, &data->channels_used))
1247  at91_set_gpio_input(AT91_PIN_PD20, 0);
1248  if (test_bit(1, &data->channels_used))
1249  at91_set_gpio_input(AT91_PIN_PD21, 0);
1250  if (test_bit(2, &data->channels_used))
1251  at91_set_gpio_input(AT91_PIN_PD22, 0);
1252  if (test_bit(3, &data->channels_used))
1253  at91_set_gpio_input(AT91_PIN_PD23, 0);
1254  if (test_bit(4, &data->channels_used))
1255  at91_set_gpio_input(AT91_PIN_PD24, 0);
1256  if (test_bit(5, &data->channels_used))
1257  at91_set_gpio_input(AT91_PIN_PD25, 0);
1258  if (test_bit(6, &data->channels_used))
1259  at91_set_gpio_input(AT91_PIN_PD26, 0);
1260  if (test_bit(7, &data->channels_used))
1261  at91_set_gpio_input(AT91_PIN_PD27, 0);
1262 
1263  if (data->use_external_triggers)
1264  at91_set_A_periph(AT91_PIN_PD28, 0);
1265 
1266  data->num_channels = 8;
1267  data->startup_time = 40;
1268  data->registers = &at91_adc_register_g45;
1269  data->trigger_number = 4;
1270  data->trigger_list = at91_adc_triggers;
1271 
1272  adc_data = *data;
1273  platform_device_register(&at91_adc_device);
1274 }
1275 #else
1276 void __init at91_add_device_adc(struct at91_adc_data *data) {}
1277 #endif
1278 
1279 /* --------------------------------------------------------------------
1280  * RTT
1281  * -------------------------------------------------------------------- */
1282 
1283 static struct resource rtt_resources[] = {
1284  {
1285  .start = AT91SAM9G45_BASE_RTT,
1286  .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1287  .flags = IORESOURCE_MEM,
1288  }, {
1289  .flags = IORESOURCE_MEM,
1290  }, {
1291  .flags = IORESOURCE_IRQ,
1292  }
1293 };
1294 
1295 static struct platform_device at91sam9g45_rtt_device = {
1296  .name = "at91_rtt",
1297  .id = 0,
1298  .resource = rtt_resources,
1299 };
1300 
1301 #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1302 static void __init at91_add_device_rtt_rtc(void)
1303 {
1304  at91sam9g45_rtt_device.name = "rtc-at91sam9";
1305  /*
1306  * The second resource is needed:
1307  * GPBR will serve as the storage for RTC time offset
1308  */
1309  at91sam9g45_rtt_device.num_resources = 3;
1310  rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1311  4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1312  rtt_resources[1].end = rtt_resources[1].start + 3;
1313  rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
1314  rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
1315 }
1316 #else
1317 static void __init at91_add_device_rtt_rtc(void)
1318 {
1319  /* Only one resource is needed: RTT not used as RTC */
1320  at91sam9g45_rtt_device.num_resources = 1;
1321 }
1322 #endif
1323 
1324 static void __init at91_add_device_rtt(void)
1325 {
1326  at91_add_device_rtt_rtc();
1327  platform_device_register(&at91sam9g45_rtt_device);
1328 }
1329 
1330 
1331 /* --------------------------------------------------------------------
1332  * TRNG
1333  * -------------------------------------------------------------------- */
1334 
1335 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1336 static struct resource trng_resources[] = {
1337  {
1338  .start = AT91SAM9G45_BASE_TRNG,
1339  .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1340  .flags = IORESOURCE_MEM,
1341  },
1342 };
1343 
1344 static struct platform_device at91sam9g45_trng_device = {
1345  .name = "atmel-trng",
1346  .id = -1,
1347  .resource = trng_resources,
1348  .num_resources = ARRAY_SIZE(trng_resources),
1349 };
1350 
1351 static void __init at91_add_device_trng(void)
1352 {
1353  platform_device_register(&at91sam9g45_trng_device);
1354 }
1355 #else
1356 static void __init at91_add_device_trng(void) {}
1357 #endif
1358 
1359 /* --------------------------------------------------------------------
1360  * Watchdog
1361  * -------------------------------------------------------------------- */
1362 
1363 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1364 static struct resource wdt_resources[] = {
1365  {
1366  .start = AT91SAM9G45_BASE_WDT,
1367  .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1368  .flags = IORESOURCE_MEM,
1369  }
1370 };
1371 
1372 static struct platform_device at91sam9g45_wdt_device = {
1373  .name = "at91_wdt",
1374  .id = -1,
1375  .resource = wdt_resources,
1376  .num_resources = ARRAY_SIZE(wdt_resources),
1377 };
1378 
1379 static void __init at91_add_device_watchdog(void)
1380 {
1381  platform_device_register(&at91sam9g45_wdt_device);
1382 }
1383 #else
1384 static void __init at91_add_device_watchdog(void) {}
1385 #endif
1386 
1387 
1388 /* --------------------------------------------------------------------
1389  * PWM
1390  * --------------------------------------------------------------------*/
1391 
1392 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1393 static u32 pwm_mask;
1394 
1395 static struct resource pwm_resources[] = {
1396  [0] = {
1397  .start = AT91SAM9G45_BASE_PWMC,
1398  .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1399  .flags = IORESOURCE_MEM,
1400  },
1401  [1] = {
1402  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1403  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1404  .flags = IORESOURCE_IRQ,
1405  },
1406 };
1407 
1408 static struct platform_device at91sam9g45_pwm0_device = {
1409  .name = "atmel_pwm",
1410  .id = -1,
1411  .dev = {
1412  .platform_data = &pwm_mask,
1413  },
1414  .resource = pwm_resources,
1415  .num_resources = ARRAY_SIZE(pwm_resources),
1416 };
1417 
1418 void __init at91_add_device_pwm(u32 mask)
1419 {
1420  if (mask & (1 << AT91_PWM0))
1421  at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1422 
1423  if (mask & (1 << AT91_PWM1))
1424  at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1425 
1426  if (mask & (1 << AT91_PWM2))
1427  at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1428 
1429  if (mask & (1 << AT91_PWM3))
1430  at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1431 
1432  pwm_mask = mask;
1433 
1434  platform_device_register(&at91sam9g45_pwm0_device);
1435 }
1436 #else
1437 void __init at91_add_device_pwm(u32 mask) {}
1438 #endif
1439 
1440 
1441 /* --------------------------------------------------------------------
1442  * SSC -- Synchronous Serial Controller
1443  * -------------------------------------------------------------------- */
1444 
1445 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1446 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1447 
1448 static struct resource ssc0_resources[] = {
1449  [0] = {
1450  .start = AT91SAM9G45_BASE_SSC0,
1451  .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1452  .flags = IORESOURCE_MEM,
1453  },
1454  [1] = {
1455  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1456  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1457  .flags = IORESOURCE_IRQ,
1458  },
1459 };
1460 
1461 static struct platform_device at91sam9g45_ssc0_device = {
1462  .name = "ssc",
1463  .id = 0,
1464  .dev = {
1465  .dma_mask = &ssc0_dmamask,
1466  .coherent_dma_mask = DMA_BIT_MASK(32),
1467  },
1468  .resource = ssc0_resources,
1469  .num_resources = ARRAY_SIZE(ssc0_resources),
1470 };
1471 
1472 static inline void configure_ssc0_pins(unsigned pins)
1473 {
1474  if (pins & ATMEL_SSC_TF)
1475  at91_set_A_periph(AT91_PIN_PD1, 1);
1476  if (pins & ATMEL_SSC_TK)
1477  at91_set_A_periph(AT91_PIN_PD0, 1);
1478  if (pins & ATMEL_SSC_TD)
1479  at91_set_A_periph(AT91_PIN_PD2, 1);
1480  if (pins & ATMEL_SSC_RD)
1481  at91_set_A_periph(AT91_PIN_PD3, 1);
1482  if (pins & ATMEL_SSC_RK)
1483  at91_set_A_periph(AT91_PIN_PD4, 1);
1484  if (pins & ATMEL_SSC_RF)
1485  at91_set_A_periph(AT91_PIN_PD5, 1);
1486 }
1487 
1488 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1489 
1490 static struct resource ssc1_resources[] = {
1491  [0] = {
1492  .start = AT91SAM9G45_BASE_SSC1,
1493  .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1494  .flags = IORESOURCE_MEM,
1495  },
1496  [1] = {
1497  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1498  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1499  .flags = IORESOURCE_IRQ,
1500  },
1501 };
1502 
1503 static struct platform_device at91sam9g45_ssc1_device = {
1504  .name = "ssc",
1505  .id = 1,
1506  .dev = {
1507  .dma_mask = &ssc1_dmamask,
1508  .coherent_dma_mask = DMA_BIT_MASK(32),
1509  },
1510  .resource = ssc1_resources,
1511  .num_resources = ARRAY_SIZE(ssc1_resources),
1512 };
1513 
1514 static inline void configure_ssc1_pins(unsigned pins)
1515 {
1516  if (pins & ATMEL_SSC_TF)
1517  at91_set_A_periph(AT91_PIN_PD14, 1);
1518  if (pins & ATMEL_SSC_TK)
1519  at91_set_A_periph(AT91_PIN_PD12, 1);
1520  if (pins & ATMEL_SSC_TD)
1521  at91_set_A_periph(AT91_PIN_PD10, 1);
1522  if (pins & ATMEL_SSC_RD)
1523  at91_set_A_periph(AT91_PIN_PD11, 1);
1524  if (pins & ATMEL_SSC_RK)
1525  at91_set_A_periph(AT91_PIN_PD13, 1);
1526  if (pins & ATMEL_SSC_RF)
1527  at91_set_A_periph(AT91_PIN_PD15, 1);
1528 }
1529 
1530 /*
1531  * SSC controllers are accessed through library code, instead of any
1532  * kind of all-singing/all-dancing driver. For example one could be
1533  * used by a particular I2S audio codec's driver, while another one
1534  * on the same system might be used by a custom data capture driver.
1535  */
1536 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1537 {
1538  struct platform_device *pdev;
1539 
1540  /*
1541  * NOTE: caller is responsible for passing information matching
1542  * "pins" to whatever will be using each particular controller.
1543  */
1544  switch (id) {
1545  case AT91SAM9G45_ID_SSC0:
1546  pdev = &at91sam9g45_ssc0_device;
1547  configure_ssc0_pins(pins);
1548  break;
1549  case AT91SAM9G45_ID_SSC1:
1550  pdev = &at91sam9g45_ssc1_device;
1551  configure_ssc1_pins(pins);
1552  break;
1553  default:
1554  return;
1555  }
1556 
1557  platform_device_register(pdev);
1558 }
1559 
1560 #else
1561 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1562 #endif
1563 
1564 
1565 /* --------------------------------------------------------------------
1566  * UART
1567  * -------------------------------------------------------------------- */
1568 
1569 #if defined(CONFIG_SERIAL_ATMEL)
1570 static struct resource dbgu_resources[] = {
1571  [0] = {
1572  .start = AT91SAM9G45_BASE_DBGU,
1573  .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1574  .flags = IORESOURCE_MEM,
1575  },
1576  [1] = {
1577  .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1578  .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1579  .flags = IORESOURCE_IRQ,
1580  },
1581 };
1582 
1583 static struct atmel_uart_data dbgu_data = {
1584  .use_dma_tx = 0,
1585  .use_dma_rx = 0,
1586 };
1587 
1588 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1589 
1590 static struct platform_device at91sam9g45_dbgu_device = {
1591  .name = "atmel_usart",
1592  .id = 0,
1593  .dev = {
1594  .dma_mask = &dbgu_dmamask,
1595  .coherent_dma_mask = DMA_BIT_MASK(32),
1596  .platform_data = &dbgu_data,
1597  },
1598  .resource = dbgu_resources,
1599  .num_resources = ARRAY_SIZE(dbgu_resources),
1600 };
1601 
1602 static inline void configure_dbgu_pins(void)
1603 {
1604  at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1605  at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1606 }
1607 
1608 static struct resource uart0_resources[] = {
1609  [0] = {
1610  .start = AT91SAM9G45_BASE_US0,
1611  .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1612  .flags = IORESOURCE_MEM,
1613  },
1614  [1] = {
1615  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1616  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1617  .flags = IORESOURCE_IRQ,
1618  },
1619 };
1620 
1621 static struct atmel_uart_data uart0_data = {
1622  .use_dma_tx = 1,
1623  .use_dma_rx = 1,
1624 };
1625 
1626 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1627 
1628 static struct platform_device at91sam9g45_uart0_device = {
1629  .name = "atmel_usart",
1630  .id = 1,
1631  .dev = {
1632  .dma_mask = &uart0_dmamask,
1633  .coherent_dma_mask = DMA_BIT_MASK(32),
1634  .platform_data = &uart0_data,
1635  },
1636  .resource = uart0_resources,
1637  .num_resources = ARRAY_SIZE(uart0_resources),
1638 };
1639 
1640 static inline void configure_usart0_pins(unsigned pins)
1641 {
1642  at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1643  at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1644 
1645  if (pins & ATMEL_UART_RTS)
1646  at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1647  if (pins & ATMEL_UART_CTS)
1648  at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1649 }
1650 
1651 static struct resource uart1_resources[] = {
1652  [0] = {
1653  .start = AT91SAM9G45_BASE_US1,
1654  .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1655  .flags = IORESOURCE_MEM,
1656  },
1657  [1] = {
1658  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1659  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1660  .flags = IORESOURCE_IRQ,
1661  },
1662 };
1663 
1664 static struct atmel_uart_data uart1_data = {
1665  .use_dma_tx = 1,
1666  .use_dma_rx = 1,
1667 };
1668 
1669 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1670 
1671 static struct platform_device at91sam9g45_uart1_device = {
1672  .name = "atmel_usart",
1673  .id = 2,
1674  .dev = {
1675  .dma_mask = &uart1_dmamask,
1676  .coherent_dma_mask = DMA_BIT_MASK(32),
1677  .platform_data = &uart1_data,
1678  },
1679  .resource = uart1_resources,
1680  .num_resources = ARRAY_SIZE(uart1_resources),
1681 };
1682 
1683 static inline void configure_usart1_pins(unsigned pins)
1684 {
1685  at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1686  at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1687 
1688  if (pins & ATMEL_UART_RTS)
1689  at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1690  if (pins & ATMEL_UART_CTS)
1691  at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1692 }
1693 
1694 static struct resource uart2_resources[] = {
1695  [0] = {
1696  .start = AT91SAM9G45_BASE_US2,
1697  .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1698  .flags = IORESOURCE_MEM,
1699  },
1700  [1] = {
1701  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1702  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1703  .flags = IORESOURCE_IRQ,
1704  },
1705 };
1706 
1707 static struct atmel_uart_data uart2_data = {
1708  .use_dma_tx = 1,
1709  .use_dma_rx = 1,
1710 };
1711 
1712 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1713 
1714 static struct platform_device at91sam9g45_uart2_device = {
1715  .name = "atmel_usart",
1716  .id = 3,
1717  .dev = {
1718  .dma_mask = &uart2_dmamask,
1719  .coherent_dma_mask = DMA_BIT_MASK(32),
1720  .platform_data = &uart2_data,
1721  },
1722  .resource = uart2_resources,
1723  .num_resources = ARRAY_SIZE(uart2_resources),
1724 };
1725 
1726 static inline void configure_usart2_pins(unsigned pins)
1727 {
1728  at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1729  at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1730 
1731  if (pins & ATMEL_UART_RTS)
1732  at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1733  if (pins & ATMEL_UART_CTS)
1734  at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1735 }
1736 
1737 static struct resource uart3_resources[] = {
1738  [0] = {
1739  .start = AT91SAM9G45_BASE_US3,
1740  .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1741  .flags = IORESOURCE_MEM,
1742  },
1743  [1] = {
1744  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1745  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1746  .flags = IORESOURCE_IRQ,
1747  },
1748 };
1749 
1750 static struct atmel_uart_data uart3_data = {
1751  .use_dma_tx = 1,
1752  .use_dma_rx = 1,
1753 };
1754 
1755 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1756 
1757 static struct platform_device at91sam9g45_uart3_device = {
1758  .name = "atmel_usart",
1759  .id = 4,
1760  .dev = {
1761  .dma_mask = &uart3_dmamask,
1762  .coherent_dma_mask = DMA_BIT_MASK(32),
1763  .platform_data = &uart3_data,
1764  },
1765  .resource = uart3_resources,
1766  .num_resources = ARRAY_SIZE(uart3_resources),
1767 };
1768 
1769 static inline void configure_usart3_pins(unsigned pins)
1770 {
1771  at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1772  at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1773 
1774  if (pins & ATMEL_UART_RTS)
1775  at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1776  if (pins & ATMEL_UART_CTS)
1777  at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1778 }
1779 
1780 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1781 
1782 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1783 {
1784  struct platform_device *pdev;
1785  struct atmel_uart_data *pdata;
1786 
1787  switch (id) {
1788  case 0: /* DBGU */
1789  pdev = &at91sam9g45_dbgu_device;
1790  configure_dbgu_pins();
1791  break;
1792  case AT91SAM9G45_ID_US0:
1793  pdev = &at91sam9g45_uart0_device;
1794  configure_usart0_pins(pins);
1795  break;
1796  case AT91SAM9G45_ID_US1:
1797  pdev = &at91sam9g45_uart1_device;
1798  configure_usart1_pins(pins);
1799  break;
1800  case AT91SAM9G45_ID_US2:
1801  pdev = &at91sam9g45_uart2_device;
1802  configure_usart2_pins(pins);
1803  break;
1804  case AT91SAM9G45_ID_US3:
1805  pdev = &at91sam9g45_uart3_device;
1806  configure_usart3_pins(pins);
1807  break;
1808  default:
1809  return;
1810  }
1811  pdata = pdev->dev.platform_data;
1812  pdata->num = portnr; /* update to mapped ID */
1813 
1814  if (portnr < ATMEL_MAX_UART)
1815  at91_uarts[portnr] = pdev;
1816 }
1817 
1818 void __init at91_add_device_serial(void)
1819 {
1820  int i;
1821 
1822  for (i = 0; i < ATMEL_MAX_UART; i++) {
1823  if (at91_uarts[i])
1824  platform_device_register(at91_uarts[i]);
1825  }
1826 }
1827 #else
1828 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1829 void __init at91_add_device_serial(void) {}
1830 #endif
1831 
1832 /* --------------------------------------------------------------------
1833  * SHA1/SHA256
1834  * -------------------------------------------------------------------- */
1835 
1836 #if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
1837 static struct resource sha_resources[] = {
1838  {
1839  .start = AT91SAM9G45_BASE_SHA,
1840  .end = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
1841  .flags = IORESOURCE_MEM,
1842  },
1843  [1] = {
1844  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1845  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1846  .flags = IORESOURCE_IRQ,
1847  },
1848 };
1849 
1850 static struct platform_device at91sam9g45_sha_device = {
1851  .name = "atmel_sha",
1852  .id = -1,
1853  .resource = sha_resources,
1854  .num_resources = ARRAY_SIZE(sha_resources),
1855 };
1856 
1857 static void __init at91_add_device_sha(void)
1858 {
1859  platform_device_register(&at91sam9g45_sha_device);
1860 }
1861 #else
1862 static void __init at91_add_device_sha(void) {}
1863 #endif
1864 
1865 /* --------------------------------------------------------------------
1866  * DES/TDES
1867  * -------------------------------------------------------------------- */
1868 
1869 #if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
1870 static struct resource tdes_resources[] = {
1871  [0] = {
1872  .start = AT91SAM9G45_BASE_TDES,
1873  .end = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
1874  .flags = IORESOURCE_MEM,
1875  },
1876  [1] = {
1877  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1878  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1879  .flags = IORESOURCE_IRQ,
1880  },
1881 };
1882 
1883 static struct platform_device at91sam9g45_tdes_device = {
1884  .name = "atmel_tdes",
1885  .id = -1,
1886  .resource = tdes_resources,
1887  .num_resources = ARRAY_SIZE(tdes_resources),
1888 };
1889 
1890 static void __init at91_add_device_tdes(void)
1891 {
1892  platform_device_register(&at91sam9g45_tdes_device);
1893 }
1894 #else
1895 static void __init at91_add_device_tdes(void) {}
1896 #endif
1897 
1898 /* --------------------------------------------------------------------
1899  * AES
1900  * -------------------------------------------------------------------- */
1901 
1902 #if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
1903 static struct aes_platform_data aes_data;
1904 static u64 aes_dmamask = DMA_BIT_MASK(32);
1905 
1906 static struct resource aes_resources[] = {
1907  [0] = {
1908  .start = AT91SAM9G45_BASE_AES,
1909  .end = AT91SAM9G45_BASE_AES + SZ_16K - 1,
1910  .flags = IORESOURCE_MEM,
1911  },
1912  [1] = {
1913  .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1914  .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1915  .flags = IORESOURCE_IRQ,
1916  },
1917 };
1918 
1919 static struct platform_device at91sam9g45_aes_device = {
1920  .name = "atmel_aes",
1921  .id = -1,
1922  .dev = {
1923  .dma_mask = &aes_dmamask,
1924  .coherent_dma_mask = DMA_BIT_MASK(32),
1925  .platform_data = &aes_data,
1926  },
1927  .resource = aes_resources,
1928  .num_resources = ARRAY_SIZE(aes_resources),
1929 };
1930 
1931 static void __init at91_add_device_aes(void)
1932 {
1933  struct at_dma_slave *atslave;
1934  struct aes_dma_data *alt_atslave;
1935 
1936  alt_atslave = kzalloc(sizeof(struct aes_dma_data), GFP_KERNEL);
1937 
1938  /* DMA TX slave channel configuration */
1939  atslave = &alt_atslave->txdata;
1940  atslave->dma_dev = &at_hdmac_device.dev;
1941  atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_SRC_H2SEL_HW |
1942  ATC_SRC_PER(AT_DMA_ID_AES_RX);
1943 
1944  /* DMA RX slave channel configuration */
1945  atslave = &alt_atslave->rxdata;
1946  atslave->dma_dev = &at_hdmac_device.dev;
1947  atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_DST_H2SEL_HW |
1948  ATC_DST_PER(AT_DMA_ID_AES_TX);
1949 
1950  aes_data.dma_slave = alt_atslave;
1951  platform_device_register(&at91sam9g45_aes_device);
1952 }
1953 #else
1954 static void __init at91_add_device_aes(void) {}
1955 #endif
1956 
1957 /* -------------------------------------------------------------------- */
1958 /*
1959  * These devices are always present and don't need any board-specific
1960  * setup.
1961  */
1962 static int __init at91_add_standard_devices(void)
1963 {
1964  if (of_have_populated_dt())
1965  return 0;
1966 
1967  at91_add_device_hdmac();
1968  at91_add_device_rtc();
1969  at91_add_device_rtt();
1970  at91_add_device_trng();
1971  at91_add_device_watchdog();
1972  at91_add_device_tc();
1973  at91_add_device_sha();
1974  at91_add_device_tdes();
1975  at91_add_device_aes();
1976  return 0;
1977 }
1978 
1979 arch_initcall(at91_add_standard_devices);
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