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bnx2x_hsi.h
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1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2012 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9 #ifndef BNX2X_HSI_H
10 #define BNX2X_HSI_H
11 
12 #include "bnx2x_fw_defs.h"
13 #include "bnx2x_mfw_req.h"
14 
15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
16 
17 struct license_key {
19 
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
25 
27 
29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
33 
35 };
36 
37 /****************************************************************************
38  * Shared HW configuration *
39  ****************************************************************************/
40 #define PIN_CFG_NA 0x00000000
41 #define PIN_CFG_GPIO0_P0 0x00000001
42 #define PIN_CFG_GPIO1_P0 0x00000002
43 #define PIN_CFG_GPIO2_P0 0x00000003
44 #define PIN_CFG_GPIO3_P0 0x00000004
45 #define PIN_CFG_GPIO0_P1 0x00000005
46 #define PIN_CFG_GPIO1_P1 0x00000006
47 #define PIN_CFG_GPIO2_P1 0x00000007
48 #define PIN_CFG_GPIO3_P1 0x00000008
49 #define PIN_CFG_EPIO0 0x00000009
50 #define PIN_CFG_EPIO1 0x0000000a
51 #define PIN_CFG_EPIO2 0x0000000b
52 #define PIN_CFG_EPIO3 0x0000000c
53 #define PIN_CFG_EPIO4 0x0000000d
54 #define PIN_CFG_EPIO5 0x0000000e
55 #define PIN_CFG_EPIO6 0x0000000f
56 #define PIN_CFG_EPIO7 0x00000010
57 #define PIN_CFG_EPIO8 0x00000011
58 #define PIN_CFG_EPIO9 0x00000012
59 #define PIN_CFG_EPIO10 0x00000013
60 #define PIN_CFG_EPIO11 0x00000014
61 #define PIN_CFG_EPIO12 0x00000015
62 #define PIN_CFG_EPIO13 0x00000016
63 #define PIN_CFG_EPIO14 0x00000017
64 #define PIN_CFG_EPIO15 0x00000018
65 #define PIN_CFG_EPIO16 0x00000019
66 #define PIN_CFG_EPIO17 0x0000001a
67 #define PIN_CFG_EPIO18 0x0000001b
68 #define PIN_CFG_EPIO19 0x0000001c
69 #define PIN_CFG_EPIO20 0x0000001d
70 #define PIN_CFG_EPIO21 0x0000001e
71 #define PIN_CFG_EPIO22 0x0000001f
72 #define PIN_CFG_EPIO23 0x00000020
73 #define PIN_CFG_EPIO24 0x00000021
74 #define PIN_CFG_EPIO25 0x00000022
75 #define PIN_CFG_EPIO26 0x00000023
76 #define PIN_CFG_EPIO27 0x00000024
77 #define PIN_CFG_EPIO28 0x00000025
78 #define PIN_CFG_EPIO29 0x00000026
79 #define PIN_CFG_EPIO30 0x00000027
80 #define PIN_CFG_EPIO31 0x00000028
81 
82 /* EPIO definition */
83 #define EPIO_CFG_NA 0x00000000
84 #define EPIO_CFG_EPIO0 0x00000001
85 #define EPIO_CFG_EPIO1 0x00000002
86 #define EPIO_CFG_EPIO2 0x00000003
87 #define EPIO_CFG_EPIO3 0x00000004
88 #define EPIO_CFG_EPIO4 0x00000005
89 #define EPIO_CFG_EPIO5 0x00000006
90 #define EPIO_CFG_EPIO6 0x00000007
91 #define EPIO_CFG_EPIO7 0x00000008
92 #define EPIO_CFG_EPIO8 0x00000009
93 #define EPIO_CFG_EPIO9 0x0000000a
94 #define EPIO_CFG_EPIO10 0x0000000b
95 #define EPIO_CFG_EPIO11 0x0000000c
96 #define EPIO_CFG_EPIO12 0x0000000d
97 #define EPIO_CFG_EPIO13 0x0000000e
98 #define EPIO_CFG_EPIO14 0x0000000f
99 #define EPIO_CFG_EPIO15 0x00000010
100 #define EPIO_CFG_EPIO16 0x00000011
101 #define EPIO_CFG_EPIO17 0x00000012
102 #define EPIO_CFG_EPIO18 0x00000013
103 #define EPIO_CFG_EPIO19 0x00000014
104 #define EPIO_CFG_EPIO20 0x00000015
105 #define EPIO_CFG_EPIO21 0x00000016
106 #define EPIO_CFG_EPIO22 0x00000017
107 #define EPIO_CFG_EPIO23 0x00000018
108 #define EPIO_CFG_EPIO24 0x00000019
109 #define EPIO_CFG_EPIO25 0x0000001a
110 #define EPIO_CFG_EPIO26 0x0000001b
111 #define EPIO_CFG_EPIO27 0x0000001c
112 #define EPIO_CFG_EPIO28 0x0000001d
113 #define EPIO_CFG_EPIO29 0x0000001e
114 #define EPIO_CFG_EPIO30 0x0000001f
115 #define EPIO_CFG_EPIO31 0x00000020
116 
117 
118 struct shared_hw_cfg { /* NVRAM Offset */
119  /* Up to 16 bytes of NULL-terminated string */
120  u8 part_num[16]; /* 0x104 */
121 
122  u32 config; /* 0x114 */
123  #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
124  #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
125  #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
126  #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
127  #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
128 
129  #define SHARED_HW_CFG_PORT_SWAP 0x00000004
130 
131  #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
132 
133  #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
134  #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
135 
136  #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
137  #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
138  /* Whatever MFW found in NVM
139  (if multiple found, priority order is: NC-SI, UMP, IPMI) */
140  #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
141  #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
142  #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
143  #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
144  /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
145  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
146  #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
147  /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
148  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
149  #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
150  /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
151  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
152  #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
153 
154  #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
155  #define SHARED_HW_CFG_LED_MODE_SHIFT 16
156  #define SHARED_HW_CFG_LED_MAC1 0x00000000
157  #define SHARED_HW_CFG_LED_PHY1 0x00010000
158  #define SHARED_HW_CFG_LED_PHY2 0x00020000
159  #define SHARED_HW_CFG_LED_PHY3 0x00030000
160  #define SHARED_HW_CFG_LED_MAC2 0x00040000
161  #define SHARED_HW_CFG_LED_PHY4 0x00050000
162  #define SHARED_HW_CFG_LED_PHY5 0x00060000
163  #define SHARED_HW_CFG_LED_PHY6 0x00070000
164  #define SHARED_HW_CFG_LED_MAC3 0x00080000
165  #define SHARED_HW_CFG_LED_PHY7 0x00090000
166  #define SHARED_HW_CFG_LED_PHY9 0x000a0000
167  #define SHARED_HW_CFG_LED_PHY11 0x000b0000
168  #define SHARED_HW_CFG_LED_MAC4 0x000c0000
169  #define SHARED_HW_CFG_LED_PHY8 0x000d0000
170  #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
171 
172 
173  #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
174  #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
175  #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
176  #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
177  #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
178  #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
179  #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
180  #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
181 
182  #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
183  #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
184  #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
185 
186  #define SHARED_HW_CFG_ATC_MASK 0x80000000
187  #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
188  #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
189 
190  u32 config2; /* 0x118 */
191  /* one time auto detect grace period (in sec) */
192  #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
193  #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
194 
195  #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
196  #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
197 
198  /* The default value for the core clock is 250MHz and it is
199  achieved by setting the clock change to 4 */
200  #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
201  #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
202 
203  #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
204  #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
205  #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
206 
207  #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
208 
209  #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
210  #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
211  #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
212 
213  /* Output low when PERST is asserted */
214  #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
215  #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
216  #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
217 
218  #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
219  #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
220  #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
221  #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
222  #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
223  #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
224 
225  /* The fan failure mechanism is usually related to the PHY type
226  since the power consumption of the board is determined by the PHY.
227  Currently, fan is required for most designs with SFX7101, BCM8727
228  and BCM8481. If a fan is not required for a board which uses one
229  of those PHYs, this field should be set to "Disabled". If a fan is
230  required for a different PHY type, this option should be set to
231  "Enabled". The fan failure indication is expected on SPIO5 */
232  #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
233  #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
234  #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
235  #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
236  #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
237 
238  /* ASPM Power Management support */
239  #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
240  #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
241  #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
242  #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
243  #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
244  #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
245 
246  /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
247  tl_control_0 (register 0x2800) */
248  #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
249  #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
250  #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
251 
252  #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
253  #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
254  #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
255 
256  #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
257  #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
258  #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
259 
260  /* Set the MDC/MDIO access for the first external phy */
261  #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
262  #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
263  #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
264  #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
265  #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
266  #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
267  #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
268 
269  /* Set the MDC/MDIO access for the second external phy */
270  #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
271  #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
272  #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
273  #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
274  #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
275  #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
276  #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
277 
278 
279  u32 power_dissipated; /* 0x11c */
280  #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
281  #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
282  #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
283  #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
284  #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
285  #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
286 
287  #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
288  #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
289 
290  u32 ump_nc_si_config; /* 0x120 */
291  #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
292  #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
293  #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
294  #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
295  #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
296  #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
297 
298  #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
299  #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
300 
301  #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
302  #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
303  #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
304  #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
305 
306  u32 board; /* 0x124 */
307  #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
308  #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
309  #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
310  #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
311  /* Use the PIN_CFG_XXX defines on top */
312  #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
313  #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
314 
315  #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
316  #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
317 
318  #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
319  #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
320 
321  u32 wc_lane_config; /* 0x128 */
322  #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
323  #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
324  #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
325  #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
326  #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
327  #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
328  #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
329  #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
330  #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
331  #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
332 
333  /* TX lane Polarity swap */
334  #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
335  #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
336  #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
337  #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
338  /* TX lane Polarity swap */
339  #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
340  #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
341  #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
342  #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
343 
344  /* Selects the port layout of the board */
345  #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
346  #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
347  #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
348  #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
349  #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
350  #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
351  #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
352  #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
353 };
354 
355 
356 /****************************************************************************
357  * Port HW configuration *
358  ****************************************************************************/
359 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
360 
362  #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
363  #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
364 
366  #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
367  #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
368 
370  #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
371  #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
372  #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
373  #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
374  #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
375  #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
376  #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
377  #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
378 
380  #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
381  #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
382  #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
383  #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
384  #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
385  #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
386  #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
387  #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
388 
390  #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
391  #define PORT_HW_CFG_UPPERMAC_SHIFT 0
393 
394  u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
396 
397  u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
399 
401  #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
402  #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
403 
404  #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
405  #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
406 
407 
408  /* Default values: 2P-64, 4P-32 */
409  u32 pf_config; /* 0x158 */
410  #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
411  #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
412 
413  /* Default values: 17 */
414  #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
415  #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
416 
417  #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
418  #define PORT_HW_CFG_FLR_ENABLED 0x00010000
419 
420  u32 vf_config; /* 0x15C */
421  #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
422  #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
423 
424  #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
425  #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
426 
427  u32 mf_pci_id; /* 0x160 */
428  #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
429  #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
430 
431  /* Controls the TX laser of the SFP+ module */
432  u32 sfp_ctrl; /* 0x164 */
433  #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
434  #define PORT_HW_CFG_TX_LASER_SHIFT 0
435  #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
436  #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
437  #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
438  #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
439  #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
440 
441  /* Controls the fault module LED of the SFP+ */
442  #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
443  #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
444  #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
445  #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
446  #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
447  #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
448  #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
449 
450  /* The output pin TX_DIS that controls the TX laser of the SFP+
451  module. Use the PIN_CFG_XXX defines on top */
452  u32 e3_sfp_ctrl; /* 0x168 */
453  #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
454  #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
455 
456  /* The output pin for SFPP_TYPE which turns on the Fault module LED */
457  #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
458  #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
459 
460  /* The input pin MOD_ABS that indicates whether SFP+ module is
461  present or not. Use the PIN_CFG_XXX defines on top */
462  #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
463  #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
464 
465  /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
466  module. Use the PIN_CFG_XXX defines on top */
467  #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
468  #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
469 
470  /*
471  * The input pin which signals module transmit fault. Use the
472  * PIN_CFG_XXX defines on top
473  */
474  u32 e3_cmn_pin_cfg; /* 0x16C */
475  #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
476  #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
477 
478  /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
479  top */
480  #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
481  #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
482 
483  /*
484  * The output pin which powers down the PHY. Use the PIN_CFG_XXX
485  * defines on top
486  */
487  #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
488  #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
489 
490  /* The output pin values BSC_SEL which selects the I2C for this port
491  in the I2C Mux */
492  #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
493  #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
494 
495 
496  /*
497  * The input pin I_FAULT which indicate over-current has occurred.
498  * Use the PIN_CFG_XXX defines on top
499  */
500  u32 e3_cmn_pin_cfg1; /* 0x170 */
501  #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
502  #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
503  u32 reserved0[7]; /* 0x174 */
504 
505  u32 aeu_int_mask; /* 0x190 */
506 
507  u32 media_type; /* 0x194 */
508  #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
509  #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
510 
511  #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
512  #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
513 
514  #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
515  #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
516 
517  /* 4 times 16 bits for all 4 lanes. In case external PHY is present
518  (not direct mode), those values will not take effect on the 4 XGXS
519  lanes. For some external PHYs (such as 8706 and 8726) the values
520  will be used to configure the external PHY in those cases, not
521  all 4 values are needed. */
522  u16 xgxs_config_rx[4]; /* 0x198 */
523  u16 xgxs_config_tx[4]; /* 0x1A0 */
524 
525  /* For storing FCOE mac on shared memory */
527  #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
528  #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
530 
533 
536 
537  u32 Reserved1[49]; /* 0x1C0 */
538 
539  /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
540  84833 only */
541  u32 xgbt_phy_cfg; /* 0x284 */
542  #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
543  #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
544 
545  u32 default_cfg; /* 0x288 */
546  #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
547  #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
548  #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
549  #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
550  #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
551  #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
552 
553  #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
554  #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
555  #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
556  #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
557  #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
558  #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
559 
560  #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
561  #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
562  #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
563  #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
564  #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
565  #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
566 
567  #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
568  #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
569  #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
570  #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
571  #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
572  #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
573 
574  /* When KR link is required to be set to force which is not
575  KR-compliant, this parameter determine what is the trigger for it.
576  When GPIO is selected, low input will force the speed. Currently
577  default speed is 1G. In the future, it may be widen to select the
578  forced speed in with another parameter. Note when force-1G is
579  enabled, it override option 56: Link Speed option. */
580  #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
581  #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
582  #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
583  #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
584  #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
585  #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
586  #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
587  #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
588  #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
589  #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
590  #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
591  #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
592  /* Enable to determine with which GPIO to reset the external phy */
593  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
594  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
595  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
596  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
597  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
598  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
599  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
600  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
601  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
602  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
603  #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
604 
605  /* Enable BAM on KR */
606  #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
607  #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
608  #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
609  #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
610 
611  /* Enable Common Mode Sense */
612  #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
613  #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
614  #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
615  #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
616 
617  /* Determine the Serdes electrical interface */
618  #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
619  #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
620  #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
621  #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
622  #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
623  #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
624  #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
625  #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
626 
627 
629  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
630  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
631  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
632  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
633  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
634  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
635  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
636  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
637  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
638  #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
639 
640  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
641  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
642  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
643  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
644  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
645  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
646  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
647  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
648  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
649  #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
650 
651 
652  /* In the case where two media types (e.g. copper and fiber) are
653  present and electrically active at the same time, PHY Selection
654  will determine which of the two PHYs will be designated as the
655  Active PHY and used for a connection to the network. */
656  u32 multi_phy_config; /* 0x290 */
657  #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
658  #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
659  #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
660  #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
661  #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
662  #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
663  #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
664 
665  /* When enabled, all second phy nvram parameters will be swapped
666  with the first phy parameters */
667  #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
668  #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
669  #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
670  #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
671 
672 
673  /* Address of the second external phy */
675  #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
676  #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
677 
678  /* The second XGXS external PHY type */
679  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
680  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
681  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
682  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
683  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
684  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
685  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
686  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
687  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
688  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
689  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
690  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
691  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
692  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
693  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
694  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
695  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
696  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
697  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
698  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
699  #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
700 
701 
702  /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
703  8706, 8726 and 8727) not all 4 values are needed. */
704  u16 xgxs_config2_rx[4]; /* 0x296 */
705  u16 xgxs_config2_tx[4]; /* 0x2A0 */
706 
708  #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
709  #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
710  /* AN and forced */
711  #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
712  /* forced only */
713  #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
714  /* forced only */
715  #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
716  /* forced only */
717  #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
718  #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
719  #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
720  #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
721  #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
722  #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
723  #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
724 
725  /* Indicate whether to swap the external phy polarity */
726  #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
727  #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
728  #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
729 
730 
732  #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
733  #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
734 
735  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
736  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
737  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
738  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
739  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
740  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
741  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
742  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
743  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
744  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
745  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
746  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
747  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
748  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
749  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
750  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
751  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
752  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
753  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
754  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
755  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
756  #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
757 
758  #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
759  #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
760 
761  #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
762  #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
763  #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
764  #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
765  #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
766  #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
767 
769  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
770  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
771  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
772  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
773  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
774  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
775  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
776  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
777  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
778  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
779  #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
780 
781  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
782  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
783  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
784  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
785  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
786  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
787  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
788  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
789  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
790  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
791  #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
792 
793  /* A place to hold the original MAC address as a backup */
794  u32 backup_mac_upper; /* 0x2B4 */
795  u32 backup_mac_lower; /* 0x2B8 */
796 
797 };
798 
799 
800 /****************************************************************************
801  * Shared Feature configuration *
802  ****************************************************************************/
803 struct shared_feat_cfg { /* NVRAM Offset */
804 
805  u32 config; /* 0x450 */
806  #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
807 
808  /* Use NVRAM values instead of HW default values */
809  #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
810  0x00000002
811  #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
812  0x00000000
813  #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
814  0x00000002
815 
816  #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
817  #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
818  #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
819 
820  #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
821  #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
822 
823  /* Override the OTP back to single function mode. When using GPIO,
824  high means only SF, 0 is according to CLP configuration */
825  #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
826  #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
827  #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
828  #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
829  #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
830  #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
831  #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
832 
833  /* The interval in seconds between sending LLDP packets. Set to zero
834  to disable the feature */
835  #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
836  #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
837 
838  /* The assigned device type ID for LLDP usage */
839  #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
840  #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
841 
842 };
843 
844 
845 /****************************************************************************
846  * Port Feature configuration *
847  ****************************************************************************/
848 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
849 
851  #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
852  #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
853  #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
854  #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
855  #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
856  #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
857  #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
858  #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
859  #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
860  #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
861  #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
862  #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
863  #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
864  #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
865  #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
866  #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
867  #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
868  #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
869  #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
870  #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
871  #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
872  #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
873  #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
874  #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
875  #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
876  #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
877  #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
878  #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
879  #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
880  #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
881  #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
882  #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
883  #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
884  #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
885  #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
886  #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
887 
888  #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
889  #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
890  #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
891 
892  #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
893  #define PORT_FEATURE_EN_SIZE_SHIFT 24
894  #define PORT_FEATURE_WOL_ENABLED 0x01000000
895  #define PORT_FEATURE_MBA_ENABLED 0x02000000
896  #define PORT_FEATURE_MFW_ENABLED 0x04000000
897 
898  /* Advertise expansion ROM even if MBA is disabled */
899  #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
900  #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
901  #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
902 
903  /* Check the optic vendor via i2c against a list of approved modules
904  in a separate nvram image */
905  #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
906  #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
907  #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
908  0x00000000
909  #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
910  0x20000000
911  #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
912  #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
913 
915  /* Default is used when driver sets to "auto" mode */
916  #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
917  #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
918  #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
919  #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
920  #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
921  #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
922  #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
923  #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
924  #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
925 
927  #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
928  #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
929  #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
930  #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
931  #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
932  #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
933  #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
934  #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
935 
936  #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
937  #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
938 
939  #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
940  #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
941  #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
942  #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
943  #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
944  #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
945  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
946  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
947  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
948  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
949  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
950  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
951  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
952  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
953  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
954  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
955  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
956  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
957  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
958  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
959  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
960  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
961  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
962  #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
963  #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
964  #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
965  #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
966  #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
967  #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
968  #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
969  #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
970  #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
971  #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
972  #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
973  #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
974  #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
975  #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
976  #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
977  #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
978  #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
979  #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
980  #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
981  #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
983  #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
984  #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
985  #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
986 
988  #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
989  #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
990  #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
991 
993  #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
994  #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
995  #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
996  #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
997  #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
998 
1000  #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1001  #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1002 
1004  #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1005  #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1006  #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1007  #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1008  #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1009  #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1010  #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1011  #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1012  #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1013  #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1014  #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1015  #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1016  #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1017  #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1018  #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1019  #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1020  #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1021  #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1022 
1023  u32 link_config; /* Used as HW defaults for the driver */
1024  #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1025  #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1026  /* (forced) low speed switch (< 10G) */
1027  #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1028  /* (forced) high speed switch (>= 10G) */
1029  #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1030  #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1031  #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1032 
1033  #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1034  #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1035  #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1036  #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1037  #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1038  #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1039  #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1040  #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1041  #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1042  #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1043  #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1044 
1045  #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1046  #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1047  #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1048  #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1049  #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1050  #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1051  #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1052 
1053  /* The default for MCP link configuration,
1054  uses the same defines as link_config */
1056 
1057  /* The default for the driver of the second external phy,
1058  uses the same defines as link_config */
1059  u32 link_config2; /* 0x47C */
1060 
1061  /* The default for MCP of the second external phy,
1062  uses the same defines as link_config */
1063  u32 mfw_wol_link_cfg2; /* 0x480 */
1064 
1065 
1066  /* EEE power saving mode */
1067  u32 eee_power_mode; /* 0x484 */
1068  #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1069  #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1070  #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1071  #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1072  #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1073  #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1074 
1075 
1076  u32 Reserved2[16]; /* 0x488 */
1077 };
1078 
1079 
1080 /****************************************************************************
1081  * Device Information *
1082  ****************************************************************************/
1083 struct shm_dev_info { /* size */
1084 
1085  u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
1086 
1088 
1089  struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
1090 
1092 
1094 
1095 };
1096 
1097 
1098 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1099  #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1100 #endif
1101 
1102 #define FUNC_0 0
1103 #define FUNC_1 1
1104 #define FUNC_2 2
1105 #define FUNC_3 3
1106 #define FUNC_4 4
1107 #define FUNC_5 5
1108 #define FUNC_6 6
1109 #define FUNC_7 7
1110 #define E1_FUNC_MAX 2
1111 #define E1H_FUNC_MAX 8
1112 #define E2_FUNC_MAX 4 /* per path */
1113 
1114 #define VN_0 0
1115 #define VN_1 1
1116 #define VN_2 2
1117 #define VN_3 3
1118 #define E1VN_MAX 1
1119 #define E1HVN_MAX 4
1120 
1121 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1122 /* This value (in milliseconds) determines the frequency of the driver
1123  * issuing the PULSE message code. The firmware monitors this periodic
1124  * pulse to determine when to switch to an OS-absent mode. */
1125 #define DRV_PULSE_PERIOD_MS 250
1126 
1127 /* This value (in milliseconds) determines how long the driver should
1128  * wait for an acknowledgement from the firmware before timing out. Once
1129  * the firmware has timed out, the driver will assume there is no firmware
1130  * running and there won't be any firmware-driver synchronization during a
1131  * driver reset. */
1132 #define FW_ACK_TIME_OUT_MS 5000
1133 
1134 #define FW_ACK_POLL_TIME_MS 1
1135 
1136 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1137 
1138 #define MFW_TRACE_SIGNATURE 0x54524342
1139 
1140 /****************************************************************************
1141  * Driver <-> FW Mailbox *
1142  ****************************************************************************/
1143 struct drv_port_mb {
1144 
1146  /* Driver should update this field on any link change event */
1147 
1148  #define LINK_STATUS_NONE (0<<0)
1149  #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1150  #define LINK_STATUS_LINK_UP 0x00000001
1151  #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1152  #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1153  #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1154  #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1155  #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1156  #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1157  #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1158  #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1159  #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1160  #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1161  #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1162  #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1163  #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1164  #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1165  #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1166  #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1167  #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1168 
1169  #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1170  #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1171 
1172  #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1173  #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1174  #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1175 
1176  #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1177  #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1178  #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1179  #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1180  #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1181  #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1182  #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1183 
1184  #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1185  #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1186 
1187  #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1188  #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1189 
1190  #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1191  #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1192  #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1193  #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1194  #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1195 
1196  #define LINK_STATUS_SERDES_LINK 0x00100000
1197 
1198  #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1199  #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1200  #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1201  #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1202 
1203  #define LINK_STATUS_PFC_ENABLED 0x20000000
1204 
1205  #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1206  #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1207 
1209 
1211 
1212  /* MCP firmware does not use this field */
1214 
1215 };
1216 
1217 
1218 struct drv_func_mb {
1219 
1221  #define DRV_MSG_CODE_MASK 0xffff0000
1222  #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1223  #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1224  #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1225  #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1226  #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1227  #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1228  #define DRV_MSG_CODE_DCC_OK 0x30000000
1229  #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1230  #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1231  #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1232  #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1233  #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1234  #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1235  #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1236  #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1237  /*
1238  * The optic module verification command requires bootcode
1239  * v5.0.6 or later, te specific optic module verification command
1240  * requires bootcode v5.2.12 or later
1241  */
1242  #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1243  #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1244  #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1245  #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1246  #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1247  #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1248  #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1249  #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1250  #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1251 
1252  #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1253  #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1254  #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1255 
1256  #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1257 
1258  #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1259  #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1260  #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1261  #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1262  #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1263 
1264  #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1265  #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1266 
1267  #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1268 
1269  #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1270  #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1271  #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1272 
1273  #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1274 
1275  #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1276  #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1277 
1278  #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1279  #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1280  #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1281  #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1282 
1283  #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1284 
1286  #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1287  #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1288 
1289  #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1290 
1291  #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1293  #define FW_MSG_CODE_MASK 0xffff0000
1294  #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1295  #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1296  #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1297  /* Load common chip is supported from bc 6.0.0 */
1298  #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1299  #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1300 
1301  #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1302  #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1303  #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1304  #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1305  #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1306  #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1307  #define FW_MSG_CODE_DCC_DONE 0x30100000
1308  #define FW_MSG_CODE_LLDP_DONE 0x40100000
1309  #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1310  #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1311  #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1312  #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1313  #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1314  #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1315  #define FW_MSG_CODE_NO_KEY 0x80f00000
1316  #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1317  #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1318  #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1319  #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1320  #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1321  #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1322  #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1323  #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1324  #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1325  #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1326  #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1327 
1328  #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1329  #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1330  #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1331  #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1332  #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1333 
1334  #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1335  #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1336 
1337  #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1338 
1339  #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1340  #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1341 
1342  #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1343 
1344  #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1345  #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1346  #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1347  #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1348 
1349  #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1350 
1352 
1354  #define DRV_PULSE_SEQ_MASK 0x00007fff
1355  #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1356  /*
1357  * The system time is in the format of
1358  * (year-2001)*12*32 + month*32 + day.
1359  */
1360  #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1361  /*
1362  * Indicate to the firmware not to go into the
1363  * OS-absent when it is not getting driver pulse.
1364  * This is used for debugging as well for PXE(MBA).
1365  */
1366 
1368  #define MCP_PULSE_SEQ_MASK 0x00007fff
1369  #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1370  /* Indicates to the driver not to assert due to lack
1371  * of MCP response */
1372  #define MCP_EVENT_MASK 0xffff0000
1373  #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1374 
1377 
1379  #define DRV_STATUS_PMF 0x00000001
1380  #define DRV_STATUS_VF_DISABLED 0x00000002
1381  #define DRV_STATUS_SET_MF_BW 0x00000004
1382  #define DRV_STATUS_LINK_EVENT 0x00000008
1383 
1384  #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1385  #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1386  #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1387  #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1388  #define DRV_STATUS_DCC_RESERVED1 0x00000800
1389  #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1390  #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1391 
1392  #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1393  #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1394  #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1395  #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1396  #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1397  #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1398  #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1399 
1400  #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1401 
1402  #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1403 
1405  #define VIRT_MAC_SIGN_MASK 0xffff0000
1406  #define VIRT_MAC_SIGNATURE 0x564d0000
1408 
1409 };
1410 
1411 
1412 /****************************************************************************
1413  * Management firmware state *
1414  ****************************************************************************/
1415 /* Allocate 440 bytes for management firmware */
1416 #define MGMTFW_STATE_WORD_SIZE 110
1417 
1420 };
1421 
1422 
1423 /****************************************************************************
1424  * Multi-Function configuration *
1425  ****************************************************************************/
1427 
1429  #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1430  /* set by CLP */
1431  #define SHARED_MF_CLP_EXIT 0x00000001
1432  /* set by MCP */
1433  #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1434 
1435 };
1436 
1437 struct port_mf_cfg {
1438 
1439  u32 dynamic_cfg; /* device control channel */
1440  #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1441  #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1442  #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1443 
1445 
1446 };
1447 
1448 struct func_mf_cfg {
1449 
1451  /* E/R/I/D */
1452  /* function 0 of each port cannot be hidden */
1453  #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1454 
1455  #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1456  #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1457  #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1458  #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1459  #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1460  #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1461  FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1462 
1463  #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1464  #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1465 
1466  /* PRI */
1467  /* 0 - low priority, 3 - high priority */
1468  #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1469  #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1470  #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1471 
1472  /* MINBW, MAXBW */
1473  /* value range - 0..100, increments in 100Mbps */
1474  #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1475  #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1476  #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1477  #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1478  #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1479  #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1480 
1481  u32 mac_upper; /* MAC */
1482  #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1483  #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1484  #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1486  #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1487 
1488  u32 e1hov_tag; /* VNI */
1489  #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1490  #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1491  #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1492 
1493  /* afex default VLAN ID - 12 bits */
1494  #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1495  #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
1496 
1498  #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
1499  #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
1500  #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
1501  #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
1502  #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
1503  #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
1504  #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
1505 
1507 };
1508 
1513 };
1514 
1515 /* This structure is not applicable and should not be accessed on 57711 */
1518  #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1519  #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1520  #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1521  #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1522  #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1523  #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1524 
1527 
1530 
1533 
1536 
1538  #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1539  #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1540  #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1541  #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1542  #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1543  #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1544 };
1545 
1546 struct mf_cfg {
1547 
1549  /* 0x8*2*2=0x20 */
1551  /* for all chips, there are 8 mf functions */
1552  struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1553  /*
1554  * Extended configuration per function - this array does not exist and
1555  * should not be accessed on 57711
1556  */
1557  struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1558 }; /* 0x224 */
1559 
1560 /****************************************************************************
1561  * Shared Memory Region *
1562  ****************************************************************************/
1563 struct shmem_region { /* SharedMem Offset (size) */
1564 
1565  u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1566  #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1567  #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1568  /* validity bits */
1569  #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1570  #define SHR_MEM_VALIDITY_MB 0x00200000
1571  #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1572  #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1573  /* One licensing bit should be set */
1574  #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1575  #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1576  #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1577  #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1578  /* Active MFW */
1579  #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1580  #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1581  #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1582  #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1583  #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1584  #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1585 
1586  struct shm_dev_info dev_info; /* 0x8 (0x438) */
1587 
1588  struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1589 
1590  /* FW information (for internal FW use) */
1591  u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1592  struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1593 
1594  struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1595 
1596 #ifdef BMAPI
1597  /* This is a variable length array */
1598  /* the number of function depends on the chip type */
1599  struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1600 #else
1601  /* the number of function depends on the chip type */
1602  struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1603 #endif /* BMAPI */
1604 
1605 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1606 
1607 /****************************************************************************
1608  * Shared Memory 2 Region *
1609  ****************************************************************************/
1610 /* The fw_flr_ack is actually built in the following way: */
1611 /* 8 bit: PF ack */
1612 /* 64 bit: VF ack */
1613 /* 8 bit: ios_dis_ack */
1614 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1615 /* u32. The fw must have the VF right after the PF since this is how it */
1616 /* access arrays(it expects always the VF to reside after the PF, and that */
1617 /* makes the calculation much easier for it. ) */
1618 /* In order to answer both limitations, and keep the struct small, the code */
1619 /* will abuse the structure defined here to achieve the actual partition */
1620 /* above */
1621 /****************************************************************************/
1622 struct fw_flr_ack {
1626 };
1627 
1628 struct fw_flr_mb {
1631  struct fw_flr_ack ack;
1632 };
1633 
1637 };
1638 
1639 /**** SUPPORT FOR SHMEM ARRRAYS ***
1640  * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1641  * define arrays with storage types smaller then unsigned dwords.
1642  * The macros below add generic support for SHMEM arrays with numeric elements
1643  * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1644  * array with individual bit-filed elements accessed using shifts and masks.
1645  *
1646  */
1647 
1648 /* eb is the bitwidth of a single element */
1649 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1650 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1651 
1652 /* the bit-position macro allows the used to flip the order of the arrays
1653  * elements on a per byte or word boundary.
1654  *
1655  * example: an array with 8 entries each 4 bit wide. This array will fit into
1656  * a single dword. The diagrmas below show the array order of the nibbles.
1657  *
1658  * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1659  *
1660  * | | | |
1661  * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1662  * | | | |
1663  *
1664  * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1665  *
1666  * | | | |
1667  * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1668  * | | | |
1669  *
1670  * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1671  *
1672  * | | | |
1673  * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1674  * | | | |
1675  */
1676 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1677  ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1678  (((i)%((fb)/(eb))) * (eb)))
1679 
1680 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1681  ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1682  SHMEM_ARRAY_MASK(eb))
1683 
1684 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1685 do { \
1686  a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1687  SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1688  a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1689  SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1690 } while (0)
1691 
1692 
1693 /****START OF DCBX STRUCTURES DECLARATIONS****/
1694 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1695 #define DCBX_PRI_PG_BITWIDTH 4
1696 #define DCBX_PRI_PG_FBITS 8
1697 #define DCBX_PRI_PG_GET(a, i) \
1698  SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1699 #define DCBX_PRI_PG_SET(a, i, val) \
1700  SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1701 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1702 #define DCBX_BW_PG_BITWIDTH 8
1703 #define DCBX_PG_BW_GET(a, i) \
1704  SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1705 #define DCBX_PG_BW_SET(a, i, val) \
1706  SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1707 #define DCBX_STRICT_PRI_PG 15
1708 #define DCBX_MAX_APP_PROTOCOL 16
1709 #define FCOE_APP_IDX 0
1710 #define ISCSI_APP_IDX 1
1711 #define PREDEFINED_APP_IDX_MAX 2
1712 
1713 
1714 /* Big/Little endian have the same representation. */
1716  /*
1717  * For Admin MIB - is this feature supported by the
1718  * driver | For Local MIB - should this feature be enabled.
1719  */
1723 };
1724 
1725 /* Driver structure in LE */
1727 #ifdef __BIG_ENDIAN
1728  u8 pri_en_bitmap;
1729  #define DCBX_PFC_PRI_0 0x01
1730  #define DCBX_PFC_PRI_1 0x02
1731  #define DCBX_PFC_PRI_2 0x04
1732  #define DCBX_PFC_PRI_3 0x08
1733  #define DCBX_PFC_PRI_4 0x10
1734  #define DCBX_PFC_PRI_5 0x20
1735  #define DCBX_PFC_PRI_6 0x40
1736  #define DCBX_PFC_PRI_7 0x80
1737  u8 pfc_caps;
1738  u8 reserved;
1739  u8 enabled;
1740 #elif defined(__LITTLE_ENDIAN)
1741  u8 enabled;
1742  u8 reserved;
1743  u8 pfc_caps;
1744  u8 pri_en_bitmap;
1745  #define DCBX_PFC_PRI_0 0x01
1746  #define DCBX_PFC_PRI_1 0x02
1747  #define DCBX_PFC_PRI_2 0x04
1748  #define DCBX_PFC_PRI_3 0x08
1749  #define DCBX_PFC_PRI_4 0x10
1750  #define DCBX_PFC_PRI_5 0x20
1751  #define DCBX_PFC_PRI_6 0x40
1752  #define DCBX_PFC_PRI_7 0x80
1753 #endif
1754 };
1755 
1757 #ifdef __BIG_ENDIAN
1758  u16 app_id;
1759  u8 pri_bitmap;
1760  u8 appBitfield;
1761  #define DCBX_APP_ENTRY_VALID 0x01
1762  #define DCBX_APP_ENTRY_SF_MASK 0x30
1763  #define DCBX_APP_ENTRY_SF_SHIFT 4
1764  #define DCBX_APP_SF_ETH_TYPE 0x10
1765  #define DCBX_APP_SF_PORT 0x20
1766 #elif defined(__LITTLE_ENDIAN)
1767  u8 appBitfield;
1768  #define DCBX_APP_ENTRY_VALID 0x01
1769  #define DCBX_APP_ENTRY_SF_MASK 0x30
1770  #define DCBX_APP_ENTRY_SF_SHIFT 4
1771  #define DCBX_APP_SF_ETH_TYPE 0x10
1772  #define DCBX_APP_SF_PORT 0x20
1773  u8 pri_bitmap;
1774  u16 app_id;
1775 #endif
1776 };
1777 
1778 
1779 /* FW structure in BE */
1781 #ifdef __BIG_ENDIAN
1782  u8 reserved;
1783  u8 default_pri;
1784  u8 tc_supported;
1785  u8 enabled;
1786 #elif defined(__LITTLE_ENDIAN)
1787  u8 enabled;
1788  u8 tc_supported;
1789  u8 default_pri;
1790  u8 reserved;
1791 #endif
1793 };
1794 
1795 /* FW structure in BE */
1797  /* PG feature */
1799  /* PFC feature */
1801  /* APP feature */
1803 };
1804 
1805 /* LLDP protocol parameters */
1806 /* FW structure in BE */
1807 struct lldp_params {
1808 #ifdef __BIG_ENDIAN
1809  u8 msg_fast_tx_interval;
1810  u8 msg_tx_hold;
1811  u8 msg_tx_interval;
1812  u8 admin_status;
1813  #define LLDP_TX_ONLY 0x01
1814  #define LLDP_RX_ONLY 0x02
1815  #define LLDP_TX_RX 0x03
1816  #define LLDP_DISABLED 0x04
1817  u8 reserved1;
1818  u8 tx_fast;
1819  u8 tx_crd_max;
1820  u8 tx_crd;
1821 #elif defined(__LITTLE_ENDIAN)
1822  u8 admin_status;
1823  #define LLDP_TX_ONLY 0x01
1824  #define LLDP_RX_ONLY 0x02
1825  #define LLDP_TX_RX 0x03
1826  #define LLDP_DISABLED 0x04
1827  u8 msg_tx_interval;
1828  u8 msg_tx_hold;
1829  u8 msg_fast_tx_interval;
1830  u8 tx_crd;
1831  u8 tx_crd_max;
1832  u8 tx_fast;
1833  u8 reserved1;
1834 #endif
1835  #define REM_CHASSIS_ID_STAT_LEN 4
1836  #define REM_PORT_ID_STAT_LEN 4
1837  /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1839  /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1841 };
1842 
1844  #define LOCAL_CHASSIS_ID_STAT_LEN 2
1845  #define LOCAL_PORT_ID_STAT_LEN 2
1846  /* Holds local Chassis ID 8B payload of constant subtype 4. */
1848  /* Holds local Port ID 8B payload of constant subtype 3. */
1850  /* Number of DCBX frames transmitted. */
1852  /* Number of DCBX frames received. */
1854 };
1855 
1856 /* ADMIN MIB - DCBX local machine default configuration. */
1859  #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1860  #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1861  #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1862  #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1863  #define DCBX_ETS_RECO_VALID 0x00000010
1864  #define DCBX_ETS_WILLING 0x00000020
1865  #define DCBX_PFC_WILLING 0x00000040
1866  #define DCBX_APP_WILLING 0x00000080
1867  #define DCBX_VERSION_CEE 0x00000100
1868  #define DCBX_VERSION_IEEE 0x00000200
1869  #define DCBX_DCBX_ENABLED 0x00000400
1870  #define DCBX_CEE_VERSION_MASK 0x0000f000
1871  #define DCBX_CEE_VERSION_SHIFT 12
1872  #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1873  #define DCBX_CEE_MAX_VERSION_SHIFT 16
1875 };
1876 
1877 /* REMOTE MIB - remote machine DCBX configuration. */
1881  #define DCBX_ETS_TLV_RX 0x00000001
1882  #define DCBX_PFC_TLV_RX 0x00000002
1883  #define DCBX_APP_TLV_RX 0x00000004
1884  #define DCBX_ETS_RX_ERROR 0x00000010
1885  #define DCBX_PFC_RX_ERROR 0x00000020
1886  #define DCBX_APP_RX_ERROR 0x00000040
1887  #define DCBX_ETS_REM_WILLING 0x00000100
1888  #define DCBX_PFC_REM_WILLING 0x00000200
1889  #define DCBX_APP_REM_WILLING 0x00000400
1890  #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1891  #define DCBX_REMOTE_MIB_VALID 0x00002000
1894 };
1895 
1896 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1899  /* Indicates if there is mismatch with negotiation results. */
1901  #define DCBX_LOCAL_ETS_ERROR 0x00000001
1902  #define DCBX_LOCAL_PFC_ERROR 0x00000002
1903  #define DCBX_LOCAL_APP_ERROR 0x00000004
1904  #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1905  #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1906  #define DCBX_REMOTE_MIB_ERROR 0x00000040
1907  #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1908  #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1909  #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1912 };
1913 /***END OF DCBX STRUCTURES DECLARATIONS***/
1914 
1915 /***********************************************************/
1916 /* Elink section */
1917 /***********************************************************/
1918 #define SHMEM_LINK_CONFIG_SIZE 2
1919 struct shmem_lfa {
1921  #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
1922  #define REQ_DUPLEX_PHY0_SHIFT 0
1923  #define REQ_DUPLEX_PHY1_MASK 0xffff0000
1924  #define REQ_DUPLEX_PHY1_SHIFT 16
1926  #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
1927  #define REQ_FLOW_CTRL_PHY0_SHIFT 0
1928  #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
1929  #define REQ_FLOW_CTRL_PHY1_SHIFT 16
1930  u32 req_line_speed; /* Also determine AutoNeg */
1931  #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
1932  #define REQ_LINE_SPD_PHY0_SHIFT 0
1933  #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
1934  #define REQ_LINE_SPD_PHY1_SHIFT 16
1937  #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
1938  #define REQ_FC_AUTO_ADV0_SHIFT 0
1939  #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
1941  #define LFA_LINK_FLAP_REASON_OFFSET 0
1942  #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
1943  #define LFA_LINK_DOWN 0x1
1944  #define LFA_LOOPBACK_ENABLED 0x2
1945  #define LFA_DUPLEX_MISMATCH 0x3
1946  #define LFA_MFW_IS_TOO_OLD 0x4
1947  #define LFA_LINK_SPEED_MISMATCH 0x5
1948  #define LFA_FLOW_CTRL_MISMATCH 0x6
1949  #define LFA_SPEED_CAP_MISMATCH 0x7
1950  #define LFA_DCC_LFA_DISABLED 0x8
1951  #define LFA_EEE_MISMATCH 0x9
1952 
1953  #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
1954  #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
1955 
1956  #define LINK_FLAP_COUNT_OFFSET 16
1957  #define LINK_FLAP_COUNT_MASK 0x00ff0000
1958 
1959  #define LFA_FLAGS_MASK 0xff000000
1960  #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
1961 };
1962 
1965  #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
1966  #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
1967 
1968  #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
1969  #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
1970 
1972  #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
1973  #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
1974 
1975  #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
1976  #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
1977 
1979  #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
1980  #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
1981 
1982  #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
1983  #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
1984 
1986  #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
1987  #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
1988 };
1989 
1993 };
1994 
1996 
1997  u32 size; /* 0x0000 */
1998 
1999  u32 dcc_support; /* 0x0004 */
2000  #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2001  #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2002  #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2003  #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2004  #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2005  #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2006 
2008  /*
2009  * For backwards compatibility, if the mf_cfg_addr does not exist
2010  * (the size filed is smaller than 0xc) the mf_cfg resides at the
2011  * end of struct shmem_region
2012  */
2013  u32 mf_cfg_addr; /* 0x0010 */
2014  #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2015 
2016  struct fw_flr_mb flr_mb; /* 0x0014 */
2018  #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2019  u32 dcbx_neg_res_offset; /* 0x002c */
2020  #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2022  #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2023  /*
2024  * The other shmemX_base_addr holds the other path's shmem address
2025  * required for example in case of common phy init, or for path1 to know
2026  * the address of mcp debug trace which is located in offset from shmem
2027  * of path0
2028  */
2031  /*
2032  * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2033  * which were disabled/flred
2034  */
2035  u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
2036 
2037  /*
2038  * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2039  * VFs
2040  */
2042 
2044  #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2045 
2046  /*
2047  * edebug_driver_if field is used to transfer messages between edebug
2048  * app to the driver through shmem2.
2049  *
2050  * message format:
2051  * bits 0-2 - function number / instance of driver to perform request
2052  * bits 3-5 - op code / is_ack?
2053  * bits 6-63 - data
2054  */
2055  u32 edebug_driver_if[2]; /* 0x0068 */
2056  #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
2057  #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
2058  #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
2059 
2061 
2062  /* afex support of that driver */
2063  u32 afex_driver_support; /* 0x0074 */
2064  #define SHMEM_AFEX_VERSION_MASK 0x100f
2065  #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2066  #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2067 
2068  /* driver receives addr in scratchpad to which it should respond */
2070 
2071  /* generic params from MCP to driver (value depends on the msg sent
2072  * to driver
2073  */
2076 
2077  u32 swim_base_addr; /* 0x0108 */
2080 
2081  /* bitmap notifying which VIF profiles stored in nvram are enabled by
2082  * switch
2083  */
2085 
2086  /* generic flags controlled by the driver */
2088  #define DRV_FLAGS_DCB_CONFIGURED 0x1
2089 
2090  /* pointer to extended dev_info shared data copied from nvm image */
2093 
2094  u32 ocsd_host_addr; /* initialized by option ROM */
2095  u32 ocbb_host_addr; /* initialized by option ROM */
2096  u32 ocsd_req_update_interval; /* initialized by option ROM */
2099 
2101 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2102 
2104 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2105 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2106 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2107 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2108 
2110 
2112 
2113  /* The offset points to the multi threaded meta structure */
2115 
2116  /* address of DMAable host address holding values from the drivers */
2119 
2120  /* general values written by the MFW (such as current version) */
2122 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2123 #define DRV_INFO_CONTROL_VER_SHIFT 0
2124 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2125 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2126  u32 ibft_host_addr; /* initialized by option ROM */
2129 
2130 
2131  /* the status of EEE auto-negotiation
2132  * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2133  * bits 19:16 the supported modes for EEE.
2134  * bits 23:20 the speeds advertised for EEE.
2135  * bits 27:24 the speeds the Link partner advertised for EEE.
2136  * The supported/adv. modes in bits 27:19 originate from the
2137  * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2138  * bit 28 when 1'b1 EEE was requested.
2139  * bit 29 when 1'b1 tx lpi was requested.
2140  * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2141  * 30:29 are 2'b11.
2142  * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2143  * value. When 1'b1 those bits contains a value times 16 microseconds.
2144  */
2146  #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2147  #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2148  #define SHMEM_EEE_SUPPORTED_SHIFT 16
2149  #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2150  #define SHMEM_EEE_100M_ADV (1<<0)
2151  #define SHMEM_EEE_1G_ADV (1<<1)
2152  #define SHMEM_EEE_10G_ADV (1<<2)
2153  #define SHMEM_EEE_ADV_STATUS_SHIFT 20
2154  #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2155  #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
2156  #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2157  #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2158  #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2159  #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2160 
2162 };
2163 
2164 
2165 struct emac_stats {
2189 
2191 
2214 };
2215 
2216 
2217 struct bmac1_stats {
2260 
2319 };
2320 
2321 struct bmac2_stats {
2322  u32 tx_stat_gtpk_lo; /* gtpok */
2323  u32 tx_stat_gtpk_hi; /* gtpok */
2324  u32 tx_stat_gtxpf_lo; /* gtpf */
2325  u32 tx_stat_gtxpf_hi; /* gtpf */
2326  u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
2327  u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
2330  u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
2331  u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
2340  u32 tx_stat_gtpkt1_lo; /* gtpkt */
2341  u32 tx_stat_gtpkt1_hi; /* gtpkt */
2370 
2403  u32 rx_stat_grxpf_lo; /* grpf */
2404  u32 rx_stat_grxpf_hi; /* grpf */
2407  u32 rx_stat_grxuo_lo; /* gruo */
2408  u32 rx_stat_grxuo_hi; /* gruo */
2413  u32 rx_stat_grxcf_lo; /* grcf */
2414  u32 rx_stat_grxcf_hi; /* grcf */
2429  u32 rx_stat_grerb_lo; /* grerrbyt */
2430  u32 rx_stat_grerb_hi; /* grerrbyt */
2431  u32 rx_stat_grfre_lo; /* grfrerr */
2432  u32 rx_stat_grfre_hi; /* grfrerr */
2435 };
2436 
2437 struct mstat_stats {
2438  struct {
2439  /* OTE MSTAT on E3 has a bug where this register's contents are
2440  * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2441  */
2496  } stats_tx;
2497 
2498  struct {
2553 
2560  } stats_rx;
2561 };
2562 
2563 union mac_stats {
2568 };
2569 
2570 
2571 struct mac_stx {
2572  /* in_bad_octets */
2575 
2576  /* out_bad_octets */
2579 
2580  /* crc_receive_errors */
2583  /* alignment_errors */
2586  /* carrier_sense_errors */
2589  /* false_carrier_detections */
2592 
2593  /* runt_packets_received */
2596  /* jabber_packets_received */
2599 
2600  /* error_runt_packets_received */
2603  /* error_jabber_packets_received */
2606 
2607  /* control_frames_received */
2614 
2615  /* xoff_state_entered */
2618  /* pause_xon_frames_received */
2621  /* pause_xoff_frames_received */
2624  /* pause_xon_frames_transmitted */
2627  /* pause_xoff_frames_transmitted */
2630  /* flow_control_done */
2633 
2634  /* ether_stats_collisions */
2637  /* single_collision_transmit_frames */
2640  /* multiple_collision_transmit_frames */
2643  /* deferred_transmissions */
2646  /* excessive_collision_frames */
2649  /* late_collision_frames */
2652 
2653  /* frames_transmitted_64_bytes */
2656  /* frames_transmitted_65_127_bytes */
2659  /* frames_transmitted_128_255_bytes */
2662  /* frames_transmitted_256_511_bytes */
2665  /* frames_transmitted_512_1023_bytes */
2668  /* frames_transmitted_1024_1522_bytes */
2671  /* frames_transmitted_1523_9022_bytes */
2682 
2683  /* internal_mac_transmit_errors */
2686 
2687  /* if_out_discards */
2690 };
2691 
2692 
2693 #define MAC_STX_IDX_MAX 2
2694 
2697 
2699 
2702 
2703  u32 not_used; /* obsolete */
2708 
2711 };
2712 
2713 
2716 
2719 
2722 
2725 
2728 
2731 
2734 
2737 
2740 
2743 
2745 };
2746 
2747 /* VIC definitions */
2748 #define VICSTATST_UIF_INDEX 2
2749 
2750 
2751 /* stats collected for afex.
2752  * NOTE: structure is exactly as expected to be received by the switch.
2753  * order must remain exactly as is unless protocol changes !
2754  */
2755 struct afex_stats {
2772 
2789 };
2790 
2791 #define BCM_5710_FW_MAJOR_VERSION 7
2792 #define BCM_5710_FW_MINOR_VERSION 8
2793 #define BCM_5710_FW_REVISION_VERSION 2
2794 #define BCM_5710_FW_ENGINEERING_VERSION 0
2795 #define BCM_5710_FW_COMPILE_FLAGS 1
2796 
2797 
2798 /*
2799  * attention bits
2800  */
2808 };
2809 
2810 
2811 /*
2812  * The eth aggregative context of Cstorm
2813  */
2816 };
2817 
2818 
2819 /*
2820  * dmae command structure
2821  */
2824 #define DMAE_COMMAND_SRC (0x1<<0)
2825 #define DMAE_COMMAND_SRC_SHIFT 0
2826 #define DMAE_COMMAND_DST (0x3<<1)
2827 #define DMAE_COMMAND_DST_SHIFT 1
2828 #define DMAE_COMMAND_C_DST (0x1<<3)
2829 #define DMAE_COMMAND_C_DST_SHIFT 3
2830 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2831 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2832 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2833 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2834 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2835 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2836 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2837 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2838 #define DMAE_COMMAND_PORT (0x1<<11)
2839 #define DMAE_COMMAND_PORT_SHIFT 11
2840 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2841 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2842 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2843 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2844 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2845 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2846 #define DMAE_COMMAND_E1HVN (0x3<<15)
2847 #define DMAE_COMMAND_E1HVN_SHIFT 15
2848 #define DMAE_COMMAND_DST_VN (0x3<<17)
2849 #define DMAE_COMMAND_DST_VN_SHIFT 17
2850 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2851 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2852 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2853 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2854 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2855 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2860 #if defined(__BIG_ENDIAN)
2861  u16 opcode_iov;
2862 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2863 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2864 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2865 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2866 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2867 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2868 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2869 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2870 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2871 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2872 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2873 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2874  u16 len;
2875 #elif defined(__LITTLE_ENDIAN)
2876  u16 len;
2877  u16 opcode_iov;
2878 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2879 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2880 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2881 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2882 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2883 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2884 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2885 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2886 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2887 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2888 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2889 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2890 #endif
2896 #if defined(__BIG_ENDIAN)
2897  u16 crc16_c;
2898  u16 crc16;
2899 #elif defined(__LITTLE_ENDIAN)
2900  u16 crc16;
2901  u16 crc16_c;
2902 #endif
2903 #if defined(__BIG_ENDIAN)
2904  u16 reserved3;
2905  u16 crc_t10;
2906 #elif defined(__LITTLE_ENDIAN)
2907  u16 crc_t10;
2908  u16 reserved3;
2909 #endif
2910 #if defined(__BIG_ENDIAN)
2911  u16 xsum8;
2912  u16 xsum16;
2913 #elif defined(__LITTLE_ENDIAN)
2914  u16 xsum16;
2915  u16 xsum8;
2916 #endif
2917 };
2918 
2919 
2920 /*
2921  * common data for all protocols
2922  */
2925 #define DOORBELL_HDR_RX (0x1<<0)
2926 #define DOORBELL_HDR_RX_SHIFT 0
2927 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
2928 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
2929 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2930 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2931 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2932 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2933 };
2934 
2935 /*
2936  * Ethernet doorbell
2937  */
2939 #if defined(__BIG_ENDIAN)
2940  u16 npackets;
2941  u8 params;
2942 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2943 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2944 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2945 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2946 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2947 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2948  struct doorbell_hdr hdr;
2949 #elif defined(__LITTLE_ENDIAN)
2950  struct doorbell_hdr hdr;
2951  u8 params;
2952 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2953 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2954 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2955 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2956 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2957 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2958  u16 npackets;
2959 #endif
2960 };
2961 
2962 
2963 /*
2964  * 3 lines. status block
2965  */
2970 };
2971 
2972 /*
2973  * host status block
2974  */
2977 };
2978 
2979 
2980 /*
2981  * 3 lines. status block
2982  */
2987 };
2988 
2989 /*
2990  * host status block
2991  */
2994 };
2995 
2996 
2997 /*
2998  * 5 lines. slow-path status block
2999  */
3005 };
3006 
3007 /*
3008  * host status block
3009  */
3013 };
3014 
3015 
3016 /*
3017  * IGU driver acknowledgment register
3018  */
3020 #if defined(__BIG_ENDIAN)
3021  u16 sb_id_and_flags;
3022 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3023 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3024 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3025 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3026 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3027 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3028 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3029 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3030 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3031 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3032  u16 status_block_index;
3033 #elif defined(__LITTLE_ENDIAN)
3034  u16 status_block_index;
3035  u16 sb_id_and_flags;
3036 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3037 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3038 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3039 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3040 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3041 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3042 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3043 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3044 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3045 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3046 #endif
3047 };
3048 
3049 
3050 /*
3051  * IGU driver acknowledgement register
3052  */
3055 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3056 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3057 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3058 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3059 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3060 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3061 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3062 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3063 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3064 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3065 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3066 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3068 };
3069 
3070 
3071 /*
3072  * IGU driver acknowledgement register
3073  */
3074 struct igu_regular {
3076 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3077 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3078 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3079 #define IGU_REGULAR_RESERVED0_SHIFT 20
3080 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3081 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3082 #define IGU_REGULAR_BUPDATE (0x1<<24)
3083 #define IGU_REGULAR_BUPDATE_SHIFT 24
3084 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3085 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3086 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3087 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3088 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3089 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3090 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3091 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3092 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3093 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3095 };
3096 
3097 /*
3098  * IGU driver acknowledgement register
3099  */
3103 };
3104 
3105 
3106 /*
3107  * Igu control commands
3108  */
3113 };
3114 
3115 
3116 /*
3117  * Control register for the IGU command register
3118  */
3121 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3122 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3123 #define IGU_CTRL_REG_FID (0x7F<<12)
3124 #define IGU_CTRL_REG_FID_SHIFT 12
3125 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3126 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3127 #define IGU_CTRL_REG_TYPE (0x1<<20)
3128 #define IGU_CTRL_REG_TYPE_SHIFT 20
3129 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3130 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3131 };
3132 
3133 
3134 /*
3135  * Igu interrupt command
3136  */
3143 };
3144 
3145 
3146 /*
3147  * Igu segments
3148  */
3154 };
3155 
3156 
3157 /*
3158  * Parser parsing flags field
3159  */
3162 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3163 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3164 #define PARSING_FLAGS_VLAN (0x1<<1)
3165 #define PARSING_FLAGS_VLAN_SHIFT 1
3166 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3167 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3168 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3169 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3170 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3171 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3172 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3173 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3174 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3175 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3176 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3177 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3178 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3179 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3180 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3181 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3182 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3183 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3184 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3185 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3186 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3187 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3188 };
3189 
3190 
3191 /*
3192  * Parsing flags for TCP ACK type
3193  */
3198 };
3199 
3200 
3201 /*
3202  * Parsing flags for Ethernet address type
3203  */
3208 };
3209 
3210 
3211 /*
3212  * Parsing flags for over-ethernet protocol
3213  */
3220 };
3221 
3222 
3223 /*
3224  * Parsing flags for over-IP protocol
3225  */
3231 };
3232 
3233 
3234 /*
3235  * SDM operation gen command (generate aggregative interrupt)
3236  */
3237 struct sdm_op_gen {
3239 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3240 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3241 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3242 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3243 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3244 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3245 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3246 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3247 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3248 #define SDM_OP_GEN_RESERVED_SHIFT 17
3249 };
3250 
3251 
3252 /*
3253  * Timers connection context
3254  */
3260 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3261 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3262 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3263 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3264 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3265 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3266 };
3267 
3268 
3269 /*
3270  * The eth aggregative context of Tstorm
3271  */
3274 };
3275 
3276 
3277 /*
3278  * The eth aggregative context of Ustorm
3279  */
3282 #if defined(__BIG_ENDIAN)
3283  u8 cdu_usage;
3284  u8 __reserved2;
3285  u16 __reserved1;
3286 #elif defined(__LITTLE_ENDIAN)
3287  u16 __reserved1;
3288  u8 __reserved2;
3289  u8 cdu_usage;
3290 #endif
3292 };
3293 
3294 
3295 /*
3296  * The eth aggregative context of Xstorm
3297  */
3300 #if defined(__BIG_ENDIAN)
3301  u8 cdu_reserved;
3302  u8 reserved2;
3303  u16 reserved1;
3304 #elif defined(__LITTLE_ENDIAN)
3305  u16 reserved1;
3306  u8 reserved2;
3307  u8 cdu_reserved;
3308 #endif
3310 };
3311 
3312 
3313 /*
3314  * doorbell message sent to the chip
3315  */
3316 struct doorbell {
3317 #if defined(__BIG_ENDIAN)
3318  u16 zero_fill2;
3319  u8 zero_fill1;
3320  struct doorbell_hdr header;
3321 #elif defined(__LITTLE_ENDIAN)
3322  struct doorbell_hdr header;
3323  u8 zero_fill1;
3324  u16 zero_fill2;
3325 #endif
3326 };
3327 
3328 
3329 /*
3330  * doorbell message sent to the chip
3331  */
3333 #if defined(__BIG_ENDIAN)
3334  u16 prod;
3335  u8 zero_fill1;
3336  struct doorbell_hdr header;
3337 #elif defined(__LITTLE_ENDIAN)
3338  struct doorbell_hdr header;
3339  u8 zero_fill1;
3340  u16 prod;
3341 #endif
3342 };
3343 
3344 
3345 struct regpair {
3348 };
3349 
3350 
3351 /*
3352  * Classify rule opcodes in E2/E3
3353  */
3354 enum classify_rule {
3359 };
3360 
3361 
3362 /*
3363  * Classify rule types in E2/E3
3364  */
3365 enum classify_rule_action_type {
3369 };
3370 
3371 
3372 /*
3373  * client init ramrod data
3374  */
3388 };
3389 
3390 
3391 /*
3392  * client init rx data
3393  */
3396 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3397 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3398 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3399 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3400 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3401 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3402 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3403 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3432 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3433 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3434 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3435 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3436 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3437 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3438 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3439 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3440 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3441 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3442 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3443 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3444 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3445 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3446 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3447 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3458 };
3459 
3460 /*
3461  * client init tx data
3462  */
3473 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3474 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3475 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3476 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3477 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3478 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3479 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3480 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3481 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3482 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3486 };
3487 
3488 /*
3489  * client init ramrod data
3490  */
3495 };
3496 
3497 
3498 /*
3499  * client update ramrod data
3500  */
3520 };
3521 
3522 
3523 /*
3524  * The eth storm context of Cstorm
3525  */
3528 };
3529 
3530 
3536 };
3537 
3538 
3539 /*
3540  * Ethernet address typesm used in ethernet tx BDs
3541  */
3548 };
3549 
3550 
3551 /*
3552  *
3553  */
3556 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3557 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3558 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3559 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3560 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3561 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3562 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3563 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3564 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3565 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3569 };
3570 
3571 
3572 /*
3573  * header for eth classification config ramrod
3574  */
3580 };
3581 
3582 
3583 /*
3584  * Command for adding/removing a MAC classification rule
3585  */
3593 };
3594 
3595 
3596 /*
3597  * Command for adding/removing a MAC-VLAN pair classification rule
3598  */
3606 };
3607 
3608 
3609 /*
3610  * Command for adding/removing a VLAN classification rule
3611  */
3618 };
3619 
3620 /*
3621  * union for eth classification rule
3622  */
3627 };
3628 
3629 /*
3630  * parameters for eth classification configuration ramrod
3631  */
3635 };
3636 
3637 
3638 /*
3639  * The data contain client ID need to the ramrod
3640  */
3644 };
3645 
3646 
3647 /*
3648  * The eth storm context of Ustorm
3649  */
3652 };
3653 
3654 /*
3655  * The eth storm context of Tstorm
3656  */
3659 };
3660 
3661 /*
3662  * The eth storm context of Xstorm
3663  */
3666 };
3667 
3668 /*
3669  * Ethernet connection context
3670  */
3671 struct eth_context {
3681 };
3682 
3683 
3684 /*
3685  * union for sgl and raw data.
3686  */
3690 };
3691 
3692 /*
3693  * eth FP end aggregation CQE parameters struct
3694  */
3697 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3698 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3699 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3700 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3701 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3702 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3714 };
3715 
3716 
3717 /*
3718  * regular eth FP CQE parameters struct
3719  */
3722 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3723 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3724 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3725 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3726 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3727 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3728 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3729 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3730 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3731 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3732 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3733 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3735 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3736 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3737 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3738 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3739 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3740 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3741 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3742 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3743 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3744 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3745 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3746 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3756 };
3757 
3758 
3759 /*
3760  * Command for setting classification flags for a client
3761  */
3764 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3765 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3766 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3767 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3768 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3769 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3774 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3775 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3776 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3777 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3778 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3779 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3780 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3781 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3782 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3783 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3784 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3785 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3786 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3787 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3788 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3789 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3792 };
3793 
3794 
3795 /*
3796  * parameters for eth classification filters ramrod
3797  */
3801 };
3802 
3803 
3804 /*
3805  * parameters for eth classification configuration ramrod
3806  */
3810 };
3811 
3812 
3813 /*
3814  * The data for Halt ramrod
3815  */
3819 };
3820 
3821 
3822 /*
3823  * Command for setting multicast classification for a client
3824  */
3827 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3828 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3829 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3830 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3831 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3832 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3833 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3834 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3840 };
3841 
3842 
3843 /*
3844  * parameters for multicast classification ramrod
3845  */
3849 };
3850 
3851 
3852 /*
3853  * Place holder for ramrods protocol specific data
3854  */
3855 struct ramrod_data {
3858 };
3859 
3860 /*
3861  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
3862  */
3865 };
3866 
3867 
3868 /*
3869  * RSS toeplitz hash type, as reported in CQE
3870  */
3881 };
3882 
3883 
3884 /*
3885  * Ethernet RSS mode
3886  */
3894 };
3895 
3896 
3897 /*
3898  * parameters for RSS update ramrod (E2)
3899  */
3903 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3904 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3905 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3906 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3907 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3908 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3909 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3910 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3911 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3912 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3913 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3914 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3915 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)
3916 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
3924 };
3925 
3926 
3927 /*
3928  * The eth Rx Buffer Descriptor
3929  */
3930 struct eth_rx_bd {
3933 };
3934 
3935 
3936 /*
3937  * Eth Rx Cqe structure- general structure for ramrods
3938  */
3941 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
3942 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
3943 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
3944 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
3945 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
3946 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
3950 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
3951 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
3952 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
3953 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
3957 };
3958 
3959 /*
3960  * Rx Last CQE in page (in ETH)
3961  */
3966 };
3967 
3968 /*
3969  * union for all eth rx cqe types (fix their sizes)
3970  */
3971 union eth_rx_cqe {
3976 };
3977 
3978 
3979 /*
3980  * Values for RX ETH CQE type field
3981  */
3988 };
3989 
3990 
3991 /*
3992  * Type of SGL/Raw field in ETH RX fast path CQE
3993  */
3998 };
3999 
4000 
4001 /*
4002  * The eth Rx SGE Descriptor
4003  */
4004 struct eth_rx_sge {
4007 };
4008 
4009 
4010 /*
4011  * common data for all protocols
4012  */
4013 struct spe_hdr {
4015 #define SPE_HDR_CID (0xFFFFFF<<0)
4016 #define SPE_HDR_CID_SHIFT 0
4017 #define SPE_HDR_CMD_ID (0xFF<<24)
4018 #define SPE_HDR_CMD_ID_SHIFT 24
4020 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4021 #define SPE_HDR_CONN_TYPE_SHIFT 0
4022 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4023 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4025 };
4026 
4027 /*
4028  * specific data for ethernet slow path element
4029  */
4040 };
4041 
4042 /*
4043  * Ethernet slow path element
4044  */
4045 struct eth_spe {
4046  struct spe_hdr hdr;
4048 };
4049 
4050 
4051 /*
4052  * Ethernet command ID for slow path elements
4053  */
4070 };
4071 
4072 
4073 /*
4074  * eth tpa update command
4075  */