#include "bnx2x_fw_defs.h"
#include "bnx2x_mfw_req.h"

Data Structures
struct	license_key

struct	shared_hw_cfg

struct	port_hw_cfg

struct	shared_feat_cfg

struct	port_feat_cfg

struct	shm_dev_info

struct	drv_port_mb

struct	drv_func_mb

struct	mgmtfw_state

struct	shared_mf_cfg

struct	port_mf_cfg

struct	func_mf_cfg

struct	func_ext_cfg

struct	mf_cfg

struct	shmem_region

struct	fw_flr_ack

struct	fw_flr_mb

struct	eee_remote_vals

struct	dcbx_ets_feature

struct	dcbx_pfc_feature

struct	dcbx_app_priority_entry

struct	dcbx_app_priority_feature

struct	dcbx_features

struct	lldp_params

struct	lldp_dcbx_stat

struct	lldp_admin_mib

struct	lldp_remote_mib

struct	lldp_local_mib

struct	shmem_lfa

struct	ncsi_oem_fcoe_features

struct	ncsi_oem_data

struct	shmem2_region

struct	emac_stats

struct	bmac1_stats

struct	bmac2_stats

struct	mstat_stats

struct	mac_stats

struct	mac_stx

struct	host_port_stats

struct	host_func_stats

struct	afex_stats

struct	atten_sp_status_block

struct	cstorm_eth_ag_context

struct	dmae_command

struct	doorbell_hdr

struct	eth_tx_doorbell

struct	hc_status_block_e1x

struct	host_hc_status_block_e1x

struct	hc_status_block_e2

struct	host_hc_status_block_e2

struct	hc_sp_status_block

struct	host_sp_status_block

struct	igu_ack_register

struct	igu_backward_compatible

struct	igu_regular

union	igu_consprod_reg

struct	igu_ctrl_reg

struct	parsing_flags

struct	sdm_op_gen

struct	timers_block_context

struct	tstorm_eth_ag_context

struct	ustorm_eth_ag_context

struct	xstorm_eth_ag_context

struct	doorbell

struct	doorbell_set_prod

struct	regpair

struct	client_init_general_data

struct	client_init_rx_data

struct	client_init_tx_data

struct	client_init_ramrod_data

struct	client_update_ramrod_data

struct	cstorm_eth_st_context

struct	double_regpair

struct	eth_classify_cmd_header

struct	eth_classify_header

struct	eth_classify_mac_cmd

struct	eth_classify_pair_cmd

struct	eth_classify_vlan_cmd

union	eth_classify_rule_cmd

struct	eth_classify_rules_ramrod_data

struct	eth_common_ramrod_data

struct	ustorm_eth_st_context

struct	tstorm_eth_st_context

struct	xstorm_eth_st_context

struct	eth_context

union	eth_sgl_or_raw_data

struct	eth_end_agg_rx_cqe

struct	eth_fast_path_rx_cqe

struct	eth_filter_rules_cmd

struct	eth_filter_rules_ramrod_data

struct	eth_general_rules_ramrod_data

struct	eth_halt_ramrod_data

struct	eth_multicast_rules_cmd

struct	eth_multicast_rules_ramrod_data

struct	ramrod_data

union	eth_ramrod_data

struct	eth_rss_update_ramrod_data

struct	eth_rx_bd

struct	common_ramrod_eth_rx_cqe

struct	eth_rx_cqe_next_page

union	eth_rx_cqe

struct	eth_rx_sge

struct	spe_hdr

union	eth_specific_data

struct	eth_spe

struct	eth_tx_bd

struct	eth_tx_bd_flags

struct	eth_tx_start_bd

struct	eth_tx_parse_bd_e1x

struct	eth_tx_parse_bd_e2

struct	eth_tx_next_bd

union	eth_tx_bd_types

struct	eth_tx_bds_array

struct	mac_configuration_hdr

struct	mac_configuration_entry

struct	mac_configuration_cmd

struct	tpa_update_ramrod_data

struct	tstorm_eth_approximate_match_multicast_filtering

struct	tstorm_eth_function_common_config

struct	tstorm_eth_mac_filter_config

struct	tx_queue_init_ramrod_data

struct	ustorm_eth_rx_producers

struct	fcoe_rx_stat_params_section0

struct	fcoe_rx_stat_params_section1

struct	fcoe_rx_stat_params_section2

struct	fcoe_tx_stat_params

struct	fcoe_statistics_params

struct	afex_vif_list_ramrod_data

struct	cfc_del_event_data

struct	cmng_flags_per_port

struct	rate_shaping_vars_per_port

struct	fairness_vars_per_port

struct	safc_struct_per_port

struct	cmng_struct_per_port

struct	rate_shaping_counter

struct	rate_shaping_vars_per_vn

struct	fairness_vars_per_vn

struct	cmng_vnic

struct	cmng_init

struct	cmng_init_input

struct	hc_dynamic_drv_counter

struct	cstorm_queue_zone_data

struct	vf_pf_channel_zone_data

struct	non_trigger_vf_zone

struct	vf_pf_channel_zone_trigger

struct	trigger_vf_zone

struct	cstorm_vf_zone_data

struct	dynamic_hc_sm_config

struct	dynamic_hc_config

struct	e2_integ_data

struct	eth_event_data

struct	vf_pf_event_data

struct	vf_flr_event_data

struct	malicious_vf_event_data

struct	vif_list_event_data

struct	event_data

struct	event_ring_data

struct	event_ring_msg

struct	event_ring_next

union	event_ring_elem

struct	priority_cos

struct	flow_control_configuration

struct	function_start_data

struct	function_update_data

struct	fw_version

struct	hc_dynamic_sb_drv_counters

struct	hc_index_data

struct	hc_status_block_sm

struct	pci_entity

struct	hc_sb_data

struct	hc_sp_status_block_data

struct	hc_status_block_data_e1x

struct	hc_status_block_data_e2

struct	tstorm_per_pf_stats

struct	per_pf_stats

struct	tstorm_per_port_stats

struct	per_port_stats

struct	tstorm_per_queue_stats

struct	ustorm_per_queue_stats

struct	xstorm_per_queue_stats

struct	per_queue_stats

struct	pram_fw_version

union	protocol_common_specific_data

struct	protocol_common_spe

struct	slow_path_element

struct	stats_counter

struct	stats_query_entry

struct	stats_query_cmd_group

struct	stats_query_header

struct	tstorm_queue_zone_data

struct	tstorm_vf_zone_data

struct	ustorm_queue_zone_data

struct	ustorm_vf_zone_data

struct	vf_pf_channel_data

struct	xstorm_queue_zone_data

struct	xstorm_vf_zone_data

Macros
#define	FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e

#define	BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF

#define	BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0

#define	BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000

#define	BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16

#define	BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF

#define	BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0

#define	BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000

#define	BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16

#define	PIN_CFG_NA 0x00000000

#define	PIN_CFG_GPIO0_P0 0x00000001

#define	PIN_CFG_GPIO1_P0 0x00000002

#define	PIN_CFG_GPIO2_P0 0x00000003

#define	PIN_CFG_GPIO3_P0 0x00000004

#define	PIN_CFG_GPIO0_P1 0x00000005

#define	PIN_CFG_GPIO1_P1 0x00000006

#define	PIN_CFG_GPIO2_P1 0x00000007

#define	PIN_CFG_GPIO3_P1 0x00000008

#define	PIN_CFG_EPIO0 0x00000009

#define	PIN_CFG_EPIO1 0x0000000a

#define	PIN_CFG_EPIO2 0x0000000b

#define	PIN_CFG_EPIO3 0x0000000c

#define	PIN_CFG_EPIO4 0x0000000d

#define	PIN_CFG_EPIO5 0x0000000e

#define	PIN_CFG_EPIO6 0x0000000f

#define	PIN_CFG_EPIO7 0x00000010

#define	PIN_CFG_EPIO8 0x00000011

#define	PIN_CFG_EPIO9 0x00000012

#define	PIN_CFG_EPIO10 0x00000013

#define	PIN_CFG_EPIO11 0x00000014

#define	PIN_CFG_EPIO12 0x00000015

#define	PIN_CFG_EPIO13 0x00000016

#define	PIN_CFG_EPIO14 0x00000017

#define	PIN_CFG_EPIO15 0x00000018

#define	PIN_CFG_EPIO16 0x00000019

#define	PIN_CFG_EPIO17 0x0000001a

#define	PIN_CFG_EPIO18 0x0000001b

#define	PIN_CFG_EPIO19 0x0000001c

#define	PIN_CFG_EPIO20 0x0000001d

#define	PIN_CFG_EPIO21 0x0000001e

#define	PIN_CFG_EPIO22 0x0000001f

#define	PIN_CFG_EPIO23 0x00000020

#define	PIN_CFG_EPIO24 0x00000021

#define	PIN_CFG_EPIO25 0x00000022

#define	PIN_CFG_EPIO26 0x00000023

#define	PIN_CFG_EPIO27 0x00000024

#define	PIN_CFG_EPIO28 0x00000025

#define	PIN_CFG_EPIO29 0x00000026

#define	PIN_CFG_EPIO30 0x00000027

#define	PIN_CFG_EPIO31 0x00000028

#define	EPIO_CFG_NA 0x00000000

#define	EPIO_CFG_EPIO0 0x00000001

#define	EPIO_CFG_EPIO1 0x00000002

#define	EPIO_CFG_EPIO2 0x00000003

#define	EPIO_CFG_EPIO3 0x00000004

#define	EPIO_CFG_EPIO4 0x00000005

#define	EPIO_CFG_EPIO5 0x00000006

#define	EPIO_CFG_EPIO6 0x00000007

#define	EPIO_CFG_EPIO7 0x00000008

#define	EPIO_CFG_EPIO8 0x00000009

#define	EPIO_CFG_EPIO9 0x0000000a

#define	EPIO_CFG_EPIO10 0x0000000b

#define	EPIO_CFG_EPIO11 0x0000000c

#define	EPIO_CFG_EPIO12 0x0000000d

#define	EPIO_CFG_EPIO13 0x0000000e

#define	EPIO_CFG_EPIO14 0x0000000f

#define	EPIO_CFG_EPIO15 0x00000010

#define	EPIO_CFG_EPIO16 0x00000011

#define	EPIO_CFG_EPIO17 0x00000012

#define	EPIO_CFG_EPIO18 0x00000013

#define	EPIO_CFG_EPIO19 0x00000014

#define	EPIO_CFG_EPIO20 0x00000015

#define	EPIO_CFG_EPIO21 0x00000016

#define	EPIO_CFG_EPIO22 0x00000017

#define	EPIO_CFG_EPIO23 0x00000018

#define	EPIO_CFG_EPIO24 0x00000019

#define	EPIO_CFG_EPIO25 0x0000001a

#define	EPIO_CFG_EPIO26 0x0000001b

#define	EPIO_CFG_EPIO27 0x0000001c

#define	EPIO_CFG_EPIO28 0x0000001d

#define	EPIO_CFG_EPIO29 0x0000001e

#define	EPIO_CFG_EPIO30 0x0000001f

#define	EPIO_CFG_EPIO31 0x00000020

#define	SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001

#define	SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0

#define	SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000

#define	SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001

#define	SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002

#define	SHARED_HW_CFG_PORT_SWAP 0x00000004

#define	SHARED_HW_CFG_BEACON_WOL_EN 0x00000008

#define	SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000

#define	SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010

#define	SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700

#define	SHARED_HW_CFG_MFW_SELECT_SHIFT 8

#define	SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000

#define	SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100

#define	SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200

#define	SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300

#define	SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400

#define	SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500

#define	SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600

#define	SHARED_HW_CFG_LED_MODE_MASK 0x000f0000

#define	SHARED_HW_CFG_LED_MODE_SHIFT 16

#define	SHARED_HW_CFG_LED_MAC1 0x00000000

#define	SHARED_HW_CFG_LED_PHY1 0x00010000

#define	SHARED_HW_CFG_LED_PHY2 0x00020000

#define	SHARED_HW_CFG_LED_PHY3 0x00030000

#define	SHARED_HW_CFG_LED_MAC2 0x00040000

#define	SHARED_HW_CFG_LED_PHY4 0x00050000

#define	SHARED_HW_CFG_LED_PHY5 0x00060000

#define	SHARED_HW_CFG_LED_PHY6 0x00070000

#define	SHARED_HW_CFG_LED_MAC3 0x00080000

#define	SHARED_HW_CFG_LED_PHY7 0x00090000

#define	SHARED_HW_CFG_LED_PHY9 0x000a0000

#define	SHARED_HW_CFG_LED_PHY11 0x000b0000

#define	SHARED_HW_CFG_LED_MAC4 0x000c0000

#define	SHARED_HW_CFG_LED_PHY8 0x000d0000

#define	SHARED_HW_CFG_LED_EXTPHY1 0x000e0000

#define	SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000

#define	SHARED_HW_CFG_AN_ENABLE_SHIFT 24

#define	SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000

#define	SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000

#define	SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000

#define	SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000

#define	SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000

#define	SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000

#define	SHARED_HW_CFG_SRIOV_MASK 0x40000000

#define	SHARED_HW_CFG_SRIOV_DISABLED 0x00000000

#define	SHARED_HW_CFG_SRIOV_ENABLED 0x40000000

#define	SHARED_HW_CFG_ATC_MASK 0x80000000

#define	SHARED_HW_CFG_ATC_DISABLED 0x00000000

#define	SHARED_HW_CFG_ATC_ENABLED 0x80000000

#define	SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff

#define	SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0

#define	SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100

#define	SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000

#define	SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00

#define	SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9

#define	SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000

#define	SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000

#define	SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000

#define	SHARED_HW_CFG_HIDE_PORT1 0x00002000

#define	SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000

#define	SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000

#define	SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000

#define	SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000

#define	SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000

#define	SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000

#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000

#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16

#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000

#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000

#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000

#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000

#define	SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000

#define	SHARED_HW_CFG_FAN_FAILURE_SHIFT 19

#define	SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000

#define	SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000

#define	SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000

#define	SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000

#define	SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21

#define	SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000

#define	SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000

#define	SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000

#define	SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000

#define	SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000

#define	SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000

#define	SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000

#define	SHARED_HW_CFG_PORT_MODE_MASK 0x01000000

#define	SHARED_HW_CFG_PORT_MODE_2 0x00000000

#define	SHARED_HW_CFG_PORT_MODE_4 0x01000000

#define	SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000

#define	SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000

#define	SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000

#define	SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000

#define	SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000

#define	SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16

#define	SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000

#define	SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000

#define	SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000

#define	SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000

#define	SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000

#define	SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24

#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003

#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0

#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000

#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001

#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000

#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002

#define	SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00

#define	SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8

#define	SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000

#define	SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16

#define	SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000

#define	SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000

#define	SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F

#define	SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0

#define	SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0

#define	SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6

#define	SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000

#define	SHARED_HW_CFG_BOARD_REV_SHIFT 16

#define	SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000

#define	SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24

#define	SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000

#define	SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28

#define	SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF

#define	SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0

#define	SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b

#define	SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4

#define	SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b

#define	SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4

#define	SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF

#define	SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0

#define	SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00

#define	SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8

#define	SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000

#define	SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000

#define	SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000

#define	SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000

#define	SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000

#define	SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000

#define	SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000

#define	SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000

#define	SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000

#define	SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24

#define	SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000

#define	SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000

#define	SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000

#define	SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000

#define	SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000

#define	SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000

#define	PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000

#define	PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff

#define	PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000

#define	PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff

#define	PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff

#define	PORT_HW_CFG_POWER_DIS_D0_SHIFT 0

#define	PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00

#define	PORT_HW_CFG_POWER_DIS_D1_SHIFT 8

#define	PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000

#define	PORT_HW_CFG_POWER_DIS_D2_SHIFT 16

#define	PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000

#define	PORT_HW_CFG_POWER_DIS_D3_SHIFT 24

#define	PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff

#define	PORT_HW_CFG_POWER_CONS_D0_SHIFT 0

#define	PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00

#define	PORT_HW_CFG_POWER_CONS_D1_SHIFT 8

#define	PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000

#define	PORT_HW_CFG_POWER_CONS_D2_SHIFT 16

#define	PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000

#define	PORT_HW_CFG_POWER_CONS_D3_SHIFT 24

#define	PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff

#define	PORT_HW_CFG_UPPERMAC_SHIFT 0

#define	PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff

#define	PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0

#define	PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000

#define	PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16

#define	PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F

#define	PORT_HW_CFG_PF_NUM_VF_SHIFT 0

#define	PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00

#define	PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8

#define	PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000

#define	PORT_HW_CFG_FLR_ENABLED 0x00010000

#define	PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F

#define	PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0

#define	PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000

#define	PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16

#define	PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF

#define	PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0

#define	PORT_HW_CFG_TX_LASER_MASK 0x000000FF

#define	PORT_HW_CFG_TX_LASER_SHIFT 0

#define	PORT_HW_CFG_TX_LASER_MDIO 0x00000000

#define	PORT_HW_CFG_TX_LASER_GPIO0 0x00000001

#define	PORT_HW_CFG_TX_LASER_GPIO1 0x00000002

#define	PORT_HW_CFG_TX_LASER_GPIO2 0x00000003

#define	PORT_HW_CFG_TX_LASER_GPIO3 0x00000004

#define	PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00

#define	PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8

#define	PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000

#define	PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100

#define	PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200

#define	PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300

#define	PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400

#define	PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF

#define	PORT_HW_CFG_E3_TX_LASER_SHIFT 0

#define	PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00

#define	PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8

#define	PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000

#define	PORT_HW_CFG_E3_MOD_ABS_SHIFT 16

#define	PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000

#define	PORT_HW_CFG_E3_PWR_DIS_SHIFT 24

#define	PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF

#define	PORT_HW_CFG_E3_TX_FAULT_SHIFT 0

#define	PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00

#define	PORT_HW_CFG_E3_PHY_RESET_SHIFT 8

#define	PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000

#define	PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16

#define	PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000

#define	PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000

#define	PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF

#define	PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0

#define	PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF

#define	PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0

#define	PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00

#define	PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8

#define	PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000

#define	PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16

#define	PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff

#define	PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0

#define	PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF

#define	PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0

#define	PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003

#define	PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0

#define	PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000

#define	PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001

#define	PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002

#define	PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003

#define	PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C

#define	PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2

#define	PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000

#define	PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004

#define	PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008

#define	PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c

#define	PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030

#define	PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4

#define	PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000

#define	PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010

#define	PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020

#define	PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030

#define	PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0

#define	PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6

#define	PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000

#define	PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040

#define	PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080

#define	PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0

#define	PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00

#define	PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8

#define	PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000

#define	PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100

#define	PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200

#define	PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300

#define	PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400

#define	PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500

#define	PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600

#define	PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700

#define	PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800

#define	PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000

#define	PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000

#define	PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000

#define	PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20

#define	PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000

#define	PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000

#define	PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000

#define	PORT_HW_CFG_ENABLE_CMS_SHIFT 21

#define	PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000

#define	PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000

#define	PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000

#define	PORT_HW_CFG_NET_SERDES_IF_SHIFT 24

#define	PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000

#define	PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000

#define	PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000

#define	PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000

#define	PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000

#define	PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000

#define	PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000

#define	PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007

#define	PORT_HW_CFG_PHY_SELECTION_SHIFT 0

#define	PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000

#define	PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001

#define	PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002

#define	PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003

#define	PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004

#define	PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008

#define	PORT_HW_CFG_PHY_SWAPPED_SHIFT 3

#define	PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000

#define	PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008

#define	PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF

#define	PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00

#define	PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00

#define	PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff

#define	PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0

#define	PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b

#define	PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4

#define	PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8

#define	PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4

#define	PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff

#define	PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0

#define	PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00

#define	PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8

#define	PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000

#define	PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14

#define	PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000

#define	PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000

#define	PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000

#define	PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff

#define	PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00

#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00

#define	PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000

#define	PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16

#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000

#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24

#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000

#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000

#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000

#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080

#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000

#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000

#define	SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001

#define	SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK 0x00000002

#define	SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000

#define	SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002

#define	SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008

#define	SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000

#define	SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008

#define	SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030

#define	SHARED_FEAT_CFG_NCSI_ID_SHIFT 4

#define	SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700

#define	SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8

#define	SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000

#define	SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100

#define	SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200

#define	SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300

#define	SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400

#define	SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000

#define	SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16

#define	SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000

#define	SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24

#define	PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f

#define	PORT_FEATURE_BAR1_SIZE_SHIFT 0

#define	PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000

#define	PORT_FEATURE_BAR1_SIZE_64K 0x00000001

#define	PORT_FEATURE_BAR1_SIZE_128K 0x00000002

#define	PORT_FEATURE_BAR1_SIZE_256K 0x00000003

#define	PORT_FEATURE_BAR1_SIZE_512K 0x00000004

#define	PORT_FEATURE_BAR1_SIZE_1M 0x00000005

#define	PORT_FEATURE_BAR1_SIZE_2M 0x00000006

#define	PORT_FEATURE_BAR1_SIZE_4M 0x00000007

#define	PORT_FEATURE_BAR1_SIZE_8M 0x00000008

#define	PORT_FEATURE_BAR1_SIZE_16M 0x00000009

#define	PORT_FEATURE_BAR1_SIZE_32M 0x0000000a

#define	PORT_FEATURE_BAR1_SIZE_64M 0x0000000b

#define	PORT_FEATURE_BAR1_SIZE_128M 0x0000000c

#define	PORT_FEATURE_BAR1_SIZE_256M 0x0000000d

#define	PORT_FEATURE_BAR1_SIZE_512M 0x0000000e

#define	PORT_FEATURE_BAR1_SIZE_1G 0x0000000f

#define	PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0

#define	PORT_FEATURE_BAR2_SIZE_SHIFT 4

#define	PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000

#define	PORT_FEATURE_BAR2_SIZE_64K 0x00000010

#define	PORT_FEATURE_BAR2_SIZE_128K 0x00000020

#define	PORT_FEATURE_BAR2_SIZE_256K 0x00000030

#define	PORT_FEATURE_BAR2_SIZE_512K 0x00000040

#define	PORT_FEATURE_BAR2_SIZE_1M 0x00000050

#define	PORT_FEATURE_BAR2_SIZE_2M 0x00000060

#define	PORT_FEATURE_BAR2_SIZE_4M 0x00000070

#define	PORT_FEATURE_BAR2_SIZE_8M 0x00000080

#define	PORT_FEATURE_BAR2_SIZE_16M 0x00000090

#define	PORT_FEATURE_BAR2_SIZE_32M 0x000000a0

#define	PORT_FEATURE_BAR2_SIZE_64M 0x000000b0

#define	PORT_FEATURE_BAR2_SIZE_128M 0x000000c0

#define	PORT_FEATURE_BAR2_SIZE_256M 0x000000d0

#define	PORT_FEATURE_BAR2_SIZE_512M 0x000000e0

#define	PORT_FEATURE_BAR2_SIZE_1G 0x000000f0

#define	PORT_FEAT_CFG_DCBX_MASK 0x00000100

#define	PORT_FEAT_CFG_DCBX_DISABLED 0x00000000

#define	PORT_FEAT_CFG_DCBX_ENABLED 0x00000100

#define	PORT_FEATURE_EN_SIZE_MASK 0x0f000000

#define	PORT_FEATURE_EN_SIZE_SHIFT 24

#define	PORT_FEATURE_WOL_ENABLED 0x01000000

#define	PORT_FEATURE_MBA_ENABLED 0x02000000

#define	PORT_FEATURE_MFW_ENABLED 0x04000000

#define	PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000

#define	PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000

#define	PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000

#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000

#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29

#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000

#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000

#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000

#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000

#define	PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003

#define	PORT_FEATURE_WOL_DEFAULT_SHIFT 0

#define	PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000

#define	PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001

#define	PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002

#define	PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003

#define	PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004

#define	PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008

#define	PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010

#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007

#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0

#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000

#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001

#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002

#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003

#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004

#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007

#define	PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038

#define	PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3

#define	PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100

#define	PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200

#define	PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400

#define	PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800

#define	PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000

#define	PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000

#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000

#define	PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000

#define	PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20

#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000

#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24

#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000

#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000

#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000

#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000

#define	PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000

#define	PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26

#define	PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000

#define	PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000

#define	PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000

#define	PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000

#define	PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000

#define	PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000

#define	PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000

#define	PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000

#define	PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000

#define	PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001

#define	PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000

#define	PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001

#define	PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff

#define	PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0

#define	PORT_FEATURE_MBA_VLAN_EN 0x00010000

#define	PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001

#define	PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002

#define	PORT_FEATURE_RESOURCE_CFG_L2 0x00000004

#define	PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008

#define	PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010

#define	PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe

#define	PORT_FEATURE_SMBUS_ADDR_SHIFT 1

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e

#define	PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f

#define	PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000

#define	PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24

#define	PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000

#define	PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000

#define	PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000

#define	PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000

#define	PORT_FEATURE_LINK_SPEED_MASK 0x000f0000

#define	PORT_FEATURE_LINK_SPEED_SHIFT 16

#define	PORT_FEATURE_LINK_SPEED_AUTO 0x00000000

#define	PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000

#define	PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000

#define	PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000

#define	PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000

#define	PORT_FEATURE_LINK_SPEED_1G 0x00050000

#define	PORT_FEATURE_LINK_SPEED_2_5G 0x00060000

#define	PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000

#define	PORT_FEATURE_LINK_SPEED_20G 0x00080000

#define	PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700

#define	PORT_FEATURE_FLOW_CONTROL_SHIFT 8

#define	PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000

#define	PORT_FEATURE_FLOW_CONTROL_TX 0x00000100

#define	PORT_FEATURE_FLOW_CONTROL_RX 0x00000200

#define	PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300

#define	PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400

#define	PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF

#define	PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0

#define	PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000

#define	PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001

#define	PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002

#define	PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003

#define	FUNC_0 0

#define	FUNC_1 1

#define	FUNC_2 2

#define	FUNC_3 3

#define	FUNC_4 4

#define	FUNC_5 5

#define	FUNC_6 6

#define	FUNC_7 7

#define	E1_FUNC_MAX 2

#define	E1H_FUNC_MAX 8

#define	E2_FUNC_MAX 4 /* per path */

#define	VN_0 0

#define	VN_1 1

#define	VN_2 2

#define	VN_3 3

#define	E1VN_MAX 1

#define	E1HVN_MAX 4

#define	E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */

#define	DRV_PULSE_PERIOD_MS 250

#define	FW_ACK_TIME_OUT_MS 5000

#define	FW_ACK_POLL_TIME_MS 1

#define	FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)

#define	MFW_TRACE_SIGNATURE 0x54524342

#define	LINK_STATUS_NONE (0<<0)

#define	LINK_STATUS_LINK_FLAG_MASK 0x00000001

#define	LINK_STATUS_LINK_UP 0x00000001

#define	LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E

#define	LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)

#define	LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)

#define	LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020

#define	LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020

#define	LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040

#define	LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080

#define	LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080

#define	LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200

#define	LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400

#define	LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800

#define	LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000

#define	LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000

#define	LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000

#define	LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000

#define	LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000

#define	LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000

#define	LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000

#define	LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000

#define	LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000

#define	LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)

#define	LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)

#define	LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)

#define	LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)

#define	LINK_STATUS_SERDES_LINK 0x00100000

#define	LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000

#define	LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000

#define	LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000

#define	LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000

#define	LINK_STATUS_PFC_ENABLED 0x20000000

#define	LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000

#define	LINK_STATUS_SFP_TX_FAULT 0x80000000

#define	DRV_MSG_CODE_MASK 0xffff0000

#define	DRV_MSG_CODE_LOAD_REQ 0x10000000

#define	DRV_MSG_CODE_LOAD_DONE 0x11000000

#define	DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000

#define	DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000

#define	DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000

#define	DRV_MSG_CODE_UNLOAD_DONE 0x21000000

#define	DRV_MSG_CODE_DCC_OK 0x30000000

#define	DRV_MSG_CODE_DCC_FAILURE 0x31000000

#define	DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000

#define	DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000

#define	DRV_MSG_CODE_VALIDATE_KEY 0x70000000

#define	DRV_MSG_CODE_GET_CURR_KEY 0x80000000

#define	DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000

#define	DRV_MSG_CODE_GET_MANUF_KEY 0x82000000

#define	DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000

#define	DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000

#define	REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006

#define	DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000

#define	REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234

#define	DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000

#define	REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002

#define	REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014

#define	REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201

#define	REQ_BC_VER_4_FCOE_FEATURES 0x00070209

#define	DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000

#define	DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000

#define	REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401

#define	DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000

#define	DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000

#define	DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000

#define	DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000

#define	DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000

#define	DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000

#define	DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000

#define	DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000

#define	DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000

#define	DRV_MSG_CODE_SET_MF_BW 0xe0000000

#define	REQ_BC_VER_4_SET_MF_BW 0x00060202

#define	DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000

#define	DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000

#define	DRV_MSG_CODE_INITIATE_FLR 0x02000000

#define	REQ_BC_VER_4_INITIATE_FLR 0x00070213

#define	BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000

#define	BIOS_MSG_CODE_LIC_RESPONSE 0xff020000

#define	BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000

#define	BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000

#define	DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff

#define	DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000

#define	DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000

#define	DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002

#define	DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a

#define	FW_MSG_CODE_MASK 0xffff0000

#define	FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000

#define	FW_MSG_CODE_DRV_LOAD_PORT 0x10110000

#define	FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000

#define	REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000

#define	FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000

#define	FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000

#define	FW_MSG_CODE_DRV_LOAD_DONE 0x11100000

#define	FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000

#define	FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000

#define	FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000

#define	FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000

#define	FW_MSG_CODE_DCC_DONE 0x30100000

#define	FW_MSG_CODE_LLDP_DONE 0x40100000

#define	FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000

#define	FW_MSG_CODE_DIAG_REFUSE 0x50200000

#define	FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000

#define	FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000

#define	FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000

#define	FW_MSG_CODE_GET_KEY_DONE 0x80100000

#define	FW_MSG_CODE_NO_KEY 0x80f00000

#define	FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000

#define	FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000

#define	FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000

#define	FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000

#define	FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000

#define	FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000

#define	FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000

#define	FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000

#define	FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000

#define	FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000

#define	FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000

#define	FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000

#define	FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000

#define	FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000

#define	FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000

#define	FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000

#define	FW_MSG_CODE_DRV_INFO_ACK 0xd8100000

#define	FW_MSG_CODE_DRV_INFO_NACK 0xd9100000

#define	FW_MSG_CODE_EEE_RESULS_ACK 0xda100000

#define	FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000

#define	FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000

#define	FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000

#define	FW_MSG_CODE_LIC_CHALLENGE 0xff010000

#define	FW_MSG_CODE_LIC_RESPONSE 0xff020000

#define	FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000

#define	FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000

#define	FW_MSG_SEQ_NUMBER_MASK 0x0000ffff

#define	DRV_PULSE_SEQ_MASK 0x00007fff

#define	DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000

#define	DRV_PULSE_ALWAYS_ALIVE 0x00008000

#define	MCP_PULSE_SEQ_MASK 0x00007fff

#define	MCP_PULSE_ALWAYS_ALIVE 0x00008000

#define	MCP_EVENT_MASK 0xffff0000

#define	MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000

#define	DRV_STATUS_PMF 0x00000001

#define	DRV_STATUS_VF_DISABLED 0x00000002

#define	DRV_STATUS_SET_MF_BW 0x00000004

#define	DRV_STATUS_LINK_EVENT 0x00000008

#define	DRV_STATUS_DCC_EVENT_MASK 0x0000ff00

#define	DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100

#define	DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200

#define	DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400

#define	DRV_STATUS_DCC_RESERVED1 0x00000800

#define	DRV_STATUS_DCC_SET_PROTOCOL 0x00001000

#define	DRV_STATUS_DCC_SET_PRIORITY 0x00002000

#define	DRV_STATUS_DCBX_EVENT_MASK 0x000f0000

#define	DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000

#define	DRV_STATUS_AFEX_EVENT_MASK 0x03f00000

#define	DRV_STATUS_AFEX_LISTGET_REQ 0x00100000

#define	DRV_STATUS_AFEX_LISTSET_REQ 0x00200000

#define	DRV_STATUS_AFEX_STATSGET_REQ 0x00400000

#define	DRV_STATUS_AFEX_VIFSET_REQ 0x00800000

#define	DRV_STATUS_DRV_INFO_REQ 0x04000000

#define	DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000

#define	VIRT_MAC_SIGN_MASK 0xffff0000

#define	VIRT_MAC_SIGNATURE 0x564d0000

#define	MGMTFW_STATE_WORD_SIZE 110

#define	SHARED_MF_CLP_SET_DEFAULT 0x00000000

#define	SHARED_MF_CLP_EXIT 0x00000001

#define	SHARED_MF_CLP_EXIT_DONE 0x00010000

#define	PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff

#define	PORT_MF_CFG_E1HOV_TAG_SHIFT 0

#define	PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK

#define	FUNC_MF_CFG_FUNC_HIDE 0x00000001

#define	FUNC_MF_CFG_PROTOCOL_MASK 0x00000006

#define	FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000

#define	FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002

#define	FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004

#define	FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006

#define	FUNC_MF_CFG_PROTOCOL_DEFAULT FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA

#define	FUNC_MF_CFG_FUNC_DISABLED 0x00000008

#define	FUNC_MF_CFG_FUNC_DELETED 0x00000010

#define	FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300

#define	FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8

#define	FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000

#define	FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000

#define	FUNC_MF_CFG_MIN_BW_SHIFT 16

#define	FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000

#define	FUNC_MF_CFG_MAX_BW_MASK 0xff000000

#define	FUNC_MF_CFG_MAX_BW_SHIFT 24

#define	FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000

#define	FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff

#define	FUNC_MF_CFG_UPPERMAC_SHIFT 0

#define	FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK

#define	FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff

#define	FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff

#define	FUNC_MF_CFG_E1HOV_TAG_SHIFT 0

#define	FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK

#define	FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000

#define	FUNC_MF_CFG_AFEX_VLAN_SHIFT 16

#define	FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff

#define	FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0

#define	FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00

#define	FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8

#define	FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100

#define	FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000

#define	FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16

#define	MACP_FUNC_CFG_FLAGS_MASK 0x000000FF

#define	MACP_FUNC_CFG_FLAGS_SHIFT 0

#define	MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001

#define	MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002

#define	MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004

#define	MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008

#define	MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)

#define	MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)

#define	MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)

#define	MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)

#define	MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)

#define	MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)

#define	SHR_MEM_FORMAT_REV_MASK 0xff000000

#define	SHR_MEM_FORMAT_REV_ID ('A'<<24)

#define	SHR_MEM_VALIDITY_PCI_CFG 0x00100000

#define	SHR_MEM_VALIDITY_MB 0x00200000

#define	SHR_MEM_VALIDITY_DEV_INFO 0x00400000

#define	SHR_MEM_VALIDITY_RESERVED 0x00000007

#define	SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038

#define	SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008

#define	SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010

#define	SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020

#define	SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000

#define	SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0

#define	SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040

#define	SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080

#define	SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0

#define	SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0

#define	SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)

#define	SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))

#define	SHMEM_ARRAY_BITPOS(i, eb, fb)

#define	SHMEM_ARRAY_GET(a, i, eb, fb)

#define	SHMEM_ARRAY_SET(a, i, eb, fb, val)

#define	DCBX_MAX_NUM_PRI_PG_ENTRIES 8

#define	DCBX_PRI_PG_BITWIDTH 4

#define	DCBX_PRI_PG_FBITS 8

#define	DCBX_PRI_PG_GET(a, i) SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)

#define	DCBX_PRI_PG_SET(a, i, val) SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)

#define	DCBX_MAX_NUM_PG_BW_ENTRIES 8

#define	DCBX_BW_PG_BITWIDTH 8

#define	DCBX_PG_BW_GET(a, i) SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)

#define	DCBX_PG_BW_SET(a, i, val) SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)

#define	DCBX_STRICT_PRI_PG 15

#define	DCBX_MAX_APP_PROTOCOL 16

#define	FCOE_APP_IDX 0

#define	ISCSI_APP_IDX 1

#define	PREDEFINED_APP_IDX_MAX 2

#define	REM_CHASSIS_ID_STAT_LEN 4

#define	REM_PORT_ID_STAT_LEN 4

#define	LOCAL_CHASSIS_ID_STAT_LEN 2

#define	LOCAL_PORT_ID_STAT_LEN 2

#define	DCBX_ETS_CONFIG_TX_ENABLED 0x00000001

#define	DCBX_PFC_CONFIG_TX_ENABLED 0x00000002

#define	DCBX_APP_CONFIG_TX_ENABLED 0x00000004

#define	DCBX_ETS_RECO_TX_ENABLED 0x00000008

#define	DCBX_ETS_RECO_VALID 0x00000010

#define	DCBX_ETS_WILLING 0x00000020

#define	DCBX_PFC_WILLING 0x00000040

#define	DCBX_APP_WILLING 0x00000080

#define	DCBX_VERSION_CEE 0x00000100

#define	DCBX_VERSION_IEEE 0x00000200

#define	DCBX_DCBX_ENABLED 0x00000400

#define	DCBX_CEE_VERSION_MASK 0x0000f000

#define	DCBX_CEE_VERSION_SHIFT 12

#define	DCBX_CEE_MAX_VERSION_MASK 0x000f0000

#define	DCBX_CEE_MAX_VERSION_SHIFT 16

#define	DCBX_ETS_TLV_RX 0x00000001

#define	DCBX_PFC_TLV_RX 0x00000002

#define	DCBX_APP_TLV_RX 0x00000004

#define	DCBX_ETS_RX_ERROR 0x00000010

#define	DCBX_PFC_RX_ERROR 0x00000020

#define	DCBX_APP_RX_ERROR 0x00000040

#define	DCBX_ETS_REM_WILLING 0x00000100

#define	DCBX_PFC_REM_WILLING 0x00000200

#define	DCBX_APP_REM_WILLING 0x00000400

#define	DCBX_REMOTE_ETS_RECO_VALID 0x00001000

#define	DCBX_REMOTE_MIB_VALID 0x00002000

#define	DCBX_LOCAL_ETS_ERROR 0x00000001

#define	DCBX_LOCAL_PFC_ERROR 0x00000002

#define	DCBX_LOCAL_APP_ERROR 0x00000004

#define	DCBX_LOCAL_PFC_MISMATCH 0x00000010

#define	DCBX_LOCAL_APP_MISMATCH 0x00000020

#define	DCBX_REMOTE_MIB_ERROR 0x00000040

#define	DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080

#define	DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100

#define	DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200

#define	SHMEM_LINK_CONFIG_SIZE 2

#define	REQ_DUPLEX_PHY0_MASK 0x0000ffff

#define	REQ_DUPLEX_PHY0_SHIFT 0

#define	REQ_DUPLEX_PHY1_MASK 0xffff0000

#define	REQ_DUPLEX_PHY1_SHIFT 16

#define	REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff

#define	REQ_FLOW_CTRL_PHY0_SHIFT 0

#define	REQ_FLOW_CTRL_PHY1_MASK 0xffff0000

#define	REQ_FLOW_CTRL_PHY1_SHIFT 16

#define	REQ_LINE_SPD_PHY0_MASK 0x0000ffff

#define	REQ_LINE_SPD_PHY0_SHIFT 0

#define	REQ_LINE_SPD_PHY1_MASK 0xffff0000

#define	REQ_LINE_SPD_PHY1_SHIFT 16

#define	REQ_FC_AUTO_ADV_MASK 0x0000ffff

#define	REQ_FC_AUTO_ADV0_SHIFT 0

#define	NO_LFA_DUE_TO_DCC_MASK 0x00010000

#define	LFA_LINK_FLAP_REASON_OFFSET 0

#define	LFA_LINK_FLAP_REASON_MASK 0x000000ff

#define	LFA_LINK_DOWN 0x1

#define	LFA_LOOPBACK_ENABLED 0x2

#define	LFA_DUPLEX_MISMATCH 0x3

#define	LFA_MFW_IS_TOO_OLD 0x4

#define	LFA_LINK_SPEED_MISMATCH 0x5

#define	LFA_FLOW_CTRL_MISMATCH 0x6

#define	LFA_SPEED_CAP_MISMATCH 0x7

#define	LFA_DCC_LFA_DISABLED 0x8

#define	LFA_EEE_MISMATCH 0x9

#define	LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8

#define	LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00

#define	LINK_FLAP_COUNT_OFFSET 16

#define	LINK_FLAP_COUNT_MASK 0x00ff0000

#define	LFA_FLAGS_MASK 0xff000000

#define	SHMEM_LFA_DONT_CLEAR_STAT (1<<24)

#define	FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF

#define	FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0

#define	FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000

#define	FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16

#define	FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF

#define	FCOE_FEATURES2_EXCHANGES_OFFSET 0

#define	FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000

#define	FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16

#define	FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF

#define	FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0

#define	FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000

#define	FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16

#define	FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F

#define	FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0

#define	SHMEM_DCC_SUPPORT_NONE 0x00000000

#define	SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001

#define	SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004

#define	SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008

#define	SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040

#define	SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080

#define	SHMEM_MF_CFG_ADDR_NONE 0x00000000

#define	SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000

#define	SHMEM_DCBX_NEG_RES_NONE 0x00000000

#define	SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000

#define	SHMEM_LLDP_DCBX_STAT_NONE 0x00000000

#define	EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1

#define	EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2

#define	EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3

#define	SHMEM_AFEX_VERSION_MASK 0x100f

#define	SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001

#define	SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000

#define	DRV_FLAGS_DCB_CONFIGURED 0x1

#define	SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000

#define	DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001

#define	DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002

#define	DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004

#define	DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008

#define	DRV_INFO_CONTROL_VER_MASK 0x000000ff

#define	DRV_INFO_CONTROL_VER_SHIFT 0

#define	DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00

#define	DRV_INFO_CONTROL_OP_CODE_SHIFT 8

#define	SHMEM_EEE_TIMER_MASK 0x0000ffff

#define	SHMEM_EEE_SUPPORTED_MASK 0x000f0000

#define	SHMEM_EEE_SUPPORTED_SHIFT 16

#define	SHMEM_EEE_ADV_STATUS_MASK 0x00f00000

#define	SHMEM_EEE_100M_ADV (1<<0)

#define	SHMEM_EEE_1G_ADV (1<<1)

#define	SHMEM_EEE_10G_ADV (1<<2)

#define	SHMEM_EEE_ADV_STATUS_SHIFT 20

#define	SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000

#define	SHMEM_EEE_LP_ADV_STATUS_SHIFT 24

#define	SHMEM_EEE_REQUESTED_BIT 0x10000000

#define	SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000

#define	SHMEM_EEE_ACTIVE_BIT 0x40000000

#define	SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000

#define	MAC_STX_IDX_MAX 2

#define	VICSTATST_UIF_INDEX 2

#define	BCM_5710_FW_MAJOR_VERSION 7

#define	BCM_5710_FW_MINOR_VERSION 8

#define	BCM_5710_FW_REVISION_VERSION 2

#define	BCM_5710_FW_ENGINEERING_VERSION 0

#define	BCM_5710_FW_COMPILE_FLAGS 1

#define	DMAE_COMMAND_SRC (0x1<<0)

#define	DMAE_COMMAND_SRC_SHIFT 0

#define	DMAE_COMMAND_DST (0x3<<1)

#define	DMAE_COMMAND_DST_SHIFT 1

#define	DMAE_COMMAND_C_DST (0x1<<3)

#define	DMAE_COMMAND_C_DST_SHIFT 3

#define	DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)

#define	DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4

#define	DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)

#define	DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5

#define	DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)

#define	DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6

#define	DMAE_COMMAND_ENDIANITY (0x3<<9)

#define	DMAE_COMMAND_ENDIANITY_SHIFT 9

#define	DMAE_COMMAND_PORT (0x1<<11)

#define	DMAE_COMMAND_PORT_SHIFT 11

#define	DMAE_COMMAND_CRC_RESET (0x1<<12)

#define	DMAE_COMMAND_CRC_RESET_SHIFT 12

#define	DMAE_COMMAND_SRC_RESET (0x1<<13)

#define	DMAE_COMMAND_SRC_RESET_SHIFT 13

#define	DMAE_COMMAND_DST_RESET (0x1<<14)

#define	DMAE_COMMAND_DST_RESET_SHIFT 14

#define	DMAE_COMMAND_E1HVN (0x3<<15)

#define	DMAE_COMMAND_E1HVN_SHIFT 15

#define	DMAE_COMMAND_DST_VN (0x3<<17)

#define	DMAE_COMMAND_DST_VN_SHIFT 17

#define	DMAE_COMMAND_C_FUNC (0x1<<19)

#define	DMAE_COMMAND_C_FUNC_SHIFT 19

#define	DMAE_COMMAND_ERR_POLICY (0x3<<20)

#define	DMAE_COMMAND_ERR_POLICY_SHIFT 20

#define	DMAE_COMMAND_RESERVED0 (0x3FF<<22)

#define	DMAE_COMMAND_RESERVED0_SHIFT 22

#define	DOORBELL_HDR_RX (0x1<<0)

#define	DOORBELL_HDR_RX_SHIFT 0

#define	DOORBELL_HDR_DB_TYPE (0x1<<1)

#define	DOORBELL_HDR_DB_TYPE_SHIFT 1

#define	DOORBELL_HDR_DPM_SIZE (0x3<<2)

#define	DOORBELL_HDR_DPM_SIZE_SHIFT 2

#define	DOORBELL_HDR_CONN_TYPE (0xF<<4)

#define	DOORBELL_HDR_CONN_TYPE_SHIFT 4

#define	IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)

#define	IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0

#define	IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)

#define	IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16

#define	IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)

#define	IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21

#define	IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)

#define	IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24

#define	IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)

#define	IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25

#define	IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)

#define	IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27

#define	IGU_REGULAR_SB_INDEX (0xFFFFF<<0)

#define	IGU_REGULAR_SB_INDEX_SHIFT 0

#define	IGU_REGULAR_RESERVED0 (0x1<<20)

#define	IGU_REGULAR_RESERVED0_SHIFT 20

#define	IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)

#define	IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21

#define	IGU_REGULAR_BUPDATE (0x1<<24)

#define	IGU_REGULAR_BUPDATE_SHIFT 24

#define	IGU_REGULAR_ENABLE_INT (0x3<<25)

#define	IGU_REGULAR_ENABLE_INT_SHIFT 25

#define	IGU_REGULAR_RESERVED_1 (0x1<<27)

#define	IGU_REGULAR_RESERVED_1_SHIFT 27

#define	IGU_REGULAR_CLEANUP_TYPE (0x3<<28)

#define	IGU_REGULAR_CLEANUP_TYPE_SHIFT 28

#define	IGU_REGULAR_CLEANUP_SET (0x1<<30)

#define	IGU_REGULAR_CLEANUP_SET_SHIFT 30

#define	IGU_REGULAR_BCLEANUP (0x1<<31)

#define	IGU_REGULAR_BCLEANUP_SHIFT 31

#define	IGU_CTRL_REG_ADDRESS (0xFFF<<0)

#define	IGU_CTRL_REG_ADDRESS_SHIFT 0

#define	IGU_CTRL_REG_FID (0x7F<<12)

#define	IGU_CTRL_REG_FID_SHIFT 12

#define	IGU_CTRL_REG_RESERVED (0x1<<19)

#define	IGU_CTRL_REG_RESERVED_SHIFT 19

#define	IGU_CTRL_REG_TYPE (0x1<<20)

#define	IGU_CTRL_REG_TYPE_SHIFT 20

#define	IGU_CTRL_REG_UNUSED (0x7FF<<21)

#define	IGU_CTRL_REG_UNUSED_SHIFT 21

#define	PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)

#define	PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0

#define	PARSING_FLAGS_VLAN (0x1<<1)

#define	PARSING_FLAGS_VLAN_SHIFT 1

#define	PARSING_FLAGS_EXTRA_VLAN (0x1<<2)

#define	PARSING_FLAGS_EXTRA_VLAN_SHIFT 2

#define	PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)

#define	PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3

#define	PARSING_FLAGS_IP_OPTIONS (0x1<<5)

#define	PARSING_FLAGS_IP_OPTIONS_SHIFT 5

#define	PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)

#define	PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6

#define	PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)

#define	PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7

#define	PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)

#define	PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9

#define	PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)

#define	PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10

#define	PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)

#define	PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11

#define	PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)

#define	PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12

#define	PARSING_FLAGS_LLC_SNAP (0x1<<13)

#define	PARSING_FLAGS_LLC_SNAP_SHIFT 13

#define	PARSING_FLAGS_RESERVED0 (0x3<<14)

#define	PARSING_FLAGS_RESERVED0_SHIFT 14

#define	SDM_OP_GEN_COMP_PARAM (0x1F<<0)

#define	SDM_OP_GEN_COMP_PARAM_SHIFT 0

#define	SDM_OP_GEN_COMP_TYPE (0x7<<5)

#define	SDM_OP_GEN_COMP_TYPE_SHIFT 5

#define	SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)

#define	SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8

#define	SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)

#define	SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16

#define	SDM_OP_GEN_RESERVED (0x7FFF<<17)

#define	SDM_OP_GEN_RESERVED_SHIFT 17

#define	__TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)

#define	__TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0

#define	TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)

#define	TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2

#define	__TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)

#define	__TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3

#define	CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)

#define	CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0

#define	CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)

#define	CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1

#define	CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)

#define	CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2

#define	CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)

#define	CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3

#define	CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)

#define	CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0

#define	CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)

#define	CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1

#define	CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)

#define	CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2

#define	CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)

#define	CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3

#define	CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)

#define	CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4

#define	CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)

#define	CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5

#define	CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)

#define	CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6

#define	CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)

#define	CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7

#define	CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)

#define	CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0

#define	CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)

#define	CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1

#define	CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)

#define	CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2

#define	CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)

#define	CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3

#define	CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)

#define	CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4

#define	ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)

#define	ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0

#define	ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)

#define	ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1

#define	ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)

#define	ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2

#define	ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)

#define	ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4

#define	ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)

#define	ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5

#define	ETH_END_AGG_RX_CQE_TYPE (0x3<<0)

#define	ETH_END_AGG_RX_CQE_TYPE_SHIFT 0

#define	ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)

#define	ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2

#define	ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)

#define	ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3

#define	ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)

#define	ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0

#define	ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)

#define	ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2

#define	ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)

#define	ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3

#define	ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)

#define	ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4

#define	ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)

#define	ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5

#define	ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)

#define	ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6

#define	ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)

#define	ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0

#define	ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)

#define	ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3

#define	ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)

#define	ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4

#define	ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)

#define	ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5

#define	ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)

#define	ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6

#define	ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)

#define	ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7

#define	ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)

#define	ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0

#define	ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)

#define	ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1

#define	ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)

#define	ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2

#define	ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)

#define	ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0

#define	ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)

#define	ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1

#define	ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)

#define	ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2

#define	ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)

#define	ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3

#define	ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)

#define	ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4

#define	ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)

#define	ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5

#define	ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)

#define	ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6

#define	ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)

#define	ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7

#define	ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)

#define	ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0

#define	ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)

#define	ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1

#define	ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)

#define	ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2

#define	ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)

#define	ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)

#define	ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5

#define	ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)

#define	ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7

#define	COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)

#define	COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0

#define	COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)

#define	COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2

#define	COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)

#define	COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3

#define	COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)

#define	COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0

#define	COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)

#define	COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24

#define	SPE_HDR_CID (0xFFFFFF<<0)

#define	SPE_HDR_CID_SHIFT 0

#define	SPE_HDR_CMD_ID (0xFF<<24)

#define	SPE_HDR_CMD_ID_SHIFT 24

#define	SPE_HDR_CONN_TYPE (0xFF<<0)

#define	SPE_HDR_CONN_TYPE_SHIFT 0

#define	SPE_HDR_FUNCTION_ID (0xFF<<8)

#define	SPE_HDR_FUNCTION_ID_SHIFT 8

#define	ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)

#define	ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0

#define	ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)

#define	ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1

#define	ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)

#define	ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2

#define	ETH_TX_BD_FLAGS_START_BD (0x1<<4)

#define	ETH_TX_BD_FLAGS_START_BD_SHIFT 4

#define	ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)

#define	ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5

#define	ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)

#define	ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6

#define	ETH_TX_BD_FLAGS_IPV6 (0x1<<7)

#define	ETH_TX_BD_FLAGS_IPV6_SHIFT 7

#define	ETH_TX_START_BD_HDR_NBDS (0xF<<0)

#define	ETH_TX_START_BD_HDR_NBDS_SHIFT 0

#define	ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)

#define	ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4

#define	ETH_TX_START_BD_PARSE_NBDS (0x3<<5)

#define	ETH_TX_START_BD_PARSE_NBDS_SHIFT 5

#define	ETH_TX_START_BD_RESREVED (0x1<<7)

#define	ETH_TX_START_BD_RESREVED_SHIFT 7

#define	ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)

#define	ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0

#define	ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)

#define	ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4

#define	ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)

#define	ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6

#define	ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)

#define	ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7

#define	ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)

#define	ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8

#define	ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)

#define	ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9

#define	ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)

#define	ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0

#define	ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)

#define	ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1

#define	ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)

#define	ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2

#define	ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)

#define	ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3

#define	ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)

#define	ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4

#define	ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)

#define	ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5

#define	ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)

#define	ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6

#define	ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)

#define	ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7

#define	ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0)

#define	ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0

#define	ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)

#define	ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11

#define	ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)

#define	ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15

#define	ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)

#define	ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16

#define	ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)

#define	ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30

#define	MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)

#define	MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0

#define	MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)

#define	MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1

#define	MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)

#define	MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2

#define	MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)

#define	MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4

#define	MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)

#define	MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5

#define	MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)

#define	MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)

#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7

#define	__TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)

#define	__TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8

#define	CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)

#define	CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0

#define	CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)

#define	CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1

#define	CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)

#define	CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2

#define	CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)

#define	CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3

#define	__CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)

#define	__CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4

#define	FW_VERSION_OPTIMIZED (0x1<<0)

#define	FW_VERSION_OPTIMIZED_SHIFT 0

#define	FW_VERSION_BIG_ENDIEN (0x1<<1)

#define	FW_VERSION_BIG_ENDIEN_SHIFT 1

#define	FW_VERSION_CHIP_VERSION (0x3<<2)

#define	FW_VERSION_CHIP_VERSION_SHIFT 2

#define	__FW_VERSION_RESERVED (0xFFFFFFF<<4)

#define	__FW_VERSION_RESERVED_SHIFT 4

#define	PRAM_FW_VERSION_OPTIMIZED (0x1<<0)

#define	PRAM_FW_VERSION_OPTIMIZED_SHIFT 0

#define	PRAM_FW_VERSION_STORM_ID (0x3<<1)

#define	PRAM_FW_VERSION_STORM_ID_SHIFT 1

#define	PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)

#define	PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3

#define	PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)

#define	PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4

#define	__PRAM_FW_VERSION_RESERVED0 (0x3<<6)

#define	__PRAM_FW_VERSION_RESERVED0_SHIFT 6

Enumerations
enum	mf_cfg_afex_vlan_mode { FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE }

enum	igu_ctrl_cmd { IGU_CTRL_CMD_TYPE_RD, IGU_CTRL_CMD_TYPE_WR, MAX_IGU_CTRL_CMD }

enum	igu_int_cmd { IGU_INT_ENABLE, IGU_INT_DISABLE, IGU_INT_NOP, IGU_INT_NOP2, MAX_IGU_INT_CMD }

enum	igu_seg_access { IGU_SEG_ACCESS_NORM, IGU_SEG_ACCESS_DEF, IGU_SEG_ACCESS_ATTN, MAX_IGU_SEG_ACCESS }

enum	prs_flags_ack_type { PRS_FLAG_PUREACK_PIGGY, PRS_FLAG_PUREACK_PURE, MAX_PRS_FLAGS_ACK_TYPE }

enum	prs_flags_eth_addr_type { PRS_FLAG_ETHTYPE_NON_UNICAST, PRS_FLAG_ETHTYPE_UNICAST, MAX_PRS_FLAGS_ETH_ADDR_TYPE }

enum	prs_flags_over_eth { PRS_FLAG_OVERETH_UNKNOWN, PRS_FLAG_OVERETH_IPV4, PRS_FLAG_OVERETH_IPV6, PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, MAX_PRS_FLAGS_OVER_ETH }

enum	prs_flags_over_ip { PRS_FLAG_OVERIP_UNKNOWN, PRS_FLAG_OVERIP_TCP, PRS_FLAG_OVERIP_UDP, MAX_PRS_FLAGS_OVER_IP }

enum	classify_rule { CLASSIFY_RULE_OPCODE_MAC, CLASSIFY_RULE_OPCODE_VLAN, CLASSIFY_RULE_OPCODE_PAIR, MAX_CLASSIFY_RULE }

enum	classify_rule_action_type { CLASSIFY_RULE_REMOVE, CLASSIFY_RULE_ADD, MAX_CLASSIFY_RULE_ACTION_TYPE }

enum	eth_addr_type { UNKNOWN_ADDRESS, UNICAST_ADDRESS, MULTICAST_ADDRESS, BROADCAST_ADDRESS, MAX_ETH_ADDR_TYPE }

enum	eth_rss_hash_type { DEFAULT_HASH_TYPE, IPV4_HASH_TYPE, TCP_IPV4_HASH_TYPE, IPV6_HASH_TYPE, TCP_IPV6_HASH_TYPE, VLAN_PRI_HASH_TYPE, E1HOV_PRI_HASH_TYPE, DSCP_HASH_TYPE, MAX_ETH_RSS_HASH_TYPE }

enum	eth_rss_mode { ETH_RSS_MODE_DISABLED, ETH_RSS_MODE_REGULAR, ETH_RSS_MODE_VLAN_PRI, ETH_RSS_MODE_E1HOV_PRI, ETH_RSS_MODE_IP_DSCP, MAX_ETH_RSS_MODE }

enum	eth_rx_cqe_type { RX_ETH_CQE_TYPE_ETH_FASTPATH, RX_ETH_CQE_TYPE_ETH_RAMROD, RX_ETH_CQE_TYPE_ETH_START_AGG, RX_ETH_CQE_TYPE_ETH_STOP_AGG, MAX_ETH_RX_CQE_TYPE }

enum	eth_rx_fp_sel { ETH_FP_CQE_REGULAR, ETH_FP_CQE_RAW, MAX_ETH_RX_FP_SEL }

enum	eth_spqe_cmd_id { RAMROD_CMD_ID_ETH_UNUSED, RAMROD_CMD_ID_ETH_CLIENT_SETUP, RAMROD_CMD_ID_ETH_HALT, RAMROD_CMD_ID_ETH_FORWARD_SETUP, RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, RAMROD_CMD_ID_ETH_CLIENT_UPDATE, RAMROD_CMD_ID_ETH_EMPTY, RAMROD_CMD_ID_ETH_TERMINATE, RAMROD_CMD_ID_ETH_TPA_UPDATE, RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, RAMROD_CMD_ID_ETH_FILTER_RULES, RAMROD_CMD_ID_ETH_MULTICAST_RULES, RAMROD_CMD_ID_ETH_RSS_UPDATE, RAMROD_CMD_ID_ETH_SET_MAC, MAX_ETH_SPQE_CMD_ID }

enum	eth_tpa_update_command { TPA_UPDATE_NONE_COMMAND, TPA_UPDATE_ENABLE_COMMAND, TPA_UPDATE_DISABLE_COMMAND, MAX_ETH_TPA_UPDATE_COMMAND }

enum	eth_tx_vlan_type { X_ETH_NO_VLAN, X_ETH_OUTBAND_VLAN, X_ETH_INBAND_VLAN, X_ETH_FW_ADDED_VLAN, MAX_ETH_TX_VLAN_TYPE }

enum	eth_vlan_filter_mode { ETH_VLAN_FILTER_ANY_VLAN, ETH_VLAN_FILTER_SPECIFIC_VLAN, ETH_VLAN_FILTER_CLASSIFY, MAX_ETH_VLAN_FILTER_MODE }

enum	set_mac_action_type { T_ETH_MAC_COMMAND_INVALIDATE, T_ETH_MAC_COMMAND_SET, MAX_SET_MAC_ACTION_TYPE }

enum	tpa_mode { TPA_LRO, TPA_GRO, MAX_TPA_MODE }

enum	common_spqe_cmd_id { RAMROD_CMD_ID_COMMON_UNUSED, RAMROD_CMD_ID_COMMON_FUNCTION_START, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, RAMROD_CMD_ID_COMMON_CFC_DEL, RAMROD_CMD_ID_COMMON_CFC_DEL_WB, RAMROD_CMD_ID_COMMON_STAT_QUERY, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, RAMROD_CMD_ID_COMMON_START_TRAFFIC, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, MAX_COMMON_SPQE_CMD_ID }

enum	connection_type { ETH_CONNECTION_TYPE, TOE_CONNECTION_TYPE, RDMA_CONNECTION_TYPE, ISCSI_CONNECTION_TYPE, FCOE_CONNECTION_TYPE, RESERVED_CONNECTION_TYPE_0, RESERVED_CONNECTION_TYPE_1, RESERVED_CONNECTION_TYPE_2, NONE_CONNECTION_TYPE, MAX_CONNECTION_TYPE }

enum	cos_mode { OVERRIDE_COS, STATIC_COS, FW_WRR, MAX_COS_MODE }

enum	event_ring_opcode { EVENT_RING_OPCODE_VF_PF_CHANNEL, EVENT_RING_OPCODE_FUNCTION_START, EVENT_RING_OPCODE_FUNCTION_STOP, EVENT_RING_OPCODE_CFC_DEL, EVENT_RING_OPCODE_CFC_DEL_WB, EVENT_RING_OPCODE_STAT_QUERY, EVENT_RING_OPCODE_STOP_TRAFFIC, EVENT_RING_OPCODE_START_TRAFFIC, EVENT_RING_OPCODE_VF_FLR, EVENT_RING_OPCODE_MALICIOUS_VF, EVENT_RING_OPCODE_FORWARD_SETUP, EVENT_RING_OPCODE_RSS_UPDATE_RULES, EVENT_RING_OPCODE_FUNCTION_UPDATE, EVENT_RING_OPCODE_AFEX_VIF_LISTS, EVENT_RING_OPCODE_SET_MAC, EVENT_RING_OPCODE_CLASSIFICATION_RULES, EVENT_RING_OPCODE_FILTERS_RULES, EVENT_RING_OPCODE_MULTICAST_RULES, MAX_EVENT_RING_OPCODE }

enum	fairness_mode { FAIRNESS_COS_WRR_MODE, FAIRNESS_COS_ETS_MODE, MAX_FAIRNESS_MODE }

enum	hc_segment { HC_REGULAR_SEGMENT, HC_DEFAULT_SEGMENT, MAX_HC_SEGMENT }

enum	igu_mode { HC_IGU_BC_MODE, HC_IGU_NBC_MODE, MAX_IGU_MODE }

enum	ip_ver { IP_V4, IP_V6, MAX_IP_VER }

enum	mf_mode { SINGLE_FUNCTION, MULTI_FUNCTION_SD, MULTI_FUNCTION_SI, MULTI_FUNCTION_AFEX, MAX_MF_MODE }

enum	stats_query_type { STATS_TYPE_QUEUE, STATS_TYPE_PORT, STATS_TYPE_PF, STATS_TYPE_TOE, STATS_TYPE_FCOE, MAX_STATS_QUERY_TYPE }

enum	status_block_state { SB_DISABLED, SB_ENABLED, SB_CLEANED, MAX_STATUS_BLOCK_STATE }

enum	storm_id { USTORM_ID, CSTORM_ID, XSTORM_ID, TSTORM_ID, ATTENTION_ID, MAX_STORM_ID }

enum	traffic_type { LLFC_TRAFFIC_TYPE_NW, LLFC_TRAFFIC_TYPE_FCOE, LLFC_TRAFFIC_TYPE_ISCSI, MAX_TRAFFIC_TYPE, TRAFFIC_TYPE_APERIODIC = 0, TRAFFIC_TYPE_PERIODIC = 1 }

enum	vf_pf_channel_state { VF_PF_CHANNEL_STATE_READY, VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, MAX_VF_PF_CHANNEL_STATE }

enum	vif_list_rule_kind { VIF_LIST_RULE_SET, VIF_LIST_RULE_GET, VIF_LIST_RULE_CLEAR_ALL, VIF_LIST_RULE_CLEAR_FUNC, MAX_VIF_LIST_RULE_KIND }

Macro Definition Documentation

#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)

Definition at line 4506 of file bnx2x_hsi.h.

#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4

Definition at line 4507 of file bnx2x_hsi.h.

#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)

Definition at line 5014 of file bnx2x_hsi.h.

#define __FW_VERSION_RESERVED_SHIFT 4

Definition at line 5015 of file bnx2x_hsi.h.

#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)

Definition at line 5302 of file bnx2x_hsi.h.

#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6

Definition at line 5303 of file bnx2x_hsi.h.

#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)

Definition at line 3260 of file bnx2x_hsi.h.

#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0

Definition at line 3261 of file bnx2x_hsi.h.

#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)

Definition at line 3264 of file bnx2x_hsi.h.

#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3

Definition at line 3265 of file bnx2x_hsi.h.

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)

Definition at line 4364 of file bnx2x_hsi.h.

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8

Definition at line 4365 of file bnx2x_hsi.h.

#define BCM_5710_FW_COMPILE_FLAGS 1

Definition at line 2795 of file bnx2x_hsi.h.

#define BCM_5710_FW_ENGINEERING_VERSION 0

Definition at line 2794 of file bnx2x_hsi.h.

#define BCM_5710_FW_MAJOR_VERSION 7

Definition at line 2791 of file bnx2x_hsi.h.

#define BCM_5710_FW_MINOR_VERSION 8

Definition at line 2792 of file bnx2x_hsi.h.

#define BCM_5710_FW_REVISION_VERSION 2

Definition at line 2793 of file bnx2x_hsi.h.

#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000

Definition at line 1278 of file bnx2x_hsi.h.

#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000

Definition at line 1279 of file bnx2x_hsi.h.

#define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000

Definition at line 1281 of file bnx2x_hsi.h.

#define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000

Definition at line 1280 of file bnx2x_hsi.h.

#define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000

Definition at line 31 of file bnx2x_hsi.h.

#define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16

Definition at line 32 of file bnx2x_hsi.h.

#define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF

Definition at line 29 of file bnx2x_hsi.h.

#define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0

Definition at line 30 of file bnx2x_hsi.h.

#define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000

Definition at line 23 of file bnx2x_hsi.h.

#define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16

Definition at line 24 of file bnx2x_hsi.h.

#define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF

Definition at line 21 of file bnx2x_hsi.h.

#define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0

Definition at line 22 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)

Definition at line 3444 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6

Definition at line 3445 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)

Definition at line 3442 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5

Definition at line 3443 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)

Definition at line 3440 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4

Definition at line 3441 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)

Definition at line 3438 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3

Definition at line 3439 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)

Definition at line 3446 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7

Definition at line 3447 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)

Definition at line 3402 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3

Definition at line 3403 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)

Definition at line 3396 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0

Definition at line 3397 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)

Definition at line 3398 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1

Definition at line 3399 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)

Definition at line 3400 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2

Definition at line 3401 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)

Definition at line 3434 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1

Definition at line 3435 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)

Definition at line 3436 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2

Definition at line 3437 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)

Definition at line 3432 of file bnx2x_hsi.h.

#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0

Definition at line 3433 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)

Definition at line 3479 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3

Definition at line 3480 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)

Definition at line 3477 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2

Definition at line 3478 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)

Definition at line 3475 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1

Definition at line 3476 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)

Definition at line 3481 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4

Definition at line 3482 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)

Definition at line 3473 of file bnx2x_hsi.h.

#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0

Definition at line 3474 of file bnx2x_hsi.h.

#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)

Definition at line 4502 of file bnx2x_hsi.h.

#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)

Definition at line 4504 of file bnx2x_hsi.h.

#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3

Definition at line 4505 of file bnx2x_hsi.h.

#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2

Definition at line 4503 of file bnx2x_hsi.h.

#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)

Definition at line 4498 of file bnx2x_hsi.h.

#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0

Definition at line 4499 of file bnx2x_hsi.h.

#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)

Definition at line 4500 of file bnx2x_hsi.h.

#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1

Definition at line 4501 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)

Definition at line 3950 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0

Definition at line 3951 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)

Definition at line 3952 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24

Definition at line 3953 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)

Definition at line 3943 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2

Definition at line 3944 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)

Definition at line 3945 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3

Definition at line 3946 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)

Definition at line 3941 of file bnx2x_hsi.h.

#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0

Definition at line 3942 of file bnx2x_hsi.h.

#define DCBX_APP_CONFIG_TX_ENABLED 0x00000004

Definition at line 1861 of file bnx2x_hsi.h.

#define DCBX_APP_REM_WILLING 0x00000400

Definition at line 1889 of file bnx2x_hsi.h.

#define DCBX_APP_RX_ERROR 0x00000040

Definition at line 1886 of file bnx2x_hsi.h.

#define DCBX_APP_TLV_RX 0x00000004

Definition at line 1883 of file bnx2x_hsi.h.

#define DCBX_APP_WILLING 0x00000080

Definition at line 1866 of file bnx2x_hsi.h.

#define DCBX_BW_PG_BITWIDTH 8

Definition at line 1702 of file bnx2x_hsi.h.

#define DCBX_CEE_MAX_VERSION_MASK 0x000f0000

Definition at line 1872 of file bnx2x_hsi.h.

#define DCBX_CEE_MAX_VERSION_SHIFT 16

Definition at line 1873 of file bnx2x_hsi.h.

#define DCBX_CEE_VERSION_MASK 0x0000f000

Definition at line 1870 of file bnx2x_hsi.h.

#define DCBX_CEE_VERSION_SHIFT 12

Definition at line 1871 of file bnx2x_hsi.h.

#define DCBX_DCBX_ENABLED 0x00000400

Definition at line 1869 of file bnx2x_hsi.h.

#define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001

Definition at line 1859 of file bnx2x_hsi.h.

#define DCBX_ETS_RECO_TX_ENABLED 0x00000008

Definition at line 1862 of file bnx2x_hsi.h.

#define DCBX_ETS_RECO_VALID 0x00000010

Definition at line 1863 of file bnx2x_hsi.h.

#define DCBX_ETS_REM_WILLING 0x00000100

Definition at line 1887 of file bnx2x_hsi.h.

#define DCBX_ETS_RX_ERROR 0x00000010

Definition at line 1884 of file bnx2x_hsi.h.

#define DCBX_ETS_TLV_RX 0x00000001

Definition at line 1881 of file bnx2x_hsi.h.

#define DCBX_ETS_WILLING 0x00000020

Definition at line 1864 of file bnx2x_hsi.h.

#define DCBX_LOCAL_APP_ERROR 0x00000004

Definition at line 1903 of file bnx2x_hsi.h.

#define DCBX_LOCAL_APP_MISMATCH 0x00000020

Definition at line 1905 of file bnx2x_hsi.h.

#define DCBX_LOCAL_ETS_ERROR 0x00000001

Definition at line 1901 of file bnx2x_hsi.h.

#define DCBX_LOCAL_PFC_ERROR 0x00000002

Definition at line 1902 of file bnx2x_hsi.h.

#define DCBX_LOCAL_PFC_MISMATCH 0x00000010

Definition at line 1904 of file bnx2x_hsi.h.

#define DCBX_MAX_APP_PROTOCOL 16

Definition at line 1708 of file bnx2x_hsi.h.

#define DCBX_MAX_NUM_PG_BW_ENTRIES 8

Definition at line 1701 of file bnx2x_hsi.h.

#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8

Definition at line 1694 of file bnx2x_hsi.h.

#define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002

Definition at line 1860 of file bnx2x_hsi.h.

#define DCBX_PFC_REM_WILLING 0x00000200

Definition at line 1888 of file bnx2x_hsi.h.

#define DCBX_PFC_RX_ERROR 0x00000020

Definition at line 1885 of file bnx2x_hsi.h.

#define DCBX_PFC_TLV_RX 0x00000002

Definition at line 1882 of file bnx2x_hsi.h.

#define DCBX_PFC_WILLING 0x00000040

Definition at line 1865 of file bnx2x_hsi.h.

#define DCBX_PG_BW_GET	(	a,
		i
	)	SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)

Definition at line 1703 of file bnx2x_hsi.h.

#define DCBX_PG_BW_SET	(	a,
		i,
		val
	)	SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)

Definition at line 1705 of file bnx2x_hsi.h.

#define DCBX_PRI_PG_BITWIDTH 4

Definition at line 1695 of file bnx2x_hsi.h.

#define DCBX_PRI_PG_FBITS 8

Definition at line 1696 of file bnx2x_hsi.h.

#define DCBX_PRI_PG_GET	(	a,
		i
	)	SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)

Definition at line 1697 of file bnx2x_hsi.h.

#define DCBX_PRI_PG_SET	(	a,
		i,
		val
	)	SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)

Definition at line 1699 of file bnx2x_hsi.h.

#define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200

Definition at line 1909 of file bnx2x_hsi.h.

#define DCBX_REMOTE_ETS_RECO_VALID 0x00001000

Definition at line 1890 of file bnx2x_hsi.h.

#define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080

Definition at line 1907 of file bnx2x_hsi.h.

#define DCBX_REMOTE_MIB_ERROR 0x00000040

Definition at line 1906 of file bnx2x_hsi.h.

#define DCBX_REMOTE_MIB_VALID 0x00002000

Definition at line 1891 of file bnx2x_hsi.h.

#define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100

Definition at line 1908 of file bnx2x_hsi.h.

#define DCBX_STRICT_PRI_PG 15

Definition at line 1707 of file bnx2x_hsi.h.

#define DCBX_VERSION_CEE 0x00000100

Definition at line 1867 of file bnx2x_hsi.h.

#define DCBX_VERSION_IEEE 0x00000200

Definition at line 1868 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_DST (0x1<<3)

Definition at line 2828 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_DST_SHIFT 3

Definition at line 2829 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_FUNC (0x1<<19)

Definition at line 2850 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_FUNC_SHIFT 19

Definition at line 2851 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)

Definition at line 2832 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5

Definition at line 2833 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)

Definition at line 2834 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6

Definition at line 2835 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)

Definition at line 2830 of file bnx2x_hsi.h.

#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4

Definition at line 2831 of file bnx2x_hsi.h.

#define DMAE_COMMAND_CRC_RESET (0x1<<12)

Definition at line 2840 of file bnx2x_hsi.h.

#define DMAE_COMMAND_CRC_RESET_SHIFT 12

Definition at line 2841 of file bnx2x_hsi.h.

#define DMAE_COMMAND_DST (0x3<<1)

Definition at line 2826 of file bnx2x_hsi.h.

#define DMAE_COMMAND_DST_RESET (0x1<<14)

Definition at line 2844 of file bnx2x_hsi.h.

#define DMAE_COMMAND_DST_RESET_SHIFT 14

Definition at line 2845 of file bnx2x_hsi.h.

#define DMAE_COMMAND_DST_SHIFT 1

Definition at line 2827 of file bnx2x_hsi.h.

#define DMAE_COMMAND_DST_VN (0x3<<17)

Definition at line 2848 of file bnx2x_hsi.h.

#define DMAE_COMMAND_DST_VN_SHIFT 17

Definition at line 2849 of file bnx2x_hsi.h.

#define DMAE_COMMAND_E1HVN (0x3<<15)

Definition at line 2846 of file bnx2x_hsi.h.

#define DMAE_COMMAND_E1HVN_SHIFT 15

Definition at line 2847 of file bnx2x_hsi.h.

#define DMAE_COMMAND_ENDIANITY (0x3<<9)

Definition at line 2836 of file bnx2x_hsi.h.

#define DMAE_COMMAND_ENDIANITY_SHIFT 9

Definition at line 2837 of file bnx2x_hsi.h.

#define DMAE_COMMAND_ERR_POLICY (0x3<<20)

Definition at line 2852 of file bnx2x_hsi.h.

#define DMAE_COMMAND_ERR_POLICY_SHIFT 20

Definition at line 2853 of file bnx2x_hsi.h.

#define DMAE_COMMAND_PORT (0x1<<11)

Definition at line 2838 of file bnx2x_hsi.h.

#define DMAE_COMMAND_PORT_SHIFT 11

Definition at line 2839 of file bnx2x_hsi.h.

#define DMAE_COMMAND_RESERVED0 (0x3FF<<22)

Definition at line 2854 of file bnx2x_hsi.h.

#define DMAE_COMMAND_RESERVED0_SHIFT 22

Definition at line 2855 of file bnx2x_hsi.h.

#define DMAE_COMMAND_SRC (0x1<<0)

Definition at line 2824 of file bnx2x_hsi.h.

#define DMAE_COMMAND_SRC_RESET (0x1<<13)

Definition at line 2842 of file bnx2x_hsi.h.

#define DMAE_COMMAND_SRC_RESET_SHIFT 13

Definition at line 2843 of file bnx2x_hsi.h.

#define DMAE_COMMAND_SRC_SHIFT 0

Definition at line 2825 of file bnx2x_hsi.h.

#define DOORBELL_HDR_CONN_TYPE (0xF<<4)

Definition at line 2931 of file bnx2x_hsi.h.

#define DOORBELL_HDR_CONN_TYPE_SHIFT 4

Definition at line 2932 of file bnx2x_hsi.h.

#define DOORBELL_HDR_DB_TYPE (0x1<<1)

Definition at line 2927 of file bnx2x_hsi.h.

#define DOORBELL_HDR_DB_TYPE_SHIFT 1

Definition at line 2928 of file bnx2x_hsi.h.

#define DOORBELL_HDR_DPM_SIZE (0x3<<2)

Definition at line 2929 of file bnx2x_hsi.h.

#define DOORBELL_HDR_DPM_SIZE_SHIFT 2

Definition at line 2930 of file bnx2x_hsi.h.

#define DOORBELL_HDR_RX (0x1<<0)

Definition at line 2925 of file bnx2x_hsi.h.

#define DOORBELL_HDR_RX_SHIFT 0

Definition at line 2926 of file bnx2x_hsi.h.

#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004

Definition at line 2106 of file bnx2x_hsi.h.

#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008

Definition at line 2107 of file bnx2x_hsi.h.

#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002

Definition at line 2105 of file bnx2x_hsi.h.

#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001

Definition at line 2104 of file bnx2x_hsi.h.

#define DRV_FLAGS_DCB_CONFIGURED 0x1

Definition at line 2088 of file bnx2x_hsi.h.

#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00

Definition at line 2124 of file bnx2x_hsi.h.

#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8

Definition at line 2125 of file bnx2x_hsi.h.

#define DRV_INFO_CONTROL_VER_MASK 0x000000ff

Definition at line 2122 of file bnx2x_hsi.h.

#define DRV_INFO_CONTROL_VER_SHIFT 0

Definition at line 2123 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000

Definition at line 1258 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000

Definition at line 1259 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000

Definition at line 1260 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000

Definition at line 1261 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000

Definition at line 1262 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000

Definition at line 1252 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000

Definition at line 1253 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_DCC_FAILURE 0x31000000

Definition at line 1229 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_DCC_OK 0x30000000

Definition at line 1228 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000

Definition at line 1230 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000

Definition at line 1231 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000

Definition at line 1264 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000

Definition at line 1265 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000

Definition at line 1267 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000

Definition at line 1233 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000

Definition at line 1235 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000

Definition at line 1234 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_INITIATE_FLR 0x02000000

Definition at line 1275 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000

Definition at line 1273 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_LOAD_DONE 0x11000000

Definition at line 1223 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000

Definition at line 1236 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_LOAD_REQ 0x10000000

Definition at line 1222 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a

Definition at line 1291 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_MASK 0xffff0000

Definition at line 1221 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_SET_MF_BW 0xe0000000

Definition at line 1269 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000

Definition at line 1271 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000

Definition at line 1287 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000

Definition at line 1286 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000

Definition at line 1227 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000

Definition at line 1225 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000

Definition at line 1224 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000

Definition at line 1226 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002

Definition at line 1289 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000

Definition at line 1232 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000

Definition at line 1256 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000

Definition at line 1246 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000

Definition at line 1242 of file bnx2x_hsi.h.

#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000

Definition at line 1244 of file bnx2x_hsi.h.

#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff

Definition at line 1283 of file bnx2x_hsi.h.

#define DRV_PULSE_ALWAYS_ALIVE 0x00008000

Definition at line 1360 of file bnx2x_hsi.h.

#define DRV_PULSE_PERIOD_MS 250

Definition at line 1125 of file bnx2x_hsi.h.

#define DRV_PULSE_SEQ_MASK 0x00007fff

Definition at line 1354 of file bnx2x_hsi.h.

#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000

Definition at line 1355 of file bnx2x_hsi.h.

#define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000

Definition at line 1394 of file bnx2x_hsi.h.

#define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000

Definition at line 1395 of file bnx2x_hsi.h.

#define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000

Definition at line 1396 of file bnx2x_hsi.h.

#define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000

Definition at line 1397 of file bnx2x_hsi.h.

#define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000

Definition at line 1398 of file bnx2x_hsi.h.

#define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000

Definition at line 1392 of file bnx2x_hsi.h.

#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000

Definition at line 1393 of file bnx2x_hsi.h.

#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200

Definition at line 1386 of file bnx2x_hsi.h.

#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400

Definition at line 1387 of file bnx2x_hsi.h.

#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100

Definition at line 1385 of file bnx2x_hsi.h.

#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00

Definition at line 1384 of file bnx2x_hsi.h.

#define DRV_STATUS_DCC_RESERVED1 0x00000800

Definition at line 1388 of file bnx2x_hsi.h.

#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000

Definition at line 1390 of file bnx2x_hsi.h.

#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000

Definition at line 1389 of file bnx2x_hsi.h.

#define DRV_STATUS_DRV_INFO_REQ 0x04000000

Definition at line 1400 of file bnx2x_hsi.h.

#define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000

Definition at line 1402 of file bnx2x_hsi.h.

#define DRV_STATUS_LINK_EVENT 0x00000008

Definition at line 1382 of file bnx2x_hsi.h.

#define DRV_STATUS_PMF 0x00000001

Definition at line 1379 of file bnx2x_hsi.h.

#define DRV_STATUS_SET_MF_BW 0x00000004

Definition at line 1381 of file bnx2x_hsi.h.

#define DRV_STATUS_VF_DISABLED 0x00000002

Definition at line 1380 of file bnx2x_hsi.h.

#define E1_FUNC_MAX 2

Definition at line 1110 of file bnx2x_hsi.h.

#define E1H_FUNC_MAX 8

Definition at line 1111 of file bnx2x_hsi.h.

#define E1HVN_MAX 4

Definition at line 1119 of file bnx2x_hsi.h.

#define E1VN_MAX 1

Definition at line 1118 of file bnx2x_hsi.h.

#define E2_FUNC_MAX 4 /* per path */

Definition at line 1112 of file bnx2x_hsi.h.

#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */

Definition at line 1121 of file bnx2x_hsi.h.

#define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3

Definition at line 2058 of file bnx2x_hsi.h.

#define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2

Definition at line 2057 of file bnx2x_hsi.h.

#define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1

Definition at line 2056 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO0 0x00000001

Definition at line 84 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO1 0x00000002

Definition at line 85 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO10 0x0000000b

Definition at line 94 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO11 0x0000000c

Definition at line 95 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO12 0x0000000d

Definition at line 96 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO13 0x0000000e

Definition at line 97 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO14 0x0000000f

Definition at line 98 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO15 0x00000010

Definition at line 99 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO16 0x00000011

Definition at line 100 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO17 0x00000012

Definition at line 101 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO18 0x00000013

Definition at line 102 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO19 0x00000014

Definition at line 103 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO2 0x00000003

Definition at line 86 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO20 0x00000015

Definition at line 104 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO21 0x00000016

Definition at line 105 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO22 0x00000017

Definition at line 106 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO23 0x00000018

Definition at line 107 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO24 0x00000019

Definition at line 108 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO25 0x0000001a

Definition at line 109 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO26 0x0000001b

Definition at line 110 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO27 0x0000001c

Definition at line 111 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO28 0x0000001d

Definition at line 112 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO29 0x0000001e

Definition at line 113 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO3 0x00000004

Definition at line 87 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO30 0x0000001f

Definition at line 114 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO31 0x00000020

Definition at line 115 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO4 0x00000005

Definition at line 88 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO5 0x00000006

Definition at line 89 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO6 0x00000007

Definition at line 90 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO7 0x00000008

Definition at line 91 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO8 0x00000009

Definition at line 92 of file bnx2x_hsi.h.

#define EPIO_CFG_EPIO9 0x0000000a

Definition at line 93 of file bnx2x_hsi.h.

#define EPIO_CFG_NA 0x00000000

Definition at line 83 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)

Definition at line 3562 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4

Definition at line 3563 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)

Definition at line 3560 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2

Definition at line 3561 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)

Definition at line 3564 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5

Definition at line 3565 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)

Definition at line 3556 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0

Definition at line 3557 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)

Definition at line 3558 of file bnx2x_hsi.h.

#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1

Definition at line 3559 of file bnx2x_hsi.h.

#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)

Definition at line 3701 of file bnx2x_hsi.h.

#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3

Definition at line 3702 of file bnx2x_hsi.h.

#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)

Definition at line 3699 of file bnx2x_hsi.h.

#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2

Definition at line 3700 of file bnx2x_hsi.h.

#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)

Definition at line 3697 of file bnx2x_hsi.h.

#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0

Definition at line 3698 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)

Definition at line 3739 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4

Definition at line 3740 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)

Definition at line 3728 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4

Definition at line 3729 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)

Definition at line 3743 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6

Definition at line 3744 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)

Definition at line 3730 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5

Definition at line 3731 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)

Definition at line 3745 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7

Definition at line 3746 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)

Definition at line 3741 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5

Definition at line 3742 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)

Definition at line 3726 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3

Definition at line 3727 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)

Definition at line 3732 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6

Definition at line 3733 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)

Definition at line 3737 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3

Definition at line 3738 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)

Definition at line 3735 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0

Definition at line 3736 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)

Definition at line 3724 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2

Definition at line 3725 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)

Definition at line 3722 of file bnx2x_hsi.h.

#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0

Definition at line 3723 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)

Definition at line 3786 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6

Definition at line 3787 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)

Definition at line 3784 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5

Definition at line 3785 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)

Definition at line 3782 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4

Definition at line 3783 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)

Definition at line 3780 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3

Definition at line 3781 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)

Definition at line 3768 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2

Definition at line 3769 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)

Definition at line 3788 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7

Definition at line 3789 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)

Definition at line 3764 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0

Definition at line 3765 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)

Definition at line 3766 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1

Definition at line 3767 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)

Definition at line 3776 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1

Definition at line 3777 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)

Definition at line 3778 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2

Definition at line 3779 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)

Definition at line 3774 of file bnx2x_hsi.h.

#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0

Definition at line 3775 of file bnx2x_hsi.h.

#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)

Definition at line 3831 of file bnx2x_hsi.h.

#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2

Definition at line 3832 of file bnx2x_hsi.h.

#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)

Definition at line 3833 of file bnx2x_hsi.h.

#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3

Definition at line 3834 of file bnx2x_hsi.h.

#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)

Definition at line 3827 of file bnx2x_hsi.h.

#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0

Definition at line 3828 of file bnx2x_hsi.h.

#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)

Definition at line 3829 of file bnx2x_hsi.h.

#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1

Definition at line 3830 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)

Definition at line 3903 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0

Definition at line 3904 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)

Definition at line 3905 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1

Definition at line 3906 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)

Definition at line 3907 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2

Definition at line 3908 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)

Definition at line 3909 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3

Definition at line 3910 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)

Definition at line 3911 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4

Definition at line 3912 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)

Definition at line 3913 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5

Definition at line 3914 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)

Definition at line 3915 of file bnx2x_hsi.h.

#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7

Definition at line 3916 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)

Definition at line 4101 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0

Definition at line 4102 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)

Definition at line 4113 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7

Definition at line 4114 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)

Definition at line 4109 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5

Definition at line 4110 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)

Definition at line 4103 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1

Definition at line 4104 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)

Definition at line 4107 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4

Definition at line 4108 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)

Definition at line 4111 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6

Definition at line 4112 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)

Definition at line 4105 of file bnx2x_hsi.h.

#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2

Definition at line 4106 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)

Definition at line 4164 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4

Definition at line 4165 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)

Definition at line 4170 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7

Definition at line 4171 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)

Definition at line 4168 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6

Definition at line 4169 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)

Definition at line 4145 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4

Definition at line 4146 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)

Definition at line 4156 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0

Definition at line 4157 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)

Definition at line 4143 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0

Definition at line 4144 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)

Definition at line 4149 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7

Definition at line 4150 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)

Definition at line 4151 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8

Definition at line 4152 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)

Definition at line 4147 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6

Definition at line 4148 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)

Definition at line 4162 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3

Definition at line 4163 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)

Definition at line 4153 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9

Definition at line 4154 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)

Definition at line 4160 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2

Definition at line 4161 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)

Definition at line 4158 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1

Definition at line 4159 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)

Definition at line 4166 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5

Definition at line 4167 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)

Definition at line 4199 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30

Definition at line 4200 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)

Definition at line 4195 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15

Definition at line 4196 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)

Definition at line 4197 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16

Definition at line 4198 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)

Definition at line 4193 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11

Definition at line 4194 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0)

Definition at line 4191 of file bnx2x_hsi.h.

#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0

Definition at line 4192 of file bnx2x_hsi.h.

#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)

Definition at line 4130 of file bnx2x_hsi.h.

#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4

Definition at line 4131 of file bnx2x_hsi.h.

#define ETH_TX_START_BD_HDR_NBDS (0xF<<0)

Definition at line 4128 of file bnx2x_hsi.h.

#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0

Definition at line 4129 of file bnx2x_hsi.h.

#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)

Definition at line 4132 of file bnx2x_hsi.h.

#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5

Definition at line 4133 of file bnx2x_hsi.h.

#define ETH_TX_START_BD_RESREVED (0x1<<7)

Definition at line 4134 of file bnx2x_hsi.h.

#define ETH_TX_START_BD_RESREVED_SHIFT 7

Definition at line 4135 of file bnx2x_hsi.h.

#define FCOE_APP_IDX 0

Definition at line 1709 of file bnx2x_hsi.h.

#define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF

Definition at line 1965 of file bnx2x_hsi.h.

#define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0

Definition at line 1966 of file bnx2x_hsi.h.

#define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000

Definition at line 1968 of file bnx2x_hsi.h.

#define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16

Definition at line 1969 of file bnx2x_hsi.h.

#define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF

Definition at line 1972 of file bnx2x_hsi.h.

#define FCOE_FEATURES2_EXCHANGES_OFFSET 0

Definition at line 1973 of file bnx2x_hsi.h.

#define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000

Definition at line 1975 of file bnx2x_hsi.h.

#define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16

Definition at line 1976 of file bnx2x_hsi.h.

#define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000

Definition at line 1982 of file bnx2x_hsi.h.

#define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16

Definition at line 1983 of file bnx2x_hsi.h.

#define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF

Definition at line 1979 of file bnx2x_hsi.h.

#define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0

Definition at line 1980 of file bnx2x_hsi.h.

#define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F

Definition at line 1986 of file bnx2x_hsi.h.

#define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0

Definition at line 1987 of file bnx2x_hsi.h.

#define FUNC_0 0

Definition at line 1102 of file bnx2x_hsi.h.

#define FUNC_1 1

Definition at line 1103 of file bnx2x_hsi.h.

#define FUNC_2 2

Definition at line 1104 of file bnx2x_hsi.h.

#define FUNC_3 3

Definition at line 1105 of file bnx2x_hsi.h.

#define FUNC_4 4

Definition at line 1106 of file bnx2x_hsi.h.

#define FUNC_5 5

Definition at line 1107 of file bnx2x_hsi.h.

#define FUNC_6 6

Definition at line 1108 of file bnx2x_hsi.h.

#define FUNC_7 7

Definition at line 1109 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff

Definition at line 1498 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0

Definition at line 1499 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00

Definition at line 1500 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8

Definition at line 1501 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100

Definition at line 1502 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000

Definition at line 1494 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000

Definition at line 1503 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16

Definition at line 1504 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16

Definition at line 1495 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK

Definition at line 1491 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff

Definition at line 1489 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0

Definition at line 1490 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_FUNC_DELETED 0x00000010

Definition at line 1464 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_FUNC_DISABLED 0x00000008

Definition at line 1463 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_FUNC_HIDE 0x00000001

Definition at line 1453 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff

Definition at line 1486 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000

Definition at line 1479 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_MAX_BW_MASK 0xff000000

Definition at line 1477 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_MAX_BW_SHIFT 24

Definition at line 1478 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000

Definition at line 1476 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000

Definition at line 1474 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_MIN_BW_SHIFT 16

Definition at line 1475 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_PROTOCOL_DEFAULT FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA

Definition at line 1460 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002

Definition at line 1457 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004

Definition at line 1458 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000

Definition at line 1456 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006

Definition at line 1459 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006

Definition at line 1455 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000

Definition at line 1470 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300

Definition at line 1468 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8

Definition at line 1469 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK

Definition at line 1484 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff

Definition at line 1482 of file bnx2x_hsi.h.

#define FUNC_MF_CFG_UPPERMAC_SHIFT 0

Definition at line 1483 of file bnx2x_hsi.h.

#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)

Definition at line 1136 of file bnx2x_hsi.h.

#define FW_ACK_POLL_TIME_MS 1

Definition at line 1134 of file bnx2x_hsi.h.

#define FW_ACK_TIME_OUT_MS 5000

Definition at line 1132 of file bnx2x_hsi.h.

#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e

Definition at line 15 of file bnx2x_hsi.h.

#define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000

Definition at line 1328 of file bnx2x_hsi.h.

#define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000

Definition at line 1329 of file bnx2x_hsi.h.

#define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000

Definition at line 1330 of file bnx2x_hsi.h.

#define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000

Definition at line 1331 of file bnx2x_hsi.h.

#define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000

Definition at line 1332 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DCC_DONE 0x30100000

Definition at line 1307 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000

Definition at line 1309 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000

Definition at line 1311 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DIAG_REFUSE 0x50200000

Definition at line 1310 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000

Definition at line 1334 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000

Definition at line 1335 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000

Definition at line 1294 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000

Definition at line 1299 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000

Definition at line 1302 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000

Definition at line 1296 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000

Definition at line 1295 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000

Definition at line 1301 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000

Definition at line 1303 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000

Definition at line 1306 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000

Definition at line 1305 of file bnx2x_hsi.h.

#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000

Definition at line 1304 of file bnx2x_hsi.h.

#define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000

Definition at line 1337 of file bnx2x_hsi.h.

#define FW_MSG_CODE_GET_KEY_DONE 0x80100000

Definition at line 1314 of file bnx2x_hsi.h.

#define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000

Definition at line 1326 of file bnx2x_hsi.h.

#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000

Definition at line 1319 of file bnx2x_hsi.h.

#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000

Definition at line 1317 of file bnx2x_hsi.h.

#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000

Definition at line 1318 of file bnx2x_hsi.h.

#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000

Definition at line 1321 of file bnx2x_hsi.h.

#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000

Definition at line 1320 of file bnx2x_hsi.h.

#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000

Definition at line 1344 of file bnx2x_hsi.h.

#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000

Definition at line 1316 of file bnx2x_hsi.h.

#define FW_MSG_CODE_LIC_RESPONSE 0xff020000

Definition at line 1345 of file bnx2x_hsi.h.

#define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000

Definition at line 1342 of file bnx2x_hsi.h.

#define FW_MSG_CODE_LLDP_DONE 0x40100000

Definition at line 1308 of file bnx2x_hsi.h.

#define FW_MSG_CODE_MASK 0xffff0000

Definition at line 1293 of file bnx2x_hsi.h.

#define FW_MSG_CODE_NO_KEY 0x80f00000

Definition at line 1315 of file bnx2x_hsi.h.

#define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000

Definition at line 1340 of file bnx2x_hsi.h.

#define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000

Definition at line 1339 of file bnx2x_hsi.h.

#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000

Definition at line 1313 of file bnx2x_hsi.h.

#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000

Definition at line 1312 of file bnx2x_hsi.h.

#define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000

Definition at line 1325 of file bnx2x_hsi.h.

#define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000

Definition at line 1347 of file bnx2x_hsi.h.

#define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000

Definition at line 1346 of file bnx2x_hsi.h.

#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000

Definition at line 1323 of file bnx2x_hsi.h.

#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000

Definition at line 1322 of file bnx2x_hsi.h.

#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000

Definition at line 1324 of file bnx2x_hsi.h.

#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff

Definition at line 1349 of file bnx2x_hsi.h.

#define FW_VERSION_BIG_ENDIEN (0x1<<1)

Definition at line 5010 of file bnx2x_hsi.h.

#define FW_VERSION_BIG_ENDIEN_SHIFT 1

Definition at line 5011 of file bnx2x_hsi.h.

#define FW_VERSION_CHIP_VERSION (0x3<<2)

Definition at line 5012 of file bnx2x_hsi.h.

#define FW_VERSION_CHIP_VERSION_SHIFT 2

Definition at line 5013 of file bnx2x_hsi.h.

#define FW_VERSION_OPTIMIZED (0x1<<0)

Definition at line 5008 of file bnx2x_hsi.h.

#define FW_VERSION_OPTIMIZED_SHIFT 0

Definition at line 5009 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)

Definition at line 3061 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24

Definition at line 3062 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)

Definition at line 3063 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25

Definition at line 3064 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)

Definition at line 3065 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27

Definition at line 3066 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)

Definition at line 3055 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0

Definition at line 3056 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)

Definition at line 3057 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16

Definition at line 3058 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)

Definition at line 3059 of file bnx2x_hsi.h.

#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21

Definition at line 3060 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_ADDRESS (0xFFF<<0)

Definition at line 3121 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_ADDRESS_SHIFT 0

Definition at line 3122 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_FID (0x7F<<12)

Definition at line 3123 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_FID_SHIFT 12

Definition at line 3124 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_RESERVED (0x1<<19)

Definition at line 3125 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_RESERVED_SHIFT 19

Definition at line 3126 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_TYPE (0x1<<20)

Definition at line 3127 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_TYPE_SHIFT 20

Definition at line 3128 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_UNUSED (0x7FF<<21)

Definition at line 3129 of file bnx2x_hsi.h.

#define IGU_CTRL_REG_UNUSED_SHIFT 21

Definition at line 3130 of file bnx2x_hsi.h.

#define IGU_REGULAR_BCLEANUP (0x1<<31)

Definition at line 3092 of file bnx2x_hsi.h.

#define IGU_REGULAR_BCLEANUP_SHIFT 31

Definition at line 3093 of file bnx2x_hsi.h.

#define IGU_REGULAR_BUPDATE (0x1<<24)

Definition at line 3082 of file bnx2x_hsi.h.

#define IGU_REGULAR_BUPDATE_SHIFT 24

Definition at line 3083 of file bnx2x_hsi.h.

#define IGU_REGULAR_CLEANUP_SET (0x1<<30)

Definition at line 3090 of file bnx2x_hsi.h.

#define IGU_REGULAR_CLEANUP_SET_SHIFT 30

Definition at line 3091 of file bnx2x_hsi.h.

#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)

Definition at line 3088 of file bnx2x_hsi.h.

#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28

Definition at line 3089 of file bnx2x_hsi.h.

#define IGU_REGULAR_ENABLE_INT (0x3<<25)

Definition at line 3084 of file bnx2x_hsi.h.

#define IGU_REGULAR_ENABLE_INT_SHIFT 25

Definition at line 3085 of file bnx2x_hsi.h.

#define IGU_REGULAR_RESERVED0 (0x1<<20)

Definition at line 3078 of file bnx2x_hsi.h.

#define IGU_REGULAR_RESERVED0_SHIFT 20

Definition at line 3079 of file bnx2x_hsi.h.

#define IGU_REGULAR_RESERVED_1 (0x1<<27)

Definition at line 3086 of file bnx2x_hsi.h.

#define IGU_REGULAR_RESERVED_1_SHIFT 27

Definition at line 3087 of file bnx2x_hsi.h.

#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)

Definition at line 3076 of file bnx2x_hsi.h.

#define IGU_REGULAR_SB_INDEX_SHIFT 0

Definition at line 3077 of file bnx2x_hsi.h.

#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)

Definition at line 3080 of file bnx2x_hsi.h.

#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21

Definition at line 3081 of file bnx2x_hsi.h.

#define ISCSI_APP_IDX 1

Definition at line 1710 of file bnx2x_hsi.h.

#define LFA_DCC_LFA_DISABLED 0x8

Definition at line 1950 of file bnx2x_hsi.h.

#define LFA_DUPLEX_MISMATCH 0x3

Definition at line 1945 of file bnx2x_hsi.h.

#define LFA_EEE_MISMATCH 0x9

Definition at line 1951 of file bnx2x_hsi.h.

#define LFA_FLAGS_MASK 0xff000000

Definition at line 1959 of file bnx2x_hsi.h.

#define LFA_FLOW_CTRL_MISMATCH 0x6

Definition at line 1948 of file bnx2x_hsi.h.

#define LFA_LINK_DOWN 0x1

Definition at line 1943 of file bnx2x_hsi.h.

#define LFA_LINK_FLAP_REASON_MASK 0x000000ff

Definition at line 1942 of file bnx2x_hsi.h.

#define LFA_LINK_FLAP_REASON_OFFSET 0

Definition at line 1941 of file bnx2x_hsi.h.

#define LFA_LINK_SPEED_MISMATCH 0x5

Definition at line 1947 of file bnx2x_hsi.h.

#define LFA_LOOPBACK_ENABLED 0x2

Definition at line 1944 of file bnx2x_hsi.h.

#define LFA_MFW_IS_TOO_OLD 0x4

Definition at line 1946 of file bnx2x_hsi.h.

#define LFA_SPEED_CAP_MISMATCH 0x7

Definition at line 1949 of file bnx2x_hsi.h.

#define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00

Definition at line 1954 of file bnx2x_hsi.h.

#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8

Definition at line 1953 of file bnx2x_hsi.h.

#define LINK_FLAP_COUNT_MASK 0x00ff0000

Definition at line 1957 of file bnx2x_hsi.h.

#define LINK_FLAP_COUNT_OFFSET 16

Definition at line 1956 of file bnx2x_hsi.h.

#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040

Definition at line 1172 of file bnx2x_hsi.h.

#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020

Definition at line 1170 of file bnx2x_hsi.h.

#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020

Definition at line 1169 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_FLAG_MASK 0x00000001

Definition at line 1149 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200

Definition at line 1176 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400

Definition at line 1177 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800

Definition at line 1178 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000

Definition at line 1179 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000

Definition at line 1180 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000

Definition at line 1200 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000

Definition at line 1181 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000

Definition at line 1182 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000

Definition at line 1201 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000

Definition at line 1198 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000

Definition at line 1199 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)

Definition at line 1193 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)

Definition at line 1194 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000

Definition at line 1190 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)

Definition at line 1191 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)

Definition at line 1192 of file bnx2x_hsi.h.

#define LINK_STATUS_LINK_UP 0x00000001

Definition at line 1150 of file bnx2x_hsi.h.

#define LINK_STATUS_NONE (0<<0)

Definition at line 1148 of file bnx2x_hsi.h.

#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080

Definition at line 1173 of file bnx2x_hsi.h.

#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080

Definition at line 1174 of file bnx2x_hsi.h.

#define LINK_STATUS_PFC_ENABLED 0x20000000

Definition at line 1203 of file bnx2x_hsi.h.

#define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000

Definition at line 1205 of file bnx2x_hsi.h.

#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000

Definition at line 1188 of file bnx2x_hsi.h.

#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000

Definition at line 1187 of file bnx2x_hsi.h.

#define LINK_STATUS_SERDES_LINK 0x00100000

Definition at line 1196 of file bnx2x_hsi.h.

#define LINK_STATUS_SFP_TX_FAULT 0x80000000

Definition at line 1206 of file bnx2x_hsi.h.

#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)

Definition at line 1159 of file bnx2x_hsi.h.

#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)

Definition at line 1158 of file bnx2x_hsi.h.

#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)

Definition at line 1160 of file bnx2x_hsi.h.

#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)

Definition at line 1156 of file bnx2x_hsi.h.

#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)

Definition at line 1157 of file bnx2x_hsi.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation