clkt34xx_dpll3m2.c

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/*
 * OMAP34xx M2 divider clock code
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2010 Nokia Corporation
 *
 * Paul Walmsley
 * Jouni Högander
 *
 * Parts of this code are based on code written by
 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/sdrc.h>

#include "clock.h"
#include "clock3xxx.h"
#include "clock34xx.h"
#include "sdrc.h"

#define CYCLES_PER_MHZ          1000000

/*
 * CORE DPLL (DPLL3) M2 divider rate programming functions
 *
 * These call into SRAM code to do the actual CM writes, since the SDRAM
 * is clocked from DPLL3.
 */

int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{
    u32 new_div = 0;
    u32 unlock_dll = 0;
    u32 c;
    unsigned long validrate, sdrcrate, _mpurate;
    struct omap_sdrc_params *sdrc_cs0;
    struct omap_sdrc_params *sdrc_cs1;
    int ret;
    unsigned long clkrate;

    if (!clk || !rate)
        return -EINVAL;

    validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
    if (validrate != rate)
        return -EINVAL;

    sdrcrate = __clk_get_rate(sdrc_ick_p);
    clkrate = __clk_get_rate(clk);
    if (rate > clkrate)
        sdrcrate <<= ((rate / clkrate) >> 1);
    else
        sdrcrate >>= ((clkrate / rate) >> 1);

    ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
    if (ret)
        return -EINVAL;

    if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
        pr_debug("clock: will unlock SDRC DLL\n");
        unlock_dll = 1;
    }

    /*
     * XXX This only needs to be done when the CPU frequency changes
     */
    _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
    c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
    c += 1;  /* for safety */
    c *= SDRC_MPURATE_LOOPS;
    c >>= SDRC_MPURATE_SCALE;
    if (c == 0)
        c = 1;

    pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
         clkrate, validrate);
    pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
         sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
         sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
    if (sdrc_cs1)
        pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
             sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
             sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);

    if (sdrc_cs1)
        omap3_configure_core_dpll(
                  new_div, unlock_dll, c, rate > clkrate,
                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
    else
        omap3_configure_core_dpll(
                  new_div, unlock_dll, c, rate > clkrate,
                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                  0, 0, 0, 0);
    clk->rate = rate;

    return 0;
}