|
| #define | WAKEUP_CHARS 256 |
| |
| #define | SERIAL_HANDLE_EARLY_ERRORS |
| |
| #define | SERIAL_DESCR_BUF_SIZE 256 |
| |
| #define | SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */ |
| |
| #define | DEF_BAUD_BASE SERIAL_PRESCALE_BASE |
| |
| #define | MIN_FLUSH_TIME_USEC 250 |
| |
| #define | TIMERD(x) |
| |
| #define | DINTR1(x) /* irq on/off, errors */ |
| |
| #define | DINTR2(x) /* tx and rx */ |
| |
| #define | DFLIP(x) |
| |
| #define | DFLOW(x) |
| |
| #define | DBAUD(x) |
| |
| #define | DLOG_INT_TRIG(x) |
| |
| #define | DEBUG_LOG(line, string, value) |
| |
| #define | CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5 |
| |
| #define | DEF_BAUD 115200 /* 115.2 kbit/s */ |
| |
| #define | STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) |
| |
| #define | DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */ |
| |
| #define | DEF_TX 0x80 /* or SERIAL_CTRL_B */ |
| |
| #define | REG_DATA 0 |
| |
| #define | REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */ |
| |
| #define | REG_TR_DATA 0 |
| |
| #define | REG_STATUS 1 |
| |
| #define | REG_TR_CTRL 1 |
| |
| #define | REG_REC_CTRL 2 |
| |
| #define | REG_BAUD 3 |
| |
| #define | REG_XOFF 4 /* this is a 32 bit register */ |
| |
| #define | SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd) |
| |
| #define | SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail) |
| |
| #define | SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err) |
| |
| #define | SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err) |
| |
| #define | SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun) |
| |
| #define | SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK) |
| |
| #define | ERRCODE_SET_BREAK (TTY_BREAK) |
| |
| #define | ERRCODE_INSERT 0x100 |
| |
| #define | ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK) |
| |
| #define | FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop; |
| |
| #define | NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial)) |
| |
| #define | PROCSTAT(x) |
| |
| #define | E100_STRUCT_PORT(line, pinname) |
| |
| #define | E100_STRUCT_SHADOW(line, pinname) |
| |
| #define | E100_STRUCT_MASK(line, pinname) |
| |
| #define | DUMMY_DTR_MASK 1 |
| |
| #define | DUMMY_RI_MASK 2 |
| |
| #define | DUMMY_DSR_MASK 4 |
| |
| #define | DUMMY_CD_MASK 8 |
| |
| #define | CONTROL_PINS_PORT_NOT_USED(line) |
| |
| #define | dtr_port port |
| |
| #define | dtr_shadow shadow |
| |
| #define | ri_port port |
| |
| #define | ri_shadow shadow |
| |
| #define | dsr_port port |
| |
| #define | dsr_shadow shadow |
| |
| #define | cd_port port |
| |
| #define | cd_shadow shadow |
| |
| #define | E100_RTS_MASK 0x20 |
| |
| #define | E100_CTS_MASK 0x40 |
| |
| #define | E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK) |
| |
| #define | E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK) |
| |
| #define | E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask) |
| |
| #define | E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask) |
| |
| #define | E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask) |
| |
| #define | E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask) |
| |
| #define | START_FLUSH_FAST_TIMER_TIME(info, string, usec) |
| |
| #define | START_FLUSH_FAST_TIMER(info, string) |
| |
1.8.2