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#define | pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#define | DRV_NAME "dmfe" |
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#define | DRV_VERSION "1.36.4" |
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#define | DRV_RELDATE "2002-01-17" |
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#define | PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */ |
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#define | PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */ |
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#define | PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */ |
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#define | PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */ |
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#define | DM9102_IO_SIZE 0x80 |
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#define | DM9102A_IO_SIZE 0x100 |
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#define | TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */ |
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#define | TX_DESC_CNT 0x10 /* Allocated Tx descriptors */ |
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#define | RX_DESC_CNT 0x20 /* Allocated Rx descriptors */ |
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#define | TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ |
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#define | TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ |
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#define | DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) |
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#define | TX_BUF_ALLOC 0x600 |
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#define | RX_ALLOC_SIZE 0x620 |
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#define | DM910X_RESET 1 |
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#define | CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */ |
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#define | CR6_DEFAULT 0x00080000 /* HD */ |
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#define | CR7_DEFAULT 0x180c1 |
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#define | CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ |
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#define | TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ |
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#define | MAX_PACKET_SIZE 1514 |
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#define | DMFE_MAX_MULTICAST 14 |
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#define | RX_COPY_SIZE 100 |
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#define | MAX_CHECK_PACKET 0x8000 |
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#define | DM9801_NOISE_FLOOR 8 |
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#define | DM9802_NOISE_FLOOR 5 |
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#define | DMFE_WOL_LINKCHANGE 0x20000000 |
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#define | DMFE_WOL_SAMPLEPACKET 0x10000000 |
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#define | DMFE_WOL_MAGICPACKET 0x08000000 |
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#define | DMFE_10MHF 0 |
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#define | DMFE_100MHF 1 |
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#define | DMFE_10MFD 4 |
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#define | DMFE_100MFD 5 |
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#define | DMFE_AUTO 8 |
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#define | DMFE_1M_HPNA 0x10 |
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#define | DMFE_TXTH_72 0x400000 /* TX TH 72 byte */ |
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#define | DMFE_TXTH_96 0x404000 /* TX TH 96 byte */ |
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#define | DMFE_TXTH_128 0x0000 /* TX TH 128 byte */ |
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#define | DMFE_TXTH_256 0x4000 /* TX TH 256 byte */ |
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#define | DMFE_TXTH_512 0x8000 /* TX TH 512 byte */ |
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#define | DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */ |
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#define | DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */ |
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#define | DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */ |
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#define | DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */ |
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#define | dw32(reg, val) iowrite32(val, ioaddr + (reg)) |
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#define | dw16(reg, val) iowrite16(val, ioaddr + (reg)) |
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#define | dr32(reg) ioread32(ioaddr + (reg)) |
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#define | dr16(reg) ioread16(ioaddr + (reg)) |
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#define | dr8(reg) ioread8(ioaddr + (reg)) |
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#define | DMFE_DBUG(dbug_now, msg, value) |
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#define | SHOW_MEDIA_TYPE(mode) |
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#define | CR9_SROM_READ 0x4800 |
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#define | CR9_SRCS 0x1 |
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#define | CR9_SRCLK 0x2 |
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#define | CR9_CRDOUT 0x8 |
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#define | SROM_DATA_0 0x0 |
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#define | SROM_DATA_1 0x4 |
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#define | PHY_DATA_1 0x20000 |
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#define | PHY_DATA_0 0x00000 |
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#define | MDCLKH 0x10000 |
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#define | PHY_POWER_DOWN 0x800 |
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#define | SROM_V41_CODE 0x14 |
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#define | __CHK_IO_SIZE(pci_id, dev_rev) |
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#define | CHK_IO_SIZE(pci_dev) |
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#define | DEVICE net_device |
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#define | dmfe_suspend NULL |
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#define | dmfe_resume NULL |
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struct tx_desc | __attribute__ ((aligned(32))) |
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| MODULE_DEVICE_TABLE (pci, dmfe_pci_tbl) |
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| MODULE_AUTHOR ("Sten Wang, [email protected]") |
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| MODULE_DESCRIPTION ("Davicom DM910X fast ethernet driver") |
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| MODULE_LICENSE ("GPL") |
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| MODULE_VERSION (DRV_VERSION) |
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| module_param (debug, int, 0) |
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| module_param (mode, byte, 0) |
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| module_param (cr6set, int, 0) |
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| module_param (chkmode, byte, 0) |
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| module_param (HPNA_mode, byte, 0) |
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| module_param (HPNA_rx_cmd, byte, 0) |
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| module_param (HPNA_tx_cmd, byte, 0) |
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| module_param (HPNA_NoiseFloor, byte, 0) |
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| module_param (SF_mode, byte, 0) |
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| MODULE_PARM_DESC (debug,"Davicom DM9xxx enable debugging (0-1)") |
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| MODULE_PARM_DESC (mode,"Davicom DM9xxx: ""Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA") |
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| MODULE_PARM_DESC (SF_mode,"Davicom DM9xxx special function ""(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)") |
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| module_init (dmfe_init_module) |
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| module_exit (dmfe_cleanup_module) |
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