Linux Kernel  3.7.1
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main.c
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1 /*
2  * This file is part of wl1271
3  *
4  * Copyright (C) 2008-2010 Nokia Corporation
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18  * 02110-1301 USA
19  *
20  */
21 
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 
25 #include <linux/err.h>
26 
27 #include <linux/wl12xx.h>
28 
29 #include "../wlcore/wlcore.h"
30 #include "../wlcore/debug.h"
31 #include "../wlcore/io.h"
32 #include "../wlcore/acx.h"
33 #include "../wlcore/tx.h"
34 #include "../wlcore/rx.h"
35 #include "../wlcore/boot.h"
36 
37 #include "wl12xx.h"
38 #include "reg.h"
39 #include "cmd.h"
40 #include "acx.h"
41 #include "debugfs.h"
42 
43 static char *fref_param;
44 static char *tcxo_param;
45 
46 static struct wlcore_conf wl12xx_conf = {
47  .sg = {
48  .params = {
49  [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
50  [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
51  [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
52  [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
53  [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
54  [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
55  [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
56  [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
57  [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
58  [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
59  [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
60  [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
61  [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
62  [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
63  [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
64  [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
65  [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
66  [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
67  [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
68  [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
69  [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
70  [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
71  [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
72  [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
73  [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
74  [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
75  /* active scan params */
76  [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
77  [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
78  [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
79  /* passive scan params */
80  [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
81  [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
82  [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
83  /* passive scan in dual antenna params */
84  [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
85  [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
86  [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
87  /* general params */
88  [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
89  [CONF_SG_ANTENNA_CONFIGURATION] = 0,
90  [CONF_SG_BEACON_MISS_PERCENT] = 60,
91  [CONF_SG_DHCP_TIME] = 5000,
92  [CONF_SG_RXT] = 1200,
93  [CONF_SG_TXT] = 1000,
94  [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
95  [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
96  [CONF_SG_HV3_MAX_SERVED] = 6,
97  [CONF_SG_PS_POLL_TIMEOUT] = 10,
98  [CONF_SG_UPSD_TIMEOUT] = 10,
99  [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
100  [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
101  [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
102  /* AP params */
103  [CONF_AP_BEACON_MISS_TX] = 3,
104  [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
105  [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
106  [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
107  [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
108  [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
109  /* CTS Diluting params */
110  [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
111  [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
112  },
113  .state = CONF_SG_PROTECTIVE,
114  },
115  .rx = {
116  .rx_msdu_life_time = 512000,
117  .packet_detection_threshold = 0,
118  .ps_poll_timeout = 15,
119  .upsd_timeout = 15,
120  .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
121  .rx_cca_threshold = 0,
122  .irq_blk_threshold = 0xFFFF,
123  .irq_pkt_threshold = 0,
124  .irq_timeout = 600,
125  .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
126  },
127  .tx = {
128  .tx_energy_detection = 0,
129  .sta_rc_conf = {
130  .enabled_rates = 0,
131  .short_retry_limit = 10,
132  .long_retry_limit = 10,
133  .aflags = 0,
134  },
135  .ac_conf_count = 4,
136  .ac_conf = {
137  [CONF_TX_AC_BE] = {
138  .ac = CONF_TX_AC_BE,
139  .cw_min = 15,
140  .cw_max = 63,
141  .aifsn = 3,
142  .tx_op_limit = 0,
143  },
144  [CONF_TX_AC_BK] = {
145  .ac = CONF_TX_AC_BK,
146  .cw_min = 15,
147  .cw_max = 63,
148  .aifsn = 7,
149  .tx_op_limit = 0,
150  },
151  [CONF_TX_AC_VI] = {
152  .ac = CONF_TX_AC_VI,
153  .cw_min = 15,
154  .cw_max = 63,
155  .aifsn = CONF_TX_AIFS_PIFS,
156  .tx_op_limit = 3008,
157  },
158  [CONF_TX_AC_VO] = {
159  .ac = CONF_TX_AC_VO,
160  .cw_min = 15,
161  .cw_max = 63,
162  .aifsn = CONF_TX_AIFS_PIFS,
163  .tx_op_limit = 1504,
164  },
165  },
166  .max_tx_retries = 100,
167  .ap_aging_period = 300,
168  .tid_conf_count = 4,
169  .tid_conf = {
170  [CONF_TX_AC_BE] = {
171  .queue_id = CONF_TX_AC_BE,
172  .channel_type = CONF_CHANNEL_TYPE_EDCF,
173  .tsid = CONF_TX_AC_BE,
174  .ps_scheme = CONF_PS_SCHEME_LEGACY,
175  .ack_policy = CONF_ACK_POLICY_LEGACY,
176  .apsd_conf = {0, 0},
177  },
178  [CONF_TX_AC_BK] = {
179  .queue_id = CONF_TX_AC_BK,
180  .channel_type = CONF_CHANNEL_TYPE_EDCF,
181  .tsid = CONF_TX_AC_BK,
182  .ps_scheme = CONF_PS_SCHEME_LEGACY,
183  .ack_policy = CONF_ACK_POLICY_LEGACY,
184  .apsd_conf = {0, 0},
185  },
186  [CONF_TX_AC_VI] = {
187  .queue_id = CONF_TX_AC_VI,
188  .channel_type = CONF_CHANNEL_TYPE_EDCF,
189  .tsid = CONF_TX_AC_VI,
190  .ps_scheme = CONF_PS_SCHEME_LEGACY,
191  .ack_policy = CONF_ACK_POLICY_LEGACY,
192  .apsd_conf = {0, 0},
193  },
194  [CONF_TX_AC_VO] = {
195  .queue_id = CONF_TX_AC_VO,
196  .channel_type = CONF_CHANNEL_TYPE_EDCF,
197  .tsid = CONF_TX_AC_VO,
198  .ps_scheme = CONF_PS_SCHEME_LEGACY,
199  .ack_policy = CONF_ACK_POLICY_LEGACY,
200  .apsd_conf = {0, 0},
201  },
202  },
203  .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
204  .tx_compl_timeout = 700,
205  .tx_compl_threshold = 4,
206  .basic_rate = CONF_HW_BIT_RATE_1MBPS,
207  .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
208  .tmpl_short_retry_limit = 10,
209  .tmpl_long_retry_limit = 10,
210  .tx_watchdog_timeout = 5000,
211  },
212  .conn = {
213  .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
214  .listen_interval = 1,
215  .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
216  .suspend_listen_interval = 3,
217  .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
218  .bcn_filt_ie_count = 3,
219  .bcn_filt_ie = {
220  [0] = {
221  .ie = WLAN_EID_CHANNEL_SWITCH,
222  .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
223  },
224  [1] = {
225  .ie = WLAN_EID_HT_OPERATION,
226  .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
227  },
228  [2] = {
229  .ie = WLAN_EID_ERP_INFO,
230  .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
231  },
232  },
233  .synch_fail_thold = 12,
234  .bss_lose_timeout = 400,
235  .beacon_rx_timeout = 10000,
236  .broadcast_timeout = 20000,
237  .rx_broadcast_in_ps = 1,
238  .ps_poll_threshold = 10,
239  .bet_enable = CONF_BET_MODE_ENABLE,
240  .bet_max_consecutive = 50,
241  .psm_entry_retries = 8,
242  .psm_exit_retries = 16,
243  .psm_entry_nullfunc_retries = 3,
244  .dynamic_ps_timeout = 1500,
245  .forced_ps = false,
246  .keep_alive_interval = 55000,
247  .max_listen_interval = 20,
248  .sta_sleep_auth = WL1271_PSM_ILLEGAL,
249  },
250  .itrim = {
251  .enable = false,
252  .timeout = 50000,
253  },
254  .pm_config = {
255  .host_clk_settling_time = 5000,
256  .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
257  },
258  .roam_trigger = {
259  .trigger_pacing = 1,
260  .avg_weight_rssi_beacon = 20,
261  .avg_weight_rssi_data = 10,
262  .avg_weight_snr_beacon = 20,
263  .avg_weight_snr_data = 10,
264  },
265  .scan = {
266  .min_dwell_time_active = 7500,
267  .max_dwell_time_active = 30000,
268  .min_dwell_time_passive = 100000,
269  .max_dwell_time_passive = 100000,
270  .num_probe_reqs = 2,
271  .split_scan_timeout = 50000,
272  },
273  .sched_scan = {
274  /*
275  * Values are in TU/1000 but since sched scan FW command
276  * params are in TUs rounding up may occur.
277  */
278  .base_dwell_time = 7500,
279  .max_dwell_time_delta = 22500,
280  /* based on 250bits per probe @1Mbps */
281  .dwell_time_delta_per_probe = 2000,
282  /* based on 250bits per probe @6Mbps (plus a bit more) */
283  .dwell_time_delta_per_probe_5 = 350,
284  .dwell_time_passive = 100000,
285  .dwell_time_dfs = 150000,
286  .num_probe_reqs = 2,
287  .rssi_threshold = -90,
288  .snr_threshold = 0,
289  },
290  .ht = {
291  .rx_ba_win_size = 8,
292  .tx_ba_win_size = 64,
293  .inactivity_timeout = 10000,
294  .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
295  },
296  /*
297  * Memory config for wl127x chips is given in the
298  * wl12xx_default_priv_conf struct. The below configuration is
299  * for wl128x chips.
300  */
301  .mem = {
302  .num_stations = 1,
303  .ssid_profiles = 1,
304  .rx_block_num = 40,
305  .tx_min_block_num = 40,
306  .dynamic_memory = 1,
307  .min_req_tx_blocks = 45,
308  .min_req_rx_blocks = 22,
309  .tx_min = 27,
310  },
311  .fm_coex = {
312  .enable = true,
313  .swallow_period = 5,
314  .n_divider_fref_set_1 = 0xff, /* default */
315  .n_divider_fref_set_2 = 12,
316  .m_divider_fref_set_1 = 0xffff,
317  .m_divider_fref_set_2 = 148, /* default */
318  .coex_pll_stabilization_time = 0xffffffff, /* default */
319  .ldo_stabilization_time = 0xffff, /* default */
320  .fm_disturbed_band_margin = 0xff, /* default */
321  .swallow_clk_diff = 0xff, /* default */
322  },
323  .rx_streaming = {
324  .duration = 150,
325  .queues = 0x1,
326  .interval = 20,
327  .always = 0,
328  },
329  .fwlog = {
330  .mode = WL12XX_FWLOG_ON_DEMAND,
331  .mem_blocks = 2,
332  .severity = 0,
333  .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
334  .output = WL12XX_FWLOG_OUTPUT_HOST,
335  .threshold = 0,
336  },
337  .rate = {
338  .rate_retry_score = 32000,
339  .per_add = 8192,
340  .per_th1 = 2048,
341  .per_th2 = 4096,
342  .max_per = 8100,
343  .inverse_curiosity_factor = 5,
344  .tx_fail_low_th = 4,
345  .tx_fail_high_th = 10,
346  .per_alpha_shift = 4,
347  .per_add_shift = 13,
348  .per_beta1_shift = 10,
349  .per_beta2_shift = 8,
350  .rate_check_up = 2,
351  .rate_check_down = 12,
352  .rate_retry_policy = {
353  0x00, 0x00, 0x00, 0x00, 0x00,
354  0x00, 0x00, 0x00, 0x00, 0x00,
355  0x00, 0x00, 0x00,
356  },
357  },
358  .hangover = {
359  .recover_time = 0,
360  .hangover_period = 20,
361  .dynamic_mode = 1,
362  .early_termination_mode = 1,
363  .max_period = 20,
364  .min_period = 1,
365  .increase_delta = 1,
366  .decrease_delta = 2,
367  .quiet_time = 4,
368  .increase_time = 1,
369  .window_size = 16,
370  },
371 };
372 
373 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
374  .rf = {
375  .tx_per_channel_power_compensation_2 = {
376  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
377  },
378  .tx_per_channel_power_compensation_5 = {
379  0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
380  0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
381  0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
382  },
383  },
384  .mem_wl127x = {
385  .num_stations = 1,
386  .ssid_profiles = 1,
387  .rx_block_num = 70,
388  .tx_min_block_num = 40,
389  .dynamic_memory = 1,
390  .min_req_tx_blocks = 100,
391  .min_req_rx_blocks = 22,
392  .tx_min = 27,
393  },
394 
395 };
396 
397 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT 1
398 #define WL12XX_TX_HW_BLOCK_GEM_SPARE 2
399 #define WL12XX_TX_HW_BLOCK_SIZE 252
400 
401 static const u8 wl12xx_rate_to_idx_2ghz[] = {
402  /* MCS rates are used only with 11n */
403  7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
404  7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
405  6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
406  5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
407  4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
408  3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
409  2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
410  1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
411  0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
412 
413  11, /* WL12XX_CONF_HW_RXTX_RATE_54 */
414  10, /* WL12XX_CONF_HW_RXTX_RATE_48 */
415  9, /* WL12XX_CONF_HW_RXTX_RATE_36 */
416  8, /* WL12XX_CONF_HW_RXTX_RATE_24 */
417 
418  /* TI-specific rate */
419  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
420 
421  7, /* WL12XX_CONF_HW_RXTX_RATE_18 */
422  6, /* WL12XX_CONF_HW_RXTX_RATE_12 */
423  3, /* WL12XX_CONF_HW_RXTX_RATE_11 */
424  5, /* WL12XX_CONF_HW_RXTX_RATE_9 */
425  4, /* WL12XX_CONF_HW_RXTX_RATE_6 */
426  2, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
427  1, /* WL12XX_CONF_HW_RXTX_RATE_2 */
428  0 /* WL12XX_CONF_HW_RXTX_RATE_1 */
429 };
430 
431 static const u8 wl12xx_rate_to_idx_5ghz[] = {
432  /* MCS rates are used only with 11n */
433  7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
434  7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
435  6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
436  5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
437  4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
438  3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
439  2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
440  1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
441  0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
442 
443  7, /* WL12XX_CONF_HW_RXTX_RATE_54 */
444  6, /* WL12XX_CONF_HW_RXTX_RATE_48 */
445  5, /* WL12XX_CONF_HW_RXTX_RATE_36 */
446  4, /* WL12XX_CONF_HW_RXTX_RATE_24 */
447 
448  /* TI-specific rate */
449  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
450 
451  3, /* WL12XX_CONF_HW_RXTX_RATE_18 */
452  2, /* WL12XX_CONF_HW_RXTX_RATE_12 */
453  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11 */
454  1, /* WL12XX_CONF_HW_RXTX_RATE_9 */
455  0, /* WL12XX_CONF_HW_RXTX_RATE_6 */
456  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
457  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2 */
458  CONF_HW_RXTX_RATE_UNSUPPORTED /* WL12XX_CONF_HW_RXTX_RATE_1 */
459 };
460 
461 static const u8 *wl12xx_band_rate_to_idx[] = {
462  [IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
463  [IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
464 };
465 
466 enum wl12xx_hw_rates {
467  WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
468  WL12XX_CONF_HW_RXTX_RATE_MCS7,
469  WL12XX_CONF_HW_RXTX_RATE_MCS6,
470  WL12XX_CONF_HW_RXTX_RATE_MCS5,
471  WL12XX_CONF_HW_RXTX_RATE_MCS4,
472  WL12XX_CONF_HW_RXTX_RATE_MCS3,
473  WL12XX_CONF_HW_RXTX_RATE_MCS2,
474  WL12XX_CONF_HW_RXTX_RATE_MCS1,
475  WL12XX_CONF_HW_RXTX_RATE_MCS0,
476  WL12XX_CONF_HW_RXTX_RATE_54,
477  WL12XX_CONF_HW_RXTX_RATE_48,
478  WL12XX_CONF_HW_RXTX_RATE_36,
479  WL12XX_CONF_HW_RXTX_RATE_24,
480  WL12XX_CONF_HW_RXTX_RATE_22,
481  WL12XX_CONF_HW_RXTX_RATE_18,
482  WL12XX_CONF_HW_RXTX_RATE_12,
483  WL12XX_CONF_HW_RXTX_RATE_11,
484  WL12XX_CONF_HW_RXTX_RATE_9,
485  WL12XX_CONF_HW_RXTX_RATE_6,
486  WL12XX_CONF_HW_RXTX_RATE_5_5,
487  WL12XX_CONF_HW_RXTX_RATE_2,
488  WL12XX_CONF_HW_RXTX_RATE_1,
489  WL12XX_CONF_HW_RXTX_RATE_MAX,
490 };
491 
492 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
493  [PART_DOWN] = {
494  .mem = {
495  .start = 0x00000000,
496  .size = 0x000177c0
497  },
498  .reg = {
499  .start = REGISTERS_BASE,
500  .size = 0x00008800
501  },
502  .mem2 = {
503  .start = 0x00000000,
504  .size = 0x00000000
505  },
506  .mem3 = {
507  .start = 0x00000000,
508  .size = 0x00000000
509  },
510  },
511 
512  [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
513  * partition here */
514  .mem = {
515  .start = 0x00040000,
516  .size = 0x00014fc0
517  },
518  .reg = {
519  .start = REGISTERS_BASE,
520  .size = 0x00008800
521  },
522  .mem2 = {
523  .start = 0x00000000,
524  .size = 0x00000000
525  },
526  .mem3 = {
527  .start = 0x00000000,
528  .size = 0x00000000
529  },
530  },
531 
532  [PART_WORK] = {
533  .mem = {
534  .start = 0x00040000,
535  .size = 0x00014fc0
536  },
537  .reg = {
538  .start = REGISTERS_BASE,
539  .size = 0x0000a000
540  },
541  .mem2 = {
542  .start = 0x003004f8,
543  .size = 0x00000004
544  },
545  .mem3 = {
546  .start = 0x00040404,
547  .size = 0x00000000
548  },
549  },
550 
551  [PART_DRPW] = {
552  .mem = {
553  .start = 0x00040000,
554  .size = 0x00014fc0
555  },
556  .reg = {
557  .start = DRPW_BASE,
558  .size = 0x00006000
559  },
560  .mem2 = {
561  .start = 0x00000000,
562  .size = 0x00000000
563  },
564  .mem3 = {
565  .start = 0x00000000,
566  .size = 0x00000000
567  }
568  }
569 };
570 
571 static const int wl12xx_rtable[REG_TABLE_LEN] = {
572  [REG_ECPU_CONTROL] = WL12XX_REG_ECPU_CONTROL,
573  [REG_INTERRUPT_NO_CLEAR] = WL12XX_REG_INTERRUPT_NO_CLEAR,
574  [REG_INTERRUPT_ACK] = WL12XX_REG_INTERRUPT_ACK,
575  [REG_COMMAND_MAILBOX_PTR] = WL12XX_REG_COMMAND_MAILBOX_PTR,
576  [REG_EVENT_MAILBOX_PTR] = WL12XX_REG_EVENT_MAILBOX_PTR,
577  [REG_INTERRUPT_TRIG] = WL12XX_REG_INTERRUPT_TRIG,
578  [REG_INTERRUPT_MASK] = WL12XX_REG_INTERRUPT_MASK,
579  [REG_PC_ON_RECOVERY] = WL12XX_SCR_PAD4,
580  [REG_CHIP_ID_B] = WL12XX_CHIP_ID_B,
581  [REG_CMD_MBOX_ADDRESS] = WL12XX_CMD_MBOX_ADDRESS,
582 
583  /* data access memory addresses, used with partition translation */
584  [REG_SLV_MEM_DATA] = WL1271_SLV_MEM_DATA,
585  [REG_SLV_REG_DATA] = WL1271_SLV_REG_DATA,
586 
587  /* raw data access memory addresses */
588  [REG_RAW_FW_STATUS_ADDR] = FW_STATUS_ADDR,
589 };
590 
591 /* TODO: maybe move to a new header file? */
592 #define WL127X_FW_NAME_MULTI "ti-connectivity/wl127x-fw-5-mr.bin"
593 #define WL127X_FW_NAME_SINGLE "ti-connectivity/wl127x-fw-5-sr.bin"
594 #define WL127X_PLT_FW_NAME "ti-connectivity/wl127x-fw-5-plt.bin"
595 
596 #define WL128X_FW_NAME_MULTI "ti-connectivity/wl128x-fw-5-mr.bin"
597 #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-5-sr.bin"
598 #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-5-plt.bin"
599 
600 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
601 {
602  int ret;
603 
604  if (wl->chip.id != CHIP_ID_1283_PG20) {
605  struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
606  struct wl127x_rx_mem_pool_addr rx_mem_addr;
607 
608  /*
609  * Choose the block we want to read
610  * For aggregated packets, only the first memory block
611  * should be retrieved. The FW takes care of the rest.
612  */
613  u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
614 
615  rx_mem_addr.addr = (mem_block << 8) +
616  le32_to_cpu(wl_mem_map->packet_memory_pool_start);
617 
618  rx_mem_addr.addr_extra = rx_mem_addr.addr + 4;
619 
620  ret = wlcore_write(wl, WL1271_SLV_REG_DATA, &rx_mem_addr,
621  sizeof(rx_mem_addr), false);
622  if (ret < 0)
623  return ret;
624  }
625 
626  return 0;
627 }
628 
629 static int wl12xx_identify_chip(struct wl1271 *wl)
630 {
631  int ret = 0;
632 
633  switch (wl->chip.id) {
634  case CHIP_ID_1271_PG10:
635  wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
636  wl->chip.id);
637 
638  wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
639  WLCORE_QUIRK_DUAL_PROBE_TMPL |
640  WLCORE_QUIRK_TKIP_HEADER_SPACE;
641  wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
642  wl->mr_fw_name = WL127X_FW_NAME_MULTI;
643  memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
644  sizeof(wl->conf.mem));
645 
646  /* read data preparation is only needed by wl127x */
647  wl->ops->prepare_read = wl127x_prepare_read;
648 
649  wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
650  WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
651  WL127X_MINOR_VER);
652  break;
653 
654  case CHIP_ID_1271_PG20:
655  wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
656  wl->chip.id);
657 
658  wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
659  WLCORE_QUIRK_DUAL_PROBE_TMPL |
660  WLCORE_QUIRK_TKIP_HEADER_SPACE;
661  wl->plt_fw_name = WL127X_PLT_FW_NAME;
662  wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
663  wl->mr_fw_name = WL127X_FW_NAME_MULTI;
664  memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
665  sizeof(wl->conf.mem));
666 
667  /* read data preparation is only needed by wl127x */
668  wl->ops->prepare_read = wl127x_prepare_read;
669 
670  wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
671  WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
672  WL127X_MINOR_VER);
673  break;
674 
675  case CHIP_ID_1283_PG20:
676  wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
677  wl->chip.id);
678  wl->plt_fw_name = WL128X_PLT_FW_NAME;
679  wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
680  wl->mr_fw_name = WL128X_FW_NAME_MULTI;
681 
682  /* wl128x requires TX blocksize alignment */
683  wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
684  WLCORE_QUIRK_DUAL_PROBE_TMPL |
685  WLCORE_QUIRK_TKIP_HEADER_SPACE;
686 
687  wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER, WL128X_IFTYPE_VER,
688  WL128X_MAJOR_VER, WL128X_SUBTYPE_VER,
689  WL128X_MINOR_VER);
690  break;
691  case CHIP_ID_1283_PG10:
692  default:
693  wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
694  ret = -ENODEV;
695  goto out;
696  }
697 
698 out:
699  return ret;
700 }
701 
702 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
703  u16 val)
704 {
705  int ret;
706 
707  /* write address >> 1 + 0x30000 to OCP_POR_CTR */
708  addr = (addr >> 1) + 0x30000;
709  ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
710  if (ret < 0)
711  goto out;
712 
713  /* write value to OCP_POR_WDATA */
714  ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
715  if (ret < 0)
716  goto out;
717 
718  /* write 1 to OCP_CMD */
719  ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
720  if (ret < 0)
721  goto out;
722 
723 out:
724  return ret;
725 }
726 
727 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
728  u16 *out)
729 {
730  u32 val;
731  int timeout = OCP_CMD_LOOP;
732  int ret;
733 
734  /* write address >> 1 + 0x30000 to OCP_POR_CTR */
735  addr = (addr >> 1) + 0x30000;
736  ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
737  if (ret < 0)
738  return ret;
739 
740  /* write 2 to OCP_CMD */
741  ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
742  if (ret < 0)
743  return ret;
744 
745  /* poll for data ready */
746  do {
747  ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
748  if (ret < 0)
749  return ret;
750  } while (!(val & OCP_READY_MASK) && --timeout);
751 
752  if (!timeout) {
753  wl1271_warning("Top register access timed out.");
754  return -ETIMEDOUT;
755  }
756 
757  /* check data status and return if OK */
758  if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
759  wl1271_warning("Top register access returned error.");
760  return -EIO;
761  }
762 
763  if (out)
764  *out = val & 0xffff;
765 
766  return 0;
767 }
768 
769 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
770 {
771  u16 spare_reg;
772  int ret;
773 
774  /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
775  ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
776  if (ret < 0)
777  return ret;
778 
779  if (spare_reg == 0xFFFF)
780  return -EFAULT;
781  spare_reg |= (BIT(3) | BIT(5) | BIT(6));
782  ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
783  if (ret < 0)
784  return ret;
785 
786  /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
787  ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
788  WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
789  if (ret < 0)
790  return ret;
791 
792  /* Delay execution for 15msec, to let the HW settle */
793  mdelay(15);
794 
795  return 0;
796 }
797 
798 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
799 {
800  u16 tcxo_detection;
801  int ret;
802 
803  ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
804  if (ret < 0)
805  return false;
806 
807  if (tcxo_detection & TCXO_DET_FAILED)
808  return false;
809 
810  return true;
811 }
812 
813 static bool wl128x_is_fref_valid(struct wl1271 *wl)
814 {
815  u16 fref_detection;
816  int ret;
817 
818  ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
819  if (ret < 0)
820  return false;
821 
822  if (fref_detection & FREF_CLK_DETECT_FAIL)
823  return false;
824 
825  return true;
826 }
827 
828 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
829 {
830  int ret;
831 
832  ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
833  if (ret < 0)
834  goto out;
835 
836  ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
837  if (ret < 0)
838  goto out;
839 
840  ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
841  MCS_PLL_CONFIG_REG_VAL);
842 
843 out:
844  return ret;
845 }
846 
847 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
848 {
849  u16 spare_reg;
850  u16 pll_config;
851  u8 input_freq;
852  struct wl12xx_priv *priv = wl->priv;
853  int ret;
854 
855  /* Mask bits [3:1] in the sys_clk_cfg register */
856  ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
857  if (ret < 0)
858  return ret;
859 
860  if (spare_reg == 0xFFFF)
861  return -EFAULT;
862  spare_reg |= BIT(2);
863  ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
864  if (ret < 0)
865  return ret;
866 
867  /* Handle special cases of the TCXO clock */
868  if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
869  priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
870  return wl128x_manually_configure_mcs_pll(wl);
871 
872  /* Set the input frequency according to the selected clock source */
873  input_freq = (clk & 1) + 1;
874 
875  ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
876  if (ret < 0)
877  return ret;
878 
879  if (pll_config == 0xFFFF)
880  return -EFAULT;
881  pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
882  pll_config |= MCS_PLL_ENABLE_HP;
883  ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
884 
885  return ret;
886 }
887 
888 /*
889  * WL128x has two clocks input - TCXO and FREF.
890  * TCXO is the main clock of the device, while FREF is used to sync
891  * between the GPS and the cellular modem.
892  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
893  * as the WLAN/BT main clock.
894  */
895 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
896 {
897  struct wl12xx_priv *priv = wl->priv;
898  u16 sys_clk_cfg;
899  int ret;
900 
901  /* For XTAL-only modes, FREF will be used after switching from TCXO */
902  if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
903  priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
904  if (!wl128x_switch_tcxo_to_fref(wl))
905  return -EINVAL;
906  goto fref_clk;
907  }
908 
909  /* Query the HW, to determine which clock source we should use */
910  ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
911  if (ret < 0)
912  return ret;
913 
914  if (sys_clk_cfg == 0xFFFF)
915  return -EINVAL;
916  if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
917  goto fref_clk;
918 
919  /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
920  if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
921  priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
922  if (!wl128x_switch_tcxo_to_fref(wl))
923  return -EINVAL;
924  goto fref_clk;
925  }
926 
927  /* TCXO clock is selected */
928  if (!wl128x_is_tcxo_valid(wl))
929  return -EINVAL;
930  *selected_clock = priv->tcxo_clock;
931  goto config_mcs_pll;
932 
933 fref_clk:
934  /* FREF clock is selected */
935  if (!wl128x_is_fref_valid(wl))
936  return -EINVAL;
937  *selected_clock = priv->ref_clock;
938 
939 config_mcs_pll:
940  return wl128x_configure_mcs_pll(wl, *selected_clock);
941 }
942 
943 static int wl127x_boot_clk(struct wl1271 *wl)
944 {
945  struct wl12xx_priv *priv = wl->priv;
946  u32 pause;
947  u32 clk;
948  int ret;
949 
950  if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
951  wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
952 
953  if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
954  priv->ref_clock == CONF_REF_CLK_38_4_E ||
955  priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
956  /* ref clk: 19.2/38.4/38.4-XTAL */
957  clk = 0x3;
958  else if (priv->ref_clock == CONF_REF_CLK_26_E ||
959  priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
960  priv->ref_clock == CONF_REF_CLK_52_E)
961  /* ref clk: 26/52 */
962  clk = 0x5;
963  else
964  return -EINVAL;
965 
966  if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
967  u16 val;
968  /* Set clock type (open drain) */
969  ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
970  if (ret < 0)
971  goto out;
972 
973  val &= FREF_CLK_TYPE_BITS;
974  ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
975  if (ret < 0)
976  goto out;
977 
978  /* Set clock pull mode (no pull) */
979  ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
980  if (ret < 0)
981  goto out;
982 
983  val |= NO_PULL;
984  ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
985  if (ret < 0)
986  goto out;
987  } else {
988  u16 val;
989  /* Set clock polarity */
990  ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
991  if (ret < 0)
992  goto out;
993 
994  val &= FREF_CLK_POLARITY_BITS;
995  val |= CLK_REQ_OUTN_SEL;
996  ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
997  if (ret < 0)
998  goto out;
999  }
1000 
1001  ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1002  if (ret < 0)
1003  goto out;
1004 
1005  ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1006  if (ret < 0)
1007  goto out;
1008 
1009  wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1010 
1011  pause &= ~(WU_COUNTER_PAUSE_VAL);
1012  pause |= WU_COUNTER_PAUSE_VAL;
1013  ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1014 
1015 out:
1016  return ret;
1017 }
1018 
1019 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1020 {
1021  unsigned long timeout;
1022  u32 boot_data;
1023  int ret = 0;
1024 
1025  /* perform soft reset */
1026  ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1027  if (ret < 0)
1028  goto out;
1029 
1030  /* SOFT_RESET is self clearing */
1031  timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1032  while (1) {
1033  ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1034  if (ret < 0)
1035  goto out;
1036 
1037  wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1038  if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1039  break;
1040 
1041  if (time_after(jiffies, timeout)) {
1042  /* 1.2 check pWhalBus->uSelfClearTime if the
1043  * timeout was reached */
1044  wl1271_error("soft reset timeout");
1045  return -1;
1046  }
1047 
1048  udelay(SOFT_RESET_STALL_TIME);
1049  }
1050 
1051  /* disable Rx/Tx */
1052  ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1053  if (ret < 0)
1054  goto out;
1055 
1056  /* disable auto calibration on start*/
1057  ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1058 
1059 out:
1060  return ret;
1061 }
1062 
1063 static int wl12xx_pre_boot(struct wl1271 *wl)
1064 {
1065  struct wl12xx_priv *priv = wl->priv;
1066  int ret = 0;
1067  u32 clk;
1068  int selected_clock = -1;
1069 
1070  if (wl->chip.id == CHIP_ID_1283_PG20) {
1071  ret = wl128x_boot_clk(wl, &selected_clock);
1072  if (ret < 0)
1073  goto out;
1074  } else {
1075  ret = wl127x_boot_clk(wl);
1076  if (ret < 0)
1077  goto out;
1078  }
1079 
1080  /* Continue the ELP wake up sequence */
1081  ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1082  if (ret < 0)
1083  goto out;
1084 
1085  udelay(500);
1086 
1087  ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1088  if (ret < 0)
1089  goto out;
1090 
1091  /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1092  to be used by DRPw FW. The RTRIM value will be added by the FW
1093  before taking DRPw out of reset */
1094 
1095  ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1096  if (ret < 0)
1097  goto out;
1098 
1099  wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1100 
1101  if (wl->chip.id == CHIP_ID_1283_PG20)
1102  clk |= ((selected_clock & 0x3) << 1) << 4;
1103  else
1104  clk |= (priv->ref_clock << 1) << 4;
1105 
1106  ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1107  if (ret < 0)
1108  goto out;
1109 
1110  ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1111  if (ret < 0)
1112  goto out;
1113 
1114  /* Disable interrupts */
1115  ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1116  if (ret < 0)
1117  goto out;
1118 
1119  ret = wl1271_boot_soft_reset(wl);
1120  if (ret < 0)
1121  goto out;
1122 
1123 out:
1124  return ret;
1125 }
1126 
1127 static int wl12xx_pre_upload(struct wl1271 *wl)
1128 {
1129  u32 tmp;
1130  u16 polarity;
1131  int ret;
1132 
1133  /* write firmware's last address (ie. it's length) to
1134  * ACX_EEPROMLESS_IND_REG */
1135  wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1136 
1137  ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1138  if (ret < 0)
1139  goto out;
1140 
1141  ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1142  if (ret < 0)
1143  goto out;
1144 
1145  wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1146 
1147  /* 6. read the EEPROM parameters */
1148  ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1149  if (ret < 0)
1150  goto out;
1151 
1152  /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1153  * to upload_fw) */
1154 
1155  if (wl->chip.id == CHIP_ID_1283_PG20) {
1156  ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1157  if (ret < 0)
1158  goto out;
1159  }
1160 
1161  /* polarity must be set before the firmware is loaded */
1162  ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1163  if (ret < 0)
1164  goto out;
1165 
1166  /* We use HIGH polarity, so unset the LOW bit */
1167  polarity &= ~POLARITY_LOW;
1168  ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1169 
1170 out:
1171  return ret;
1172 }
1173 
1174 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1175 {
1176  int ret;
1177 
1178  ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1179  WL12XX_ACX_ALL_EVENTS_VECTOR);
1180  if (ret < 0)
1181  goto out;
1182 
1183  wlcore_enable_interrupts(wl);
1184  ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1185  WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1186  if (ret < 0)
1187  goto disable_interrupts;
1188 
1189  ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1190  if (ret < 0)
1191  goto disable_interrupts;
1192 
1193  return ret;
1194 
1195 disable_interrupts:
1196  wlcore_disable_interrupts(wl);
1197 
1198 out:
1199  return ret;
1200 }
1201 
1202 static int wl12xx_boot(struct wl1271 *wl)
1203 {
1204  int ret;
1205 
1206  ret = wl12xx_pre_boot(wl);
1207  if (ret < 0)
1208  goto out;
1209 
1210  ret = wlcore_boot_upload_nvs(wl);
1211  if (ret < 0)
1212  goto out;
1213 
1214  ret = wl12xx_pre_upload(wl);
1215  if (ret < 0)
1216  goto out;
1217 
1218  ret = wlcore_boot_upload_firmware(wl);
1219  if (ret < 0)
1220  goto out;
1221 
1222  ret = wlcore_boot_run_firmware(wl);
1223  if (ret < 0)
1224  goto out;
1225 
1226  ret = wl12xx_enable_interrupts(wl);
1227 
1228 out:
1229  return ret;
1230 }
1231 
1232 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1233  void *buf, size_t len)
1234 {
1235  int ret;
1236 
1237  ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1238  if (ret < 0)
1239  return ret;
1240 
1241  ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1242 
1243  return ret;
1244 }
1245 
1246 static int wl12xx_ack_event(struct wl1271 *wl)
1247 {
1248  return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1249  WL12XX_INTR_TRIG_EVENT_ACK);
1250 }
1251 
1252 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1253 {
1254  u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1255  u32 align_len = wlcore_calc_packet_alignment(wl, len);
1256 
1257  return (align_len + blk_size - 1) / blk_size + spare_blks;
1258 }
1259 
1260 static void
1261 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1262  u32 blks, u32 spare_blks)
1263 {
1264  if (wl->chip.id == CHIP_ID_1283_PG20) {
1265  desc->wl128x_mem.total_mem_blocks = blks;
1266  } else {
1267  desc->wl127x_mem.extra_blocks = spare_blks;
1268  desc->wl127x_mem.total_mem_blocks = blks;
1269  }
1270 }
1271 
1272 static void
1273 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1274  struct sk_buff *skb)
1275 {
1276  u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1277 
1278  if (wl->chip.id == CHIP_ID_1283_PG20) {
1279  desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1280  desc->length = cpu_to_le16(aligned_len >> 2);
1281 
1282  wl1271_debug(DEBUG_TX,
1283  "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1284  desc->hlid,
1285  le16_to_cpu(desc->length),
1286  le16_to_cpu(desc->life_time),
1287  desc->wl128x_mem.total_mem_blocks,
1288  desc->wl128x_mem.extra_bytes);
1289  } else {
1290  /* calculate number of padding bytes */
1291  int pad = aligned_len - skb->len;
1292  desc->tx_attr |=
1293  cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1294 
1295  /* Store the aligned length in terms of words */
1296  desc->length = cpu_to_le16(aligned_len >> 2);
1297 
1298  wl1271_debug(DEBUG_TX,
1299  "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1300  pad, desc->hlid,
1301  le16_to_cpu(desc->length),
1302  le16_to_cpu(desc->life_time),
1303  desc->wl127x_mem.total_mem_blocks);
1304  }
1305 }
1306 
1307 static enum wl_rx_buf_align
1308 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1309 {
1310  if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1311  return WLCORE_RX_BUF_UNALIGNED;
1312 
1313  return WLCORE_RX_BUF_ALIGNED;
1314 }
1315 
1316 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1317  u32 data_len)
1318 {
1319  struct wl1271_rx_descriptor *desc = rx_data;
1320 
1321  /* invalid packet */
1322  if (data_len < sizeof(*desc) ||
1323  data_len < sizeof(*desc) + desc->pad_len)
1324  return 0;
1325 
1326  return data_len - sizeof(*desc) - desc->pad_len;
1327 }
1328 
1329 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1330 {
1331  if (wl->fw_status_1->tx_results_counter ==
1332  (wl->tx_results_count & 0xff))
1333  return 0;
1334 
1335  return wlcore_tx_complete(wl);
1336 }
1337 
1338 static int wl12xx_hw_init(struct wl1271 *wl)
1339 {
1340  int ret;
1341 
1342  if (wl->chip.id == CHIP_ID_1283_PG20) {
1343  u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1344 
1345  ret = wl128x_cmd_general_parms(wl);
1346  if (ret < 0)
1347  goto out;
1348 
1349  /*
1350  * If we are in calibrator based auto detect then we got the FEM nr
1351  * in wl->fem_manuf. No need to continue further
1352  */
1353  if (wl->plt_mode == PLT_FEM_DETECT)
1354  goto out;
1355 
1356  ret = wl128x_cmd_radio_parms(wl);
1357  if (ret < 0)
1358  goto out;
1359 
1360  if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1361  /* Enable SDIO padding */
1362  host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1363 
1364  /* Must be before wl1271_acx_init_mem_config() */
1365  ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1366  if (ret < 0)
1367  goto out;
1368  } else {
1369  ret = wl1271_cmd_general_parms(wl);
1370  if (ret < 0)
1371  goto out;
1372 
1373  /*
1374  * If we are in calibrator based auto detect then we got the FEM nr
1375  * in wl->fem_manuf. No need to continue further
1376  */
1377  if (wl->plt_mode == PLT_FEM_DETECT)
1378  goto out;
1379 
1380  ret = wl1271_cmd_radio_parms(wl);
1381  if (ret < 0)
1382  goto out;
1383  ret = wl1271_cmd_ext_radio_parms(wl);
1384  if (ret < 0)
1385  goto out;
1386  }
1387 out:
1388  return ret;
1389 }
1390 
1391 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1392  struct wl12xx_vif *wlvif)
1393 {
1394  return wlvif->rate_set;
1395 }
1396 
1397 static int wl12xx_identify_fw(struct wl1271 *wl)
1398 {
1399  unsigned int *fw_ver = wl->chip.fw_ver;
1400 
1401  /* Only new station firmwares support routing fw logs to the host */
1402  if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
1403  (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
1404  wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1405 
1406  /* This feature is not yet supported for AP mode */
1407  if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
1408  wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1409 
1410  return 0;
1411 }
1412 
1413 static void wl12xx_conf_init(struct wl1271 *wl)
1414 {
1415  struct wl12xx_priv *priv = wl->priv;
1416 
1417  /* apply driver default configuration */
1418  memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1419 
1420  /* apply default private configuration */
1421  memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1422 }
1423 
1424 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1425 {
1426  bool supported = false;
1427  u8 major, minor;
1428 
1429  if (wl->chip.id == CHIP_ID_1283_PG20) {
1430  major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1431  minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1432 
1433  /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1434  if (major > 2 || (major == 2 && minor >= 1))
1435  supported = true;
1436  } else {
1437  major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1438  minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1439 
1440  /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1441  if (major == 3 && minor >= 1)
1442  supported = true;
1443  }
1444 
1445  wl1271_debug(DEBUG_PROBE,
1446  "PG Ver major = %d minor = %d, MAC %s present",
1447  major, minor, supported ? "is" : "is not");
1448 
1449  return supported;
1450 }
1451 
1452 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1453 {
1454  u32 mac1, mac2;
1455  int ret;
1456 
1457  ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1458  if (ret < 0)
1459  goto out;
1460 
1461  ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1462  if (ret < 0)
1463  goto out;
1464 
1465  ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1466  if (ret < 0)
1467  goto out;
1468 
1469  /* these are the two parts of the BD_ADDR */
1470  wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1471  ((mac1 & 0xff000000) >> 24);
1472  wl->fuse_nic_addr = mac1 & 0xffffff;
1473 
1474  ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1475 
1476 out:
1477  return ret;
1478 }
1479 
1480 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1481 {
1482  u16 die_info;
1483  int ret;
1484 
1485  if (wl->chip.id == CHIP_ID_1283_PG20)
1486  ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1487  &die_info);
1488  else
1489  ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1490  &die_info);
1491 
1492  if (ret >= 0 && ver)
1493  *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1494 
1495  return ret;
1496 }
1497 
1498 static int wl12xx_get_mac(struct wl1271 *wl)
1499 {
1500  if (wl12xx_mac_in_fuse(wl))
1501  return wl12xx_get_fuse_mac(wl);
1502 
1503  return 0;
1504 }
1505 
1506 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1507  struct wl1271_tx_hw_descr *desc,
1508  struct sk_buff *skb)
1509 {
1510  desc->wl12xx_reserved = 0;
1511 }
1512 
1513 static int wl12xx_plt_init(struct wl1271 *wl)
1514 {
1515  int ret;
1516 
1517  ret = wl->ops->boot(wl);
1518  if (ret < 0)
1519  goto out;
1520 
1521  ret = wl->ops->hw_init(wl);
1522  if (ret < 0)
1523  goto out_irq_disable;
1524 
1525  /*
1526  * If we are in calibrator based auto detect then we got the FEM nr
1527  * in wl->fem_manuf. No need to continue further
1528  */
1529  if (wl->plt_mode == PLT_FEM_DETECT)
1530  goto out;
1531 
1532  ret = wl1271_acx_init_mem_config(wl);
1533  if (ret < 0)
1534  goto out_irq_disable;
1535 
1536  ret = wl12xx_acx_mem_cfg(wl);
1537  if (ret < 0)
1538  goto out_free_memmap;
1539 
1540  /* Enable data path */
1541  ret = wl1271_cmd_data_path(wl, 1);
1542  if (ret < 0)
1543  goto out_free_memmap;
1544 
1545  /* Configure for CAM power saving (ie. always active) */
1546  ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1547  if (ret < 0)
1548  goto out_free_memmap;
1549 
1550  /* configure PM */
1551  ret = wl1271_acx_pm_config(wl);
1552  if (ret < 0)
1553  goto out_free_memmap;
1554 
1555  goto out;
1556 
1557 out_free_memmap:
1558  kfree(wl->target_mem_map);
1559  wl->target_mem_map = NULL;
1560 
1561 out_irq_disable:
1562  mutex_unlock(&wl->mutex);
1563  /* Unlocking the mutex in the middle of handling is
1564  inherently unsafe. In this case we deem it safe to do,
1565  because we need to let any possibly pending IRQ out of
1566  the system (and while we are WL1271_STATE_OFF the IRQ
1567  work function will not do anything.) Also, any other
1568  possible concurrent operations will fail due to the
1569  current state, hence the wl1271 struct should be safe. */
1570  wlcore_disable_interrupts(wl);
1571  mutex_lock(&wl->mutex);
1572 out:
1573  return ret;
1574 }
1575 
1576 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1577 {
1578  if (is_gem)
1579  return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1580 
1581  return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1582 }
1583 
1584 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1585  struct ieee80211_vif *vif,
1586  struct ieee80211_sta *sta,
1587  struct ieee80211_key_conf *key_conf)
1588 {
1589  return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1590 }
1591 
1592 static int wl12xx_setup(struct wl1271 *wl);
1593 
1594 static struct wlcore_ops wl12xx_ops = {
1595  .setup = wl12xx_setup,
1596  .identify_chip = wl12xx_identify_chip,
1597  .identify_fw = wl12xx_identify_fw,
1598  .boot = wl12xx_boot,
1599  .plt_init = wl12xx_plt_init,
1600  .trigger_cmd = wl12xx_trigger_cmd,
1601  .ack_event = wl12xx_ack_event,
1602  .calc_tx_blocks = wl12xx_calc_tx_blocks,
1603  .set_tx_desc_blocks = wl12xx_set_tx_desc_blocks,
1604  .set_tx_desc_data_len = wl12xx_set_tx_desc_data_len,
1605  .get_rx_buf_align = wl12xx_get_rx_buf_align,
1606  .get_rx_packet_len = wl12xx_get_rx_packet_len,
1607  .tx_immediate_compl = NULL,
1608  .tx_delayed_compl = wl12xx_tx_delayed_compl,
1609  .hw_init = wl12xx_hw_init,
1610  .init_vif = NULL,
1611  .sta_get_ap_rate_mask = wl12xx_sta_get_ap_rate_mask,
1612  .get_pg_ver = wl12xx_get_pg_ver,
1613  .get_mac = wl12xx_get_mac,
1614  .set_tx_desc_csum = wl12xx_set_tx_desc_csum,
1615  .set_rx_csum = NULL,
1616  .ap_get_mimo_wide_rate_mask = NULL,
1617  .debugfs_init = wl12xx_debugfs_add_files,
1618  .get_spare_blocks = wl12xx_get_spare_blocks,
1619  .set_key = wl12xx_set_key,
1620  .pre_pkt_send = NULL,
1621 };
1622 
1623 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1624  .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1625  (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1626  .ht_supported = true,
1627  .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1628  .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1629  .mcs = {
1630  .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1631  .rx_highest = cpu_to_le16(72),
1632  .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1633  },
1634 };
1635 
1636 static int wl12xx_setup(struct wl1271 *wl)
1637 {
1638  struct wl12xx_priv *priv = wl->priv;
1639  struct wl12xx_platform_data *pdata = wl->pdev->dev.platform_data;
1640 
1641  wl->rtable = wl12xx_rtable;
1642  wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1643  wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1644  wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1645  wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1646  wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1647  wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1648  wl->fw_status_priv_len = 0;
1649  wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1650  wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, &wl12xx_ht_cap);
1651  wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, &wl12xx_ht_cap);
1652  wl12xx_conf_init(wl);
1653 
1654  if (!fref_param) {
1655  priv->ref_clock = pdata->board_ref_clock;
1656  } else {
1657  if (!strcmp(fref_param, "19.2"))
1658  priv->ref_clock = WL12XX_REFCLOCK_19;
1659  else if (!strcmp(fref_param, "26"))
1660  priv->ref_clock = WL12XX_REFCLOCK_26;
1661  else if (!strcmp(fref_param, "26x"))
1662  priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1663  else if (!strcmp(fref_param, "38.4"))
1664  priv->ref_clock = WL12XX_REFCLOCK_38;
1665  else if (!strcmp(fref_param, "38.4x"))
1666  priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1667  else if (!strcmp(fref_param, "52"))
1668  priv->ref_clock = WL12XX_REFCLOCK_52;
1669  else
1670  wl1271_error("Invalid fref parameter %s", fref_param);
1671  }
1672 
1673  if (!tcxo_param) {
1674  priv->tcxo_clock = pdata->board_tcxo_clock;
1675  } else {
1676  if (!strcmp(tcxo_param, "19.2"))
1677  priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1678  else if (!strcmp(tcxo_param, "26"))
1679  priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1680  else if (!strcmp(tcxo_param, "38.4"))
1681  priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1682  else if (!strcmp(tcxo_param, "52"))
1683  priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1684  else if (!strcmp(tcxo_param, "16.368"))
1685  priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1686  else if (!strcmp(tcxo_param, "32.736"))
1687  priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1688  else if (!strcmp(tcxo_param, "16.8"))
1689  priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1690  else if (!strcmp(tcxo_param, "33.6"))
1691  priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1692  else
1693  wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1694  }
1695 
1696  return 0;
1697 }
1698 
1699 static int __devinit wl12xx_probe(struct platform_device *pdev)
1700 {
1701  struct wl1271 *wl;
1702  struct ieee80211_hw *hw;
1703  int ret;
1704 
1705  hw = wlcore_alloc_hw(sizeof(struct wl12xx_priv),
1706  WL12XX_AGGR_BUFFER_SIZE);
1707  if (IS_ERR(hw)) {
1708  wl1271_error("can't allocate hw");
1709  ret = PTR_ERR(hw);
1710  goto out;
1711  }
1712 
1713  wl = hw->priv;
1714  wl->ops = &wl12xx_ops;
1715  wl->ptable = wl12xx_ptable;
1716  ret = wlcore_probe(wl, pdev);
1717  if (ret)
1718  goto out_free;
1719 
1720  return ret;
1721 
1722 out_free:
1723  wlcore_free_hw(wl);
1724 out:
1725  return ret;
1726 }
1727 
1728 static const struct platform_device_id wl12xx_id_table[] __devinitconst = {
1729  { "wl12xx", 0 },
1730  { } /* Terminating Entry */
1731 };
1732 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1733 
1734 static struct platform_driver wl12xx_driver = {
1735  .probe = wl12xx_probe,
1736  .remove = __devexit_p(wlcore_remove),
1737  .id_table = wl12xx_id_table,
1738  .driver = {
1739  .name = "wl12xx_driver",
1740  .owner = THIS_MODULE,
1741  }
1742 };
1743 
1744 module_platform_driver(wl12xx_driver);
1745 
1746 module_param_named(fref, fref_param, charp, 0);
1747 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1748 
1749 module_param_named(tcxo, tcxo_param, charp, 0);
1750 MODULE_PARM_DESC(tcxo,
1751  "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1752 
1753 MODULE_LICENSE("GPL v2");
1754 MODULE_AUTHOR("Luciano Coelho <[email protected]>");
1755 MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
1756 MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
1757 MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
1758 MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
1759 MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
1760 MODULE_FIRMWARE(WL128X_PLT_FW_NAME);
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