25 #define SSB_VERBOSE_PCMCIACORESWITCH_DEBUG 0
29 #define SSB_PCMCIA_ADDRESS0 0x2E
30 #define SSB_PCMCIA_ADDRESS1 0x30
31 #define SSB_PCMCIA_ADDRESS2 0x32
32 #define SSB_PCMCIA_MEMSEG 0x34
33 #define SSB_PCMCIA_SPROMCTL 0x36
34 #define SSB_PCMCIA_SPROMCTL_IDLE 0
35 #define SSB_PCMCIA_SPROMCTL_WRITE 1
36 #define SSB_PCMCIA_SPROMCTL_READ 2
37 #define SSB_PCMCIA_SPROMCTL_WRITEEN 4
38 #define SSB_PCMCIA_SPROMCTL_WRITEDIS 7
39 #define SSB_PCMCIA_SPROMCTL_DONE 8
40 #define SSB_PCMCIA_SPROM_DATALO 0x38
41 #define SSB_PCMCIA_SPROM_DATAHI 0x3A
42 #define SSB_PCMCIA_SPROM_ADDRLO 0x3C
43 #define SSB_PCMCIA_SPROM_ADDRHI 0x3E
46 #define SSB_PCMCIA_CIS 0x80
47 #define SSB_PCMCIA_CIS_ID 0x01
48 #define SSB_PCMCIA_CIS_BOARDREV 0x02
49 #define SSB_PCMCIA_CIS_PA 0x03
50 #define SSB_PCMCIA_CIS_PA_PA0B0_LO 0
51 #define SSB_PCMCIA_CIS_PA_PA0B0_HI 1
52 #define SSB_PCMCIA_CIS_PA_PA0B1_LO 2
53 #define SSB_PCMCIA_CIS_PA_PA0B1_HI 3
54 #define SSB_PCMCIA_CIS_PA_PA0B2_LO 4
55 #define SSB_PCMCIA_CIS_PA_PA0B2_HI 5
56 #define SSB_PCMCIA_CIS_PA_ITSSI 6
57 #define SSB_PCMCIA_CIS_PA_MAXPOW 7
58 #define SSB_PCMCIA_CIS_OEMNAME 0x04
59 #define SSB_PCMCIA_CIS_CCODE 0x05
60 #define SSB_PCMCIA_CIS_ANTENNA 0x06
61 #define SSB_PCMCIA_CIS_ANTGAIN 0x07
62 #define SSB_PCMCIA_CIS_BFLAGS 0x08
63 #define SSB_PCMCIA_CIS_LEDS 0x09
66 #define SSB_PCMCIA_SPROM_SIZE 256
67 #define SSB_PCMCIA_SPROM_SIZE_BYTES (SSB_PCMCIA_SPROM_SIZE * sizeof(u16))
107 (addr & 0x0000F000) >> 12);
111 (addr & 0x00FF0000) >> 16);
115 (addr & 0xFF000000) >> 24);
124 read_addr |= ((
u32)(val & 0x0F)) << 12;
128 read_addr |= ((
u32)val) << 16;
132 read_addr |= ((
u32)val) << 24;
135 if (cur_core == coreidx)
155 #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
157 "Switching to %s core, index %d\n",
206 if (*offset >= 0x800) {
234 err = select_core_and_segment(dev, &offset);
237 spin_unlock_irqrestore(&bus->
bar_lock, flags);
250 err = select_core_and_segment(dev, &offset);
253 spin_unlock_irqrestore(&bus->
bar_lock, flags);
263 u32 lo = 0xFFFFFFFF,
hi = 0xFFFFFFFF;
266 err = select_core_and_segment(dev, &offset);
271 spin_unlock_irqrestore(&bus->
bar_lock, flags);
273 return (lo | (hi << 16));
276 #ifdef CONFIG_SSB_BLOCKIO
286 err = select_core_and_segment(dev, &offset);
288 memset(buffer, 0xFF, count);
330 spin_unlock_irqrestore(&bus->
bar_lock, flags);
334 static void ssb_pcmcia_write8(
struct ssb_device *dev,
u16 offset,
u8 value)
341 err = select_core_and_segment(dev, &offset);
345 spin_unlock_irqrestore(&bus->
bar_lock, flags);
348 static void ssb_pcmcia_write16(
struct ssb_device *dev,
u16 offset,
u16 value)
355 err = select_core_and_segment(dev, &offset);
359 spin_unlock_irqrestore(&bus->
bar_lock, flags);
362 static void ssb_pcmcia_write32(
struct ssb_device *dev,
u16 offset,
u32 value)
369 err = select_core_and_segment(dev, &offset);
371 writew((value & 0x0000FFFF), bus->
mmio + offset);
372 writew(((value & 0xFFFF0000) >> 16), bus->
mmio + offset + 2);
375 spin_unlock_irqrestore(&bus->
bar_lock, flags);
378 #ifdef CONFIG_SSB_BLOCKIO
379 static void ssb_pcmcia_block_write(
struct ssb_device *dev,
const void *buffer,
380 size_t count,
u16 offset,
u8 reg_width)
388 err = select_core_and_segment(dev, &offset);
431 spin_unlock_irqrestore(&bus->
bar_lock, flags);
437 .read8 = ssb_pcmcia_read8,
438 .read16 = ssb_pcmcia_read16,
439 .read32 = ssb_pcmcia_read32,
440 .write8 = ssb_pcmcia_write8,
441 .write16 = ssb_pcmcia_write16,
442 .write32 = ssb_pcmcia_write32,
443 #ifdef CONFIG_SSB_BLOCKIO
444 .block_read = ssb_pcmcia_block_read,
445 .block_write = ssb_pcmcia_block_write,
458 for (i = 0; i < 1000; i++) {
471 static int ssb_pcmcia_sprom_read(
struct ssb_bus *bus,
u16 offset,
u16 *value)
483 (offset & 0xFF00) >> 8);
495 *value = (lo | (((
u16)hi) << 8));
501 static int ssb_pcmcia_sprom_write(
struct ssb_bus *bus,
u16 offset,
u16 value)
512 (offset & 0xFF00) >> 8);
520 (value & 0xFF00) >> 8);
532 static int ssb_pcmcia_sprom_read_all(
struct ssb_bus *bus,
u16 *sprom)
537 err = ssb_pcmcia_sprom_read(bus, i, &sprom[i]);
546 static int ssb_pcmcia_sprom_write_all(
struct ssb_bus *bus,
const u16 *sprom)
553 "Writing SPROM. Do NOT turn off the power! "
554 "Please stand by...\n");
558 "Could not enable SPROM write access.\n");
563 for (i = 0; i <
size; i++) {
566 else if (i == size / 2)
568 else if (i == (size * 3) / 4)
572 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
575 "Failed to write to SPROM.\n");
583 "Could not disable SPROM write access.\n");
592 return failed ? -
EBUSY : 0;
595 static int ssb_pcmcia_sprom_check_crc(
const u16 *sprom,
size_t size)
601 #define GOTO_ERROR_ON(condition, description) do { \
602 if (unlikely(condition)) { \
603 error_description = description; \
608 static int ssb_pcmcia_get_mac(
struct pcmcia_device *p_dev,
624 static int ssb_pcmcia_do_get_invariants(
struct pcmcia_device *p_dev,
631 const char *error_description;
644 "boardrev tpl size");
704 "PCMCIA: Failed to fetch device invariants: %s\n",
716 memset(sprom, 0xFF,
sizeof(*sprom));
723 ssb_pcmcia_get_mac, sprom);
726 "PCMCIA: Failed to fetch MAC address\n");
732 ssb_pcmcia_do_get_invariants, iv);
733 if ((res == 0) || (res == -
ENOSPC))
737 "PCMCIA: Failed to fetch device invariants\n");
741 static ssize_t ssb_pcmcia_attr_sprom_show(
struct device *pcmciadev,
745 struct pcmcia_device *
pdev =
754 ssb_pcmcia_sprom_read_all);
757 static ssize_t ssb_pcmcia_attr_sprom_store(
struct device *pcmciadev,
759 const char *buf,
size_t count)
761 struct pcmcia_device *pdev =
770 ssb_pcmcia_sprom_check_crc,
771 ssb_pcmcia_sprom_write_all);
775 ssb_pcmcia_attr_sprom_show,
776 ssb_pcmcia_attr_sprom_store);
778 static int ssb_pcmcia_cor_setup(
struct ssb_bus *bus,
u8 cor)
783 err = ssb_pcmcia_cfg_read(bus, cor, &val);
788 err = ssb_pcmcia_cfg_write(bus, cor, val);
812 err = ssb_pcmcia_cor_setup(bus,
CISREG_COR + 0x80);