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core.c
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1 
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
46 #include <linux/ioport.h>
47 #include <linux/io.h>
48 #include <linux/list.h>
49 #include <linux/delay.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/of.h>
52 
53 #include <linux/usb/otg.h>
54 #include <linux/usb/ch9.h>
55 #include <linux/usb/gadget.h>
56 
57 #include "core.h"
58 #include "gadget.h"
59 #include "io.h"
60 
61 #include "debug.h"
62 
63 static char *maximum_speed = "super";
64 module_param(maximum_speed, charp, 0);
65 MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
66 
67 /* -------------------------------------------------------------------------- */
68 
69 #define DWC3_DEVS_POSSIBLE 32
70 
71 static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
72 
74 {
75  int id;
76 
77 again:
78  id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
79  if (id < DWC3_DEVS_POSSIBLE) {
80  int old;
81 
82  old = test_and_set_bit(id, dwc3_devs);
83  if (old)
84  goto again;
85  } else {
86  pr_err("dwc3: no space for new device\n");
87  id = -ENOMEM;
88  }
89 
90  return id;
91 }
93 
94 void dwc3_put_device_id(int id)
95 {
96  int ret;
97 
98  if (id < 0)
99  return;
100 
101  ret = test_bit(id, dwc3_devs);
102  WARN(!ret, "dwc3: ID %d not in use\n", id);
104  clear_bit(id, dwc3_devs);
105 }
107 
108 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
109 {
110  u32 reg;
111 
112  reg = dwc3_readl(dwc->regs, DWC3_GCTL);
114  reg |= DWC3_GCTL_PRTCAPDIR(mode);
115  dwc3_writel(dwc->regs, DWC3_GCTL, reg);
116 }
117 
122 static void dwc3_core_soft_reset(struct dwc3 *dwc)
123 {
124  u32 reg;
125 
126  /* Before Resetting PHY, put Core in Reset */
127  reg = dwc3_readl(dwc->regs, DWC3_GCTL);
129  dwc3_writel(dwc->regs, DWC3_GCTL, reg);
130 
131  /* Assert USB3 PHY reset */
132  reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
134  dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
135 
136  /* Assert USB2 PHY reset */
137  reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
139  dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
140 
141  usb_phy_init(dwc->usb2_phy);
142  usb_phy_init(dwc->usb3_phy);
143  mdelay(100);
144 
145  /* Clear USB3 PHY reset */
146  reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
148  dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
149 
150  /* Clear USB2 PHY reset */
151  reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
153  dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
154 
155  mdelay(100);
156 
157  /* After PHYs are stable we can take Core out of reset state */
158  reg = dwc3_readl(dwc->regs, DWC3_GCTL);
159  reg &= ~DWC3_GCTL_CORESOFTRESET;
160  dwc3_writel(dwc->regs, DWC3_GCTL, reg);
161 }
162 
168 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
169  struct dwc3_event_buffer *evt)
170 {
171  dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
172  kfree(evt);
173 }
174 
183 static struct dwc3_event_buffer *__devinit
184 dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
185 {
186  struct dwc3_event_buffer *evt;
187 
188  evt = kzalloc(sizeof(*evt), GFP_KERNEL);
189  if (!evt)
190  return ERR_PTR(-ENOMEM);
191 
192  evt->dwc = dwc;
193  evt->length = length;
194  evt->buf = dma_alloc_coherent(dwc->dev, length,
195  &evt->dma, GFP_KERNEL);
196  if (!evt->buf) {
197  kfree(evt);
198  return ERR_PTR(-ENOMEM);
199  }
200 
201  return evt;
202 }
203 
208 static void dwc3_free_event_buffers(struct dwc3 *dwc)
209 {
210  struct dwc3_event_buffer *evt;
211  int i;
212 
213  for (i = 0; i < dwc->num_event_buffers; i++) {
214  evt = dwc->ev_buffs[i];
215  if (evt)
216  dwc3_free_one_event_buffer(dwc, evt);
217  }
218 
219  kfree(dwc->ev_buffs);
220 }
221 
230 static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
231 {
232  int num;
233  int i;
234 
235  num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
236  dwc->num_event_buffers = num;
237 
238  dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
239  if (!dwc->ev_buffs) {
240  dev_err(dwc->dev, "can't allocate event buffers array\n");
241  return -ENOMEM;
242  }
243 
244  for (i = 0; i < num; i++) {
245  struct dwc3_event_buffer *evt;
246 
247  evt = dwc3_alloc_one_event_buffer(dwc, length);
248  if (IS_ERR(evt)) {
249  dev_err(dwc->dev, "can't allocate event buffer\n");
250  return PTR_ERR(evt);
251  }
252  dwc->ev_buffs[i] = evt;
253  }
254 
255  return 0;
256 }
257 
264 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
265 {
266  struct dwc3_event_buffer *evt;
267  int n;
268 
269  for (n = 0; n < dwc->num_event_buffers; n++) {
270  evt = dwc->ev_buffs[n];
271  dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
272  evt->buf, (unsigned long long) evt->dma,
273  evt->length);
274 
275  evt->lpos = 0;
276 
277  dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
278  lower_32_bits(evt->dma));
279  dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
280  upper_32_bits(evt->dma));
281  dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
282  evt->length & 0xffff);
283  dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
284  }
285 
286  return 0;
287 }
288 
289 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
290 {
291  struct dwc3_event_buffer *evt;
292  int n;
293 
294  for (n = 0; n < dwc->num_event_buffers; n++) {
295  evt = dwc->ev_buffs[n];
296 
297  evt->lpos = 0;
298 
299  dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
300  dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
301  dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
302  dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
303  }
304 }
305 
306 static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
307 {
308  struct dwc3_hwparams *parms = &dwc->hwparams;
309 
310  parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
311  parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
312  parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
313  parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
314  parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
315  parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
316  parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
317  parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
318  parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
319 }
320 
327 static int __devinit dwc3_core_init(struct dwc3 *dwc)
328 {
329  unsigned long timeout;
330  u32 reg;
331  int ret;
332 
333  reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
334  /* This should read as U3 followed by revision number */
335  if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
336  dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
337  ret = -ENODEV;
338  goto err0;
339  }
340  dwc->revision = reg;
341 
342  /* issue device SoftReset too */
343  timeout = jiffies + msecs_to_jiffies(500);
344  dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
345  do {
346  reg = dwc3_readl(dwc->regs, DWC3_DCTL);
347  if (!(reg & DWC3_DCTL_CSFTRST))
348  break;
349 
350  if (time_after(jiffies, timeout)) {
351  dev_err(dwc->dev, "Reset Timed Out\n");
352  ret = -ETIMEDOUT;
353  goto err0;
354  }
355 
356  cpu_relax();
357  } while (true);
358 
359  dwc3_core_soft_reset(dwc);
360 
361  dwc3_cache_hwparams(dwc);
362 
363  reg = dwc3_readl(dwc->regs, DWC3_GCTL);
364  reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
365  reg &= ~DWC3_GCTL_DISSCRAMBLE;
366 
367  switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
369  reg &= ~DWC3_GCTL_DSBLCLKGTNG;
370  break;
371  default:
372  dev_dbg(dwc->dev, "No power optimization available\n");
373  }
374 
375  /*
376  * WORKAROUND: DWC3 revisions <1.90a have a bug
377  * where the device can fail to connect at SuperSpeed
378  * and falls back to high-speed mode which causes
379  * the device to enter a Connect/Disconnect loop
380  */
381  if (dwc->revision < DWC3_REVISION_190A)
382  reg |= DWC3_GCTL_U2RSTECN;
383 
384  dwc3_writel(dwc->regs, DWC3_GCTL, reg);
385 
386  ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
387  if (ret) {
388  dev_err(dwc->dev, "failed to allocate event buffers\n");
389  ret = -ENOMEM;
390  goto err1;
391  }
392 
393  ret = dwc3_event_buffers_setup(dwc);
394  if (ret) {
395  dev_err(dwc->dev, "failed to setup event buffers\n");
396  goto err1;
397  }
398 
399  return 0;
400 
401 err1:
402  dwc3_free_event_buffers(dwc);
403 
404 err0:
405  return ret;
406 }
407 
408 static void dwc3_core_exit(struct dwc3 *dwc)
409 {
410  dwc3_event_buffers_cleanup(dwc);
411  dwc3_free_event_buffers(dwc);
412 
413  usb_phy_shutdown(dwc->usb2_phy);
414  usb_phy_shutdown(dwc->usb3_phy);
415 
416 }
417 
418 #define DWC3_ALIGN_MASK (16 - 1)
419 
420 static int __devinit dwc3_probe(struct platform_device *pdev)
421 {
422  struct device_node *node = pdev->dev.of_node;
423  struct resource *res;
424  struct dwc3 *dwc;
425  struct device *dev = &pdev->dev;
426 
427  int ret = -ENOMEM;
428 
429  void __iomem *regs;
430  void *mem;
431 
432  u8 mode;
433 
434  mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
435  if (!mem) {
436  dev_err(dev, "not enough memory\n");
437  return -ENOMEM;
438  }
439  dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
440  dwc->mem = mem;
441 
442  res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
443  if (!res) {
444  dev_err(dev, "missing IRQ\n");
445  return -ENODEV;
446  }
447  dwc->xhci_resources[1].start = res->start;
448  dwc->xhci_resources[1].end = res->end;
449  dwc->xhci_resources[1].flags = res->flags;
450  dwc->xhci_resources[1].name = res->name;
451 
452  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
453  if (!res) {
454  dev_err(dev, "missing memory resource\n");
455  return -ENODEV;
456  }
457  dwc->xhci_resources[0].start = res->start;
458  dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
460  dwc->xhci_resources[0].flags = res->flags;
461  dwc->xhci_resources[0].name = res->name;
462 
463  /*
464  * Request memory region but exclude xHCI regs,
465  * since it will be requested by the xhci-plat driver.
466  */
468  resource_size(res) - DWC3_GLOBALS_REGS_START,
469  dev_name(dev));
470  if (!res) {
471  dev_err(dev, "can't request mem region\n");
472  return -ENOMEM;
473  }
474 
475  regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
476  if (!regs) {
477  dev_err(dev, "ioremap failed\n");
478  return -ENOMEM;
479  }
480 
482  if (IS_ERR_OR_NULL(dwc->usb2_phy)) {
483  dev_err(dev, "no usb2 phy configured\n");
484  return -EPROBE_DEFER;
485  }
486 
488  if (IS_ERR_OR_NULL(dwc->usb3_phy)) {
489  dev_err(dev, "no usb3 phy configured\n");
490  return -EPROBE_DEFER;
491  }
492 
493  spin_lock_init(&dwc->lock);
494  platform_set_drvdata(pdev, dwc);
495 
496  dwc->regs = regs;
497  dwc->regs_size = resource_size(res);
498  dwc->dev = dev;
499 
500  if (!strncmp("super", maximum_speed, 5))
502  else if (!strncmp("high", maximum_speed, 4))
504  else if (!strncmp("full", maximum_speed, 4))
506  else if (!strncmp("low", maximum_speed, 3))
508  else
510 
511  if (of_get_property(node, "tx-fifo-resize", NULL))
512  dwc->needs_fifo_resize = true;
513 
514  pm_runtime_enable(dev);
515  pm_runtime_get_sync(dev);
516  pm_runtime_forbid(dev);
517 
518  ret = dwc3_core_init(dwc);
519  if (ret) {
520  dev_err(dev, "failed to initialize core\n");
521  return ret;
522  }
523 
524  mode = DWC3_MODE(dwc->hwparams.hwparams0);
525 
526  switch (mode) {
527  case DWC3_MODE_DEVICE:
529  ret = dwc3_gadget_init(dwc);
530  if (ret) {
531  dev_err(dev, "failed to initialize gadget\n");
532  goto err1;
533  }
534  break;
535  case DWC3_MODE_HOST:
537  ret = dwc3_host_init(dwc);
538  if (ret) {
539  dev_err(dev, "failed to initialize host\n");
540  goto err1;
541  }
542  break;
543  case DWC3_MODE_DRD:
545  ret = dwc3_host_init(dwc);
546  if (ret) {
547  dev_err(dev, "failed to initialize host\n");
548  goto err1;
549  }
550 
551  ret = dwc3_gadget_init(dwc);
552  if (ret) {
553  dev_err(dev, "failed to initialize gadget\n");
554  goto err1;
555  }
556  break;
557  default:
558  dev_err(dev, "Unsupported mode of operation %d\n", mode);
559  goto err1;
560  }
561  dwc->mode = mode;
562 
563  ret = dwc3_debugfs_init(dwc);
564  if (ret) {
565  dev_err(dev, "failed to initialize debugfs\n");
566  goto err2;
567  }
568 
569  pm_runtime_allow(dev);
570 
571  return 0;
572 
573 err2:
574  switch (mode) {
575  case DWC3_MODE_DEVICE:
576  dwc3_gadget_exit(dwc);
577  break;
578  case DWC3_MODE_HOST:
579  dwc3_host_exit(dwc);
580  break;
581  case DWC3_MODE_DRD:
582  dwc3_host_exit(dwc);
583  dwc3_gadget_exit(dwc);
584  break;
585  default:
586  /* do nothing */
587  break;
588  }
589 
590 err1:
591  dwc3_core_exit(dwc);
592 
593  return ret;
594 }
595 
596 static int __devexit dwc3_remove(struct platform_device *pdev)
597 {
598  struct dwc3 *dwc = platform_get_drvdata(pdev);
599  struct resource *res;
600 
601  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
602 
603  pm_runtime_put(&pdev->dev);
604  pm_runtime_disable(&pdev->dev);
605 
606  dwc3_debugfs_exit(dwc);
607 
608  switch (dwc->mode) {
609  case DWC3_MODE_DEVICE:
610  dwc3_gadget_exit(dwc);
611  break;
612  case DWC3_MODE_HOST:
613  dwc3_host_exit(dwc);
614  break;
615  case DWC3_MODE_DRD:
616  dwc3_host_exit(dwc);
617  dwc3_gadget_exit(dwc);
618  break;
619  default:
620  /* do nothing */
621  break;
622  }
623 
624  dwc3_core_exit(dwc);
625 
626  return 0;
627 }
628 
629 static struct platform_driver dwc3_driver = {
630  .probe = dwc3_probe,
631  .remove = __devexit_p(dwc3_remove),
632  .driver = {
633  .name = "dwc3",
634  },
635 };
636 
637 module_platform_driver(dwc3_driver);
638 
639 MODULE_ALIAS("platform:dwc3");
640 MODULE_AUTHOR("Felipe Balbi <[email protected]>");
641 MODULE_LICENSE("Dual BSD/GPL");
642 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");