#include <linux/device.h>
#include <linux/spinlock.h>
#include <linux/ioport.h>
#include <linux/list.h>
#include <linux/dma-mapping.h>
#include <linux/mm.h>
#include <linux/debugfs.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>

Data Structures
struct	dwc3_event_buffer

struct	dwc3_ep

struct	dwc3_trb

struct	dwc3_hwparams

struct	dwc3_request

struct	dwc3_scratchpad_array

struct	dwc3

struct	dwc3_event_type

struct	dwc3_event_depevt

struct	dwc3_event_devt

struct	dwc3_event_gevt

union	dwc3_event

Macros
#define	DWC3_EP0_BOUNCE_SIZE 512

#define	DWC3_ENDPOINTS_NUM 32

#define	DWC3_XHCI_RESOURCES_NUM 2

#define	DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE

#define	DWC3_EVENT_TYPE_MASK 0xfe

#define	DWC3_EVENT_TYPE_DEV 0

#define	DWC3_EVENT_TYPE_CARKIT 3

#define	DWC3_EVENT_TYPE_I2C 4

#define	DWC3_DEVICE_EVENT_DISCONNECT 0

#define	DWC3_DEVICE_EVENT_RESET 1

#define	DWC3_DEVICE_EVENT_CONNECT_DONE 2

#define	DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3

#define	DWC3_DEVICE_EVENT_WAKEUP 4

#define	DWC3_DEVICE_EVENT_HIBER_REQ 5

#define	DWC3_DEVICE_EVENT_EOPF 6

#define	DWC3_DEVICE_EVENT_SOF 7

#define	DWC3_DEVICE_EVENT_ERRATIC_ERROR 9

#define	DWC3_DEVICE_EVENT_CMD_CMPL 10

#define	DWC3_DEVICE_EVENT_OVERFLOW 11

#define	DWC3_GEVNTCOUNT_MASK 0xfffc

#define	DWC3_GSNPSID_MASK 0xffff0000

#define	DWC3_GSNPSREV_MASK 0xffff

#define	DWC3_XHCI_REGS_START 0x0

#define	DWC3_XHCI_REGS_END 0x7fff

#define	DWC3_GLOBALS_REGS_START 0xc100

#define	DWC3_GLOBALS_REGS_END 0xc6ff

#define	DWC3_DEVICE_REGS_START 0xc700

#define	DWC3_DEVICE_REGS_END 0xcbff

#define	DWC3_OTG_REGS_START 0xcc00

#define	DWC3_OTG_REGS_END 0xccff

#define	DWC3_GSBUSCFG0 0xc100

#define	DWC3_GSBUSCFG1 0xc104

#define	DWC3_GTXTHRCFG 0xc108

#define	DWC3_GRXTHRCFG 0xc10c

#define	DWC3_GCTL 0xc110

#define	DWC3_GEVTEN 0xc114

#define	DWC3_GSTS 0xc118

#define	DWC3_GSNPSID 0xc120

#define	DWC3_GGPIO 0xc124

#define	DWC3_GUID 0xc128

#define	DWC3_GUCTL 0xc12c

#define	DWC3_GBUSERRADDR0 0xc130

#define	DWC3_GBUSERRADDR1 0xc134

#define	DWC3_GPRTBIMAP0 0xc138

#define	DWC3_GPRTBIMAP1 0xc13c

#define	DWC3_GHWPARAMS0 0xc140

#define	DWC3_GHWPARAMS1 0xc144

#define	DWC3_GHWPARAMS2 0xc148

#define	DWC3_GHWPARAMS3 0xc14c

#define	DWC3_GHWPARAMS4 0xc150

#define	DWC3_GHWPARAMS5 0xc154

#define	DWC3_GHWPARAMS6 0xc158

#define	DWC3_GHWPARAMS7 0xc15c

#define	DWC3_GDBGFIFOSPACE 0xc160

#define	DWC3_GDBGLTSSM 0xc164

#define	DWC3_GPRTBIMAP_HS0 0xc180

#define	DWC3_GPRTBIMAP_HS1 0xc184

#define	DWC3_GPRTBIMAP_FS0 0xc188

#define	DWC3_GPRTBIMAP_FS1 0xc18c

#define	DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))

#define	DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))

#define	DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))

#define	DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))

#define	DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))

#define	DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))

#define	DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))

#define	DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))

#define	DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))

#define	DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))

#define	DWC3_GHWPARAMS8 0xc600

#define	DWC3_DCFG 0xc700

#define	DWC3_DCTL 0xc704

#define	DWC3_DEVTEN 0xc708

#define	DWC3_DSTS 0xc70c

#define	DWC3_DGCMDPAR 0xc710

#define	DWC3_DGCMD 0xc714

#define	DWC3_DALEPENA 0xc720

#define	DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))

#define	DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))

#define	DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))

#define	DWC3_DEPCMD(n) (0xc80c + (n * 0x10))

#define	DWC3_OCFG 0xcc00

#define	DWC3_OCTL 0xcc04

#define	DWC3_OEVTEN 0xcc08

#define	DWC3_OSTS 0xcc0C

#define	DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)

#define	DWC3_GCTL_U2RSTECN (1 << 16)

#define	DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)

#define	DWC3_GCTL_CLK_BUS (0)

#define	DWC3_GCTL_CLK_PIPE (1)

#define	DWC3_GCTL_CLK_PIPEHALF (2)

#define	DWC3_GCTL_CLK_MASK (3)

#define	DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)

#define	DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)

#define	DWC3_GCTL_PRTCAP_HOST 1

#define	DWC3_GCTL_PRTCAP_DEVICE 2

#define	DWC3_GCTL_PRTCAP_OTG 3

#define	DWC3_GCTL_CORESOFTRESET (1 << 11)

#define	DWC3_GCTL_SCALEDOWN(n) ((n) << 4)

#define	DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)

#define	DWC3_GCTL_DISSCRAMBLE (1 << 3)

#define	DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)

#define	DWC3_GCTL_DSBLCLKGTNG (1 << 0)

#define	DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)

#define	DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)

#define	DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)

#define	DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)

#define	DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)

#define	DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)

#define	DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)

#define	DWC3_GHWPARAMS1_EN_PWROPT_NO 0

#define	DWC3_GHWPARAMS1_EN_PWROPT_CLK 1

#define	DWC3_GHWPARAMS1_EN_PWROPT_HIB 2

#define	DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)

#define	DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)

#define	DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)

#define	DWC3_MAX_HIBER_SCRATCHBUFS 15

#define	DWC3_DCFG_LPM_CAP (1 << 22)

#define	DWC3_DCFG_DEVADDR(addr) ((addr) << 3)

#define	DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)

#define	DWC3_DCFG_SPEED_MASK (7 << 0)

#define	DWC3_DCFG_SUPERSPEED (4 << 0)

#define	DWC3_DCFG_HIGHSPEED (0 << 0)

#define	DWC3_DCFG_FULLSPEED2 (1 << 0)

#define	DWC3_DCFG_LOWSPEED (2 << 0)

#define	DWC3_DCFG_FULLSPEED1 (3 << 0)

#define	DWC3_DCFG_LPM_CAP (1 << 22)

#define	DWC3_DCTL_RUN_STOP (1 << 31)

#define	DWC3_DCTL_CSFTRST (1 << 30)

#define	DWC3_DCTL_LSFTRST (1 << 29)

#define	DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)

#define	DWC3_DCTL_HIRD_THRES(n) ((n) << 24)

#define	DWC3_DCTL_APPL1RES (1 << 23)

#define	DWC3_DCTL_TRGTULST_MASK (0x0f << 17)

#define	DWC3_DCTL_TRGTULST(n) ((n) << 17)

#define	DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))

#define	DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))

#define	DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))

#define	DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))

#define	DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))

#define	DWC3_DCTL_KEEP_CONNECT (1 << 19)

#define	DWC3_DCTL_L1_HIBER_EN (1 << 18)

#define	DWC3_DCTL_CRS (1 << 17)

#define	DWC3_DCTL_CSS (1 << 16)

#define	DWC3_DCTL_INITU2ENA (1 << 12)

#define	DWC3_DCTL_ACCEPTU2ENA (1 << 11)

#define	DWC3_DCTL_INITU1ENA (1 << 10)

#define	DWC3_DCTL_ACCEPTU1ENA (1 << 9)

#define	DWC3_DCTL_TSTCTRL_MASK (0xf << 1)

#define	DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)

#define	DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)

#define	DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))

#define	DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))

#define	DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))

#define	DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))

#define	DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))

#define	DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))

#define	DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))

#define	DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)

#define	DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)

#define	DWC3_DEVTEN_CMDCMPLTEN (1 << 10)

#define	DWC3_DEVTEN_ERRTICERREN (1 << 9)

#define	DWC3_DEVTEN_SOFEN (1 << 7)

#define	DWC3_DEVTEN_EOPFEN (1 << 6)

#define	DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)

#define	DWC3_DEVTEN_WKUPEVTEN (1 << 4)

#define	DWC3_DEVTEN_ULSTCNGEN (1 << 3)

#define	DWC3_DEVTEN_CONNECTDONEEN (1 << 2)

#define	DWC3_DEVTEN_USBRSTEN (1 << 1)

#define	DWC3_DEVTEN_DISCONNEVTEN (1 << 0)

#define	DWC3_DSTS_DCNRD (1 << 29)

#define	DWC3_DSTS_PWRUPREQ (1 << 24)

#define	DWC3_DSTS_RSS (1 << 25)

#define	DWC3_DSTS_SSS (1 << 24)

#define	DWC3_DSTS_COREIDLE (1 << 23)

#define	DWC3_DSTS_DEVCTRLHLT (1 << 22)

#define	DWC3_DSTS_USBLNKST_MASK (0x0f << 18)

#define	DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)

#define	DWC3_DSTS_RXFIFOEMPTY (1 << 17)

#define	DWC3_DSTS_SOFFN_MASK (0x3fff << 3)

#define	DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)

#define	DWC3_DSTS_CONNECTSPD (7 << 0)

#define	DWC3_DSTS_SUPERSPEED (4 << 0)

#define	DWC3_DSTS_HIGHSPEED (0 << 0)

#define	DWC3_DSTS_FULLSPEED2 (1 << 0)

#define	DWC3_DSTS_LOWSPEED (2 << 0)

#define	DWC3_DSTS_FULLSPEED1 (3 << 0)

#define	DWC3_DGCMD_SET_LMP 0x01

#define	DWC3_DGCMD_SET_PERIODIC_PAR 0x02

#define	DWC3_DGCMD_XMIT_FUNCTION 0x03

#define	DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04

#define	DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05

#define	DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09

#define	DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a

#define	DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c

#define	DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10

#define	DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)

#define	DWC3_DGCMD_CMDACT (1 << 10)

#define	DWC3_DGCMD_CMDIOC (1 << 8)

#define	DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)

#define	DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)

#define	DWC3_DGCMDPAR_RX_FIFO (0 << 5)

#define	DWC3_DGCMDPAR_TX_FIFO (1 << 5)

#define	DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)

#define	DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)

#define	DWC3_DEPCMD_PARAM_SHIFT 16

#define	DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)

#define	DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)

#define	DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)

#define	DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)

#define	DWC3_DEPCMD_CMDACT (1 << 10)

#define	DWC3_DEPCMD_CMDIOC (1 << 8)

#define	DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)

#define	DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)

#define	DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)

#define	DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)

#define	DWC3_DEPCMD_CLEARSTALL (0x05 << 0)

#define	DWC3_DEPCMD_SETSTALL (0x04 << 0)

#define	DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)

#define	DWC3_DEPCMD_GETEPSTATE (0x03 << 0)

#define	DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)

#define	DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)

#define	DWC3_DALEPENA_EP(n) (1 << n)

#define	DWC3_DEPCMD_TYPE_CONTROL 0

#define	DWC3_DEPCMD_TYPE_ISOC 1

#define	DWC3_DEPCMD_TYPE_BULK 2

#define	DWC3_DEPCMD_TYPE_INTR 3

#define	DWC3_EP_FLAG_STALLED (1 << 0)

#define	DWC3_EP_FLAG_WEDGED (1 << 1)

#define	DWC3_EP_DIRECTION_TX true

#define	DWC3_EP_DIRECTION_RX false

#define	DWC3_TRB_NUM 32

#define	DWC3_TRB_MASK (DWC3_TRB_NUM - 1)

#define	DWC3_EP_ENABLED (1 << 0)

#define	DWC3_EP_STALL (1 << 1)

#define	DWC3_EP_WEDGE (1 << 2)

#define	DWC3_EP_BUSY (1 << 4)

#define	DWC3_EP_PENDING_REQUEST (1 << 5)

#define	DWC3_EP_MISSED_ISOC (1 << 6)

#define	DWC3_EP0_DIR_IN (1 << 31)

#define	DWC3_REVISION_173A 0x5533173a

#define	DWC3_REVISION_175A 0x5533175a

#define	DWC3_REVISION_180A 0x5533180a

#define	DWC3_REVISION_183A 0x5533183a

#define	DWC3_REVISION_185A 0x5533185a

#define	DWC3_REVISION_187A 0x5533187a

#define	DWC3_REVISION_188A 0x5533188a

#define	DWC3_REVISION_190A 0x5533190a

#define	DWC3_REVISION_194A 0x5533194a

#define	DWC3_REVISION_200A 0x5533200a

#define	DWC3_REVISION_202A 0x5533202a

#define	DWC3_REVISION_210A 0x5533210a

#define	DWC3_REVISION_220A 0x5533220a

#define	DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)

#define	DEPEVT_STATUS_BUSERR (1 << 0)

#define	DEPEVT_STATUS_SHORT (1 << 1)

#define	DEPEVT_STATUS_IOC (1 << 2)

#define	DEPEVT_STATUS_LST (1 << 3)

#define	DEPEVT_STREAMEVT_FOUND 1

#define	DEPEVT_STREAMEVT_NOTFOUND 2

#define	DEPEVT_STATUS_CONTROL_DATA 1

#define	DEPEVT_STATUS_CONTROL_STATUS 2

: a human readable name e.g. ep1out-bulk
struct dwc3_ep - device side endpoint representation : usb endpoint : list of requests for this endpoint : list of requests on this ep which have TRBs setup : array of transaction buffers : dma address of : next slot which is going to be used : first slot which is owned by HW : usb_endpoint_descriptor pointer : pointer to DWC controller : endpoint flags (wedged, stalled, ...) : index of current used trb : endpoint number (1 - 15) : set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK : Resource transfer index : Current uf received through last event parameter : the intervall on which the ISOC transfer is started : true for TX, false for RX : true when streams are enabled
#define	DWC3_TRB_SIZE_MASK (0x00ffffff)

#define	DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)

#define	DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)

#define	DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)

#define	DWC3_TRBSTS_OK 0

#define	DWC3_TRBSTS_MISSED_ISOC 1

#define	DWC3_TRBSTS_SETUP_PENDING 2

#define	DWC3_TRB_STS_XFER_IN_PROG 4

#define	DWC3_TRB_CTRL_HWO (1 << 0)

#define	DWC3_TRB_CTRL_LST (1 << 1)

#define	DWC3_TRB_CTRL_CHN (1 << 2)

#define	DWC3_TRB_CTRL_CSP (1 << 3)

#define	DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)

#define	DWC3_TRB_CTRL_ISP_IMI (1 << 10)

#define	DWC3_TRB_CTRL_IOC (1 << 11)

#define	DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)

#define	DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)

#define	DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)

#define	DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)

#define	DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)

#define	DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)

#define	DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)

#define	DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)

#define	DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)

#define	DWC3_MODE(n) ((n) & 0x7)

#define	DWC3_MODE_DEVICE 0

#define	DWC3_MODE_HOST 1

#define	DWC3_MODE_DRD 2

#define	DWC3_MODE_HUB 3

#define	DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)

#define	DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)

#define	DWC3_RAM1_DEPTH(n) ((n) & 0xffff)

#define	DWC3_DEPEVT_XFERCOMPLETE 0x01

#define	DWC3_DEPEVT_XFERINPROGRESS 0x02

#define	DWC3_DEPEVT_XFERNOTREADY 0x03

#define	DWC3_DEPEVT_RXTXFIFOEVT 0x04

#define	DWC3_DEPEVT_STREAMEVT 0x06

#define	DWC3_DEPEVT_EPCMDCMPLT 0x07

#define	DWC3_HAS_PERIPHERAL BIT(0)

#define	DWC3_HAS_XHCI BIT(1)

#define	DWC3_HAS_OTG BIT(3)

enum	dwc3_phy { DWC3_PHY_UNKNOWN = 0, DWC3_PHY_USB3, DWC3_PHY_USB2 }

enum	dwc3_ep0_next { DWC3_EP0_UNKNOWN = 0, DWC3_EP0_COMPLETE, DWC3_EP0_NRDY_DATA, DWC3_EP0_NRDY_STATUS }

enum	dwc3_ep0_state { EP0_UNCONNECTED = 0, EP0_SETUP_PHASE, EP0_DATA_PHASE, EP0_STATUS_PHASE }

enum	dwc3_link_state { DWC3_LINK_STATE_U0 = 0x00, DWC3_LINK_STATE_U1 = 0x01, DWC3_LINK_STATE_U2 = 0x02, DWC3_LINK_STATE_U3 = 0x03, DWC3_LINK_STATE_SS_DIS = 0x04, DWC3_LINK_STATE_RX_DET = 0x05, DWC3_LINK_STATE_SS_INACT = 0x06, DWC3_LINK_STATE_POLL = 0x07, DWC3_LINK_STATE_RECOV = 0x08, DWC3_LINK_STATE_HRESET = 0x09, DWC3_LINK_STATE_CMPLY = 0x0a, DWC3_LINK_STATE_LPBK = 0x0b, DWC3_LINK_STATE_RESET = 0x0e, DWC3_LINK_STATE_RESUME = 0x0f, DWC3_LINK_STATE_MASK = 0x0f }

enum	dwc3_device_state { DWC3_DEFAULT_STATE, DWC3_ADDRESS_STATE, DWC3_CONFIGURED_STATE }

struct dwc3_trb	__packed

void	dwc3_set_mode (struct dwc3 *dwc, u32 mode)

int	dwc3_gadget_resize_tx_fifos (struct dwc3 *dwc)

int	dwc3_host_init (struct dwc3 *dwc)

void	dwc3_host_exit (struct dwc3 *dwc)

int	dwc3_gadget_init (struct dwc3 *dwc)

void	dwc3_gadget_exit (struct dwc3 *dwc)

int	dwc3_get_device_id (void)

void	dwc3_put_device_id (int id)

Macro Definition Documentation

#define DEPEVT_STATUS_BUSERR (1 << 0)

Definition at line 776 of file core.h.

#define DEPEVT_STATUS_CONTROL_DATA 1

Definition at line 786 of file core.h.

#define DEPEVT_STATUS_CONTROL_STATUS 2

Definition at line 787 of file core.h.

#define DEPEVT_STATUS_IOC (1 << 2)

Definition at line 778 of file core.h.

#define DEPEVT_STATUS_LST (1 << 3)

Definition at line 779 of file core.h.

#define DEPEVT_STATUS_SHORT (1 << 1)

Definition at line 777 of file core.h.

#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)

Definition at line 773 of file core.h.

#define DEPEVT_STREAMEVT_FOUND 1

Definition at line 782 of file core.h.

#define DEPEVT_STREAMEVT_NOTFOUND 2

Definition at line 783 of file core.h.

#define DWC3_DALEPENA 0xc720

Definition at line 146 of file core.h.

#define DWC3_DALEPENA_EP ( n ) (1 << n)

Definition at line 354 of file core.h.

#define DWC3_DCFG 0xc700

Definition at line 140 of file core.h.

#define DWC3_DCFG_DEVADDR ( addr ) ((addr) << 3)

Definition at line 208 of file core.h.

#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)

Definition at line 209 of file core.h.

#define DWC3_DCFG_FULLSPEED1 (3 << 0)

Definition at line 216 of file core.h.

#define DWC3_DCFG_FULLSPEED2 (1 << 0)

Definition at line 214 of file core.h.

#define DWC3_DCFG_HIGHSPEED (0 << 0)

Definition at line 213 of file core.h.

#define DWC3_DCFG_LOWSPEED (2 << 0)

Definition at line 215 of file core.h.

#define DWC3_DCFG_LPM_CAP (1 << 22)

Definition at line 218 of file core.h.

#define DWC3_DCFG_LPM_CAP (1 << 22)

Definition at line 218 of file core.h.

#define DWC3_DCFG_SPEED_MASK (7 << 0)

Definition at line 211 of file core.h.

#define DWC3_DCFG_SUPERSPEED (4 << 0)

Definition at line 212 of file core.h.

#define DWC3_DCTL 0xc704

Definition at line 141 of file core.h.

#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)

Definition at line 248 of file core.h.

#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)

Definition at line 246 of file core.h.

#define DWC3_DCTL_APPL1RES (1 << 23)

Definition at line 228 of file core.h.

#define DWC3_DCTL_CRS (1 << 17)

Definition at line 242 of file core.h.

#define DWC3_DCTL_CSFTRST (1 << 30)

Definition at line 222 of file core.h.

#define DWC3_DCTL_CSS (1 << 16)

Definition at line 243 of file core.h.

#define DWC3_DCTL_HIRD_THRES ( n ) ((n) << 24)

Definition at line 226 of file core.h.

#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)

Definition at line 225 of file core.h.

#define DWC3_DCTL_INITU1ENA (1 << 10)

Definition at line 247 of file core.h.

#define DWC3_DCTL_INITU2ENA (1 << 12)

Definition at line 245 of file core.h.

#define DWC3_DCTL_KEEP_CONNECT (1 << 19)

Definition at line 240 of file core.h.

#define DWC3_DCTL_L1_HIBER_EN (1 << 18)

Definition at line 241 of file core.h.

#define DWC3_DCTL_LSFTRST (1 << 29)

Definition at line 223 of file core.h.

#define DWC3_DCTL_RUN_STOP (1 << 31)

Definition at line 221 of file core.h.

#define DWC3_DCTL_TRGTULST ( n ) ((n) << 17)

Definition at line 232 of file core.h.

#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)

Definition at line 231 of file core.h.

#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))

Definition at line 236 of file core.h.

#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))

Definition at line 235 of file core.h.

#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))

Definition at line 237 of file core.h.

#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))

Definition at line 233 of file core.h.

#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))

Definition at line 234 of file core.h.

#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)

Definition at line 249 of file core.h.

#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))

Definition at line 259 of file core.h.

#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))

Definition at line 260 of file core.h.

#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))

Definition at line 254 of file core.h.

#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))

Definition at line 258 of file core.h.

#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))

Definition at line 256 of file core.h.

#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))

Definition at line 255 of file core.h.

#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))

Definition at line 257 of file core.h.

#define DWC3_DCTL_ULSTCHNGREQ ( n ) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)

Definition at line 252 of file core.h.

#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)

Definition at line 251 of file core.h.

#define DWC3_DEPCMD ( n ) (0xc80c + (n * 0x10))

Definition at line 150 of file core.h.

#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)

Definition at line 344 of file core.h.

#define DWC3_DEPCMD_CMDACT (1 << 10)

Definition at line 337 of file core.h.

#define DWC3_DEPCMD_CMDIOC (1 << 8)

Definition at line 338 of file core.h.

#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)

Definition at line 340 of file core.h.

#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)

Definition at line 341 of file core.h.

#define DWC3_DEPCMD_GET_RSC_IDX ( x ) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)

Definition at line 334 of file core.h.

#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)

Definition at line 349 of file core.h.

#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)

Definition at line 347 of file core.h.

#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)

Definition at line 336 of file core.h.

#define DWC3_DEPCMD_PARAM ( x ) ((x) << DWC3_DEPCMD_PARAM_SHIFT)

Definition at line 333 of file core.h.

#define DWC3_DEPCMD_PARAM_SHIFT 16

Definition at line 332 of file core.h.

#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)

Definition at line 351 of file core.h.

#define DWC3_DEPCMD_SETSTALL (0x04 << 0)

Definition at line 345 of file core.h.

#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)

Definition at line 350 of file core.h.

#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)

Definition at line 343 of file core.h.

#define DWC3_DEPCMD_STATUS ( x ) (((x) >> 15) & 1)

Definition at line 335 of file core.h.

#define DWC3_DEPCMD_TYPE_BULK 2

Definition at line 358 of file core.h.

#define DWC3_DEPCMD_TYPE_CONTROL 0

Definition at line 356 of file core.h.

#define DWC3_DEPCMD_TYPE_INTR 3

Definition at line 359 of file core.h.

#define DWC3_DEPCMD_TYPE_ISOC 1

Definition at line 357 of file core.h.

#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)

Definition at line 342 of file core.h.

#define DWC3_DEPCMDPAR0 ( n ) (0xc808 + (n * 0x10))

Definition at line 149 of file core.h.

#define DWC3_DEPCMDPAR1 ( n ) (0xc804 + (n * 0x10))

Definition at line 148 of file core.h.

#define DWC3_DEPCMDPAR2 ( n ) (0xc800 + (n * 0x10))

Definition at line 147 of file core.h.

#define DWC3_DEPEVT_EPCMDCMPLT 0x07

Definition at line 744 of file core.h.

#define DWC3_DEPEVT_RXTXFIFOEVT 0x04

Definition at line 742 of file core.h.

#define DWC3_DEPEVT_STREAMEVT 0x06

Definition at line 743 of file core.h.

#define DWC3_DEPEVT_XFERCOMPLETE 0x01

Definition at line 739 of file core.h.

#define DWC3_DEPEVT_XFERINPROGRESS 0x02

Definition at line 740 of file core.h.

#define DWC3_DEPEVT_XFERNOTREADY 0x03

Definition at line 741 of file core.h.

#define DWC3_DEVICE_EVENT_CMD_CMPL 10

Definition at line 74 of file core.h.

#define DWC3_DEVICE_EVENT_CONNECT_DONE 2

Definition at line 67 of file core.h.

#define DWC3_DEVICE_EVENT_DISCONNECT 0

Definition at line 65 of file core.h.

#define DWC3_DEVICE_EVENT_EOPF 6

Definition at line 71 of file core.h.

#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9

Definition at line 73 of file core.h.

#define DWC3_DEVICE_EVENT_HIBER_REQ 5

Definition at line 70 of file core.h.

#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3

Definition at line 68 of file core.h.

#define DWC3_DEVICE_EVENT_OVERFLOW 11

Definition at line 75 of file core.h.

#define DWC3_DEVICE_EVENT_RESET 1

Definition at line 66 of file core.h.

#define DWC3_DEVICE_EVENT_SOF 7

Definition at line 72 of file core.h.

#define DWC3_DEVICE_EVENT_WAKEUP 4

Definition at line 69 of file core.h.

#define DWC3_DEVICE_REGS_END 0xcbff

Definition at line 87 of file core.h.

#define DWC3_DEVICE_REGS_START 0xc700

Definition at line 86 of file core.h.

#define DWC3_DEVTEN 0xc708

Definition at line 142 of file core.h.

#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)

Definition at line 265 of file core.h.

#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)

Definition at line 272 of file core.h.

#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)

Definition at line 274 of file core.h.

#define DWC3_DEVTEN_EOPFEN (1 << 6)

Definition at line 268 of file core.h.

#define DWC3_DEVTEN_ERRTICERREN (1 << 9)

Definition at line 266 of file core.h.

#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)

Definition at line 264 of file core.h.

#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)

Definition at line 269 of file core.h.

#define DWC3_DEVTEN_SOFEN (1 << 7)

Definition at line 267 of file core.h.

#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)

Definition at line 271 of file core.h.

#define DWC3_DEVTEN_USBRSTEN (1 << 1)

Definition at line 273 of file core.h.

#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)

Definition at line 263 of file core.h.

#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)

Definition at line 270 of file core.h.

#define DWC3_DGCMD 0xc714

Definition at line 145 of file core.h.

#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a

Definition at line 315 of file core.h.

#define DWC3_DGCMD_CMDACT (1 << 10)

Definition at line 320 of file core.h.

#define DWC3_DGCMD_CMDIOC (1 << 8)

Definition at line 321 of file core.h.

#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10

Definition at line 317 of file core.h.

#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09

Definition at line 314 of file core.h.

#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c

Definition at line 316 of file core.h.

#define DWC3_DGCMD_SET_LMP 0x01

Definition at line 306 of file core.h.

#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02

Definition at line 307 of file core.h.

#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05

Definition at line 312 of file core.h.

#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04

Definition at line 311 of file core.h.

#define DWC3_DGCMD_STATUS ( n ) (((n) >> 15) & 1)

Definition at line 319 of file core.h.

#define DWC3_DGCMD_XMIT_FUNCTION 0x03

Definition at line 308 of file core.h.

#define DWC3_DGCMDPAR 0xc710

Definition at line 144 of file core.h.

#define DWC3_DGCMDPAR_FIFO_NUM ( n ) ((n) << 0)

Definition at line 325 of file core.h.

#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)

Definition at line 324 of file core.h.

#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)

Definition at line 328 of file core.h.

#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)

Definition at line 329 of file core.h.

#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)

Definition at line 326 of file core.h.

#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)

Definition at line 327 of file core.h.

#define DWC3_DSTS 0xc70c

Definition at line 143 of file core.h.

#define DWC3_DSTS_CONNECTSPD (7 << 0)

Definition at line 297 of file core.h.

#define DWC3_DSTS_COREIDLE (1 << 23)

Definition at line 286 of file core.h.

#define DWC3_DSTS_DCNRD (1 << 29)

Definition at line 277 of file core.h.

#define DWC3_DSTS_DEVCTRLHLT (1 << 22)

Definition at line 287 of file core.h.

#define DWC3_DSTS_FULLSPEED1 (3 << 0)

Definition at line 303 of file core.h.

#define DWC3_DSTS_FULLSPEED2 (1 << 0)

Definition at line 301 of file core.h.

#define DWC3_DSTS_HIGHSPEED (0 << 0)

Definition at line 300 of file core.h.

#define DWC3_DSTS_LOWSPEED (2 << 0)

Definition at line 302 of file core.h.

#define DWC3_DSTS_PWRUPREQ (1 << 24)

Definition at line 280 of file core.h.

#define DWC3_DSTS_RSS (1 << 25)

Definition at line 283 of file core.h.

#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)

Definition at line 292 of file core.h.

#define DWC3_DSTS_SOFFN ( n ) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)

Definition at line 295 of file core.h.

#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)

Definition at line 294 of file core.h.

#define DWC3_DSTS_SSS (1 << 24)

Definition at line 284 of file core.h.

#define DWC3_DSTS_SUPERSPEED (4 << 0)

Definition at line 299 of file core.h.

#define DWC3_DSTS_USBLNKST ( n ) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)

Definition at line 290 of file core.h.

#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)

Definition at line 289 of file core.h.

#define DWC3_ENDPOINTS_NUM 32

Definition at line 55 of file core.h.

#define DWC3_EP0_BOUNCE_SIZE 512

core.h - DesignWare USB3 DRD Core Header

Authors: Felipe Balbi balbi.nosp@m.@ti..nosp@m.com, Sebastian Andrzej Siewior bigea.nosp@m.sy@l.nosp@m.inutr.nosp@m.onix.nosp@m..de

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer, without modification.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of the above-listed copyright holders may not be used to endorse or promote products derived from this software without specific prior written permission.

ALTERNATIVELY, this software may be distributed under the terms of the GNU General Public License ("GPL") version 2, as published by the Free Software Foundation.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition at line 54 of file core.h.

#define DWC3_EP0_DIR_IN (1 << 31)

Definition at line 435 of file core.h.

#define DWC3_EP_BUSY (1 << 4)

Definition at line 430 of file core.h.

#define DWC3_EP_DIRECTION_RX false

Definition at line 387 of file core.h.

#define DWC3_EP_DIRECTION_TX true

Definition at line 386 of file core.h.

#define DWC3_EP_ENABLED (1 << 0)

Definition at line 427 of file core.h.

#define DWC3_EP_FLAG_STALLED (1 << 0)

Definition at line 383 of file core.h.

#define DWC3_EP_FLAG_WEDGED (1 << 1)

Definition at line 384 of file core.h.

#define DWC3_EP_MISSED_ISOC (1 << 6)

Definition at line 432 of file core.h.

#define DWC3_EP_PENDING_REQUEST (1 << 5)

Definition at line 431 of file core.h.

#define DWC3_EP_STALL (1 << 1)

Definition at line 428 of file core.h.

#define DWC3_EP_WEDGE (1 << 2)

Definition at line 429 of file core.h.

#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE

Definition at line 58 of file core.h.

#define DWC3_EVENT_TYPE_CARKIT 3

Definition at line 62 of file core.h.

#define DWC3_EVENT_TYPE_DEV 0

Definition at line 61 of file core.h.

#define DWC3_EVENT_TYPE_I2C 4

Definition at line 63 of file core.h.

#define DWC3_EVENT_TYPE_MASK 0xfe

Definition at line 59 of file core.h.

#define DWC3_GBUSERRADDR0 0xc130

Definition at line 103 of file core.h.

#define DWC3_GBUSERRADDR1 0xc134

Definition at line 104 of file core.h.

#define DWC3_GCTL 0xc110

Definition at line 96 of file core.h.

#define DWC3_GCTL_CLK_BUS (0)

Definition at line 164 of file core.h.

#define DWC3_GCTL_CLK_MASK (3)

Definition at line 167 of file core.h.

#define DWC3_GCTL_CLK_PIPE (1)

Definition at line 165 of file core.h.

#define DWC3_GCTL_CLK_PIPEHALF (2)

Definition at line 166 of file core.h.

#define DWC3_GCTL_CORESOFTRESET (1 << 11)

Definition at line 175 of file core.h.

#define DWC3_GCTL_DISSCRAMBLE (1 << 3)

Definition at line 178 of file core.h.

#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)

Definition at line 180 of file core.h.

#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)

Definition at line 179 of file core.h.

#define DWC3_GCTL_PRTCAP ( n ) (((n) & (3 << 12)) >> 12)

Definition at line 169 of file core.h.

#define DWC3_GCTL_PRTCAP_DEVICE 2

Definition at line 172 of file core.h.

#define DWC3_GCTL_PRTCAP_HOST 1

Definition at line 171 of file core.h.

#define DWC3_GCTL_PRTCAP_OTG 3

Definition at line 173 of file core.h.

#define DWC3_GCTL_PRTCAPDIR ( n ) ((n) << 12)

Definition at line 170 of file core.h.

#define DWC3_GCTL_PWRDNSCALE ( n ) ((n) << 19)

Definition at line 161 of file core.h.

#define DWC3_GCTL_RAMCLKSEL ( x ) (((x) & DWC3_GCTL_CLK_MASK) << 6)

Definition at line 163 of file core.h.

#define DWC3_GCTL_SCALEDOWN ( n ) ((n) << 4)

Definition at line 176 of file core.h.

#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)

Definition at line 177 of file core.h.

#define DWC3_GCTL_U2RSTECN (1 << 16)

Definition at line 162 of file core.h.

#define DWC3_GDBGFIFOSPACE 0xc160

Definition at line 115 of file core.h.

#define DWC3_GDBGLTSSM 0xc164

Definition at line 116 of file core.h.

#define DWC3_GEVNTADRHI ( n ) (0xc404 + (n * 0x10))

Definition at line 133 of file core.h.

#define DWC3_GEVNTADRLO ( n ) (0xc400 + (n * 0x10))

Definition at line 132 of file core.h.

#define DWC3_GEVNTCOUNT ( n ) (0xc40c + (n * 0x10))

Definition at line 135 of file core.h.

#define DWC3_GEVNTCOUNT_MASK 0xfffc

Definition at line 77 of file core.h.

#define DWC3_GEVNTSIZ ( n ) (0xc408 + (n * 0x10))

Definition at line 134 of file core.h.

#define DWC3_GEVTEN 0xc114

Definition at line 97 of file core.h.

#define DWC3_GGPIO 0xc124

Definition at line 100 of file core.h.

#define DWC3_GHWPARAMS0 0xc140

Definition at line 107 of file core.h.

#define DWC3_GHWPARAMS1 0xc144

Definition at line 108 of file core.h.

#define DWC3_GHWPARAMS1_EN_PWROPT ( n ) (((n) & (3 << 24)) >> 24)

Definition at line 195 of file core.h.

#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1

Definition at line 197 of file core.h.

#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2

Definition at line 198 of file core.h.

#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0

Definition at line 196 of file core.h.

#define DWC3_GHWPARAMS1_PWROPT ( n ) ((n) << 24)

Definition at line 199 of file core.h.

#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)

Definition at line 200 of file core.h.

#define DWC3_GHWPARAMS2 0xc148

Definition at line 109 of file core.h.

#define DWC3_GHWPARAMS3 0xc14c

Definition at line 110 of file core.h.

#define DWC3_GHWPARAMS4 0xc150

Definition at line 111 of file core.h.

#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS ( n ) (((n) & (0x0f << 13)) >> 13)

Definition at line 203 of file core.h.

#define DWC3_GHWPARAMS5 0xc154

Definition at line 112 of file core.h.

#define DWC3_GHWPARAMS6 0xc158

Definition at line 113 of file core.h.

#define DWC3_GHWPARAMS7 0xc15c

Definition at line 114 of file core.h.

#define DWC3_GHWPARAMS8 0xc600

Definition at line 137 of file core.h.

#define DWC3_GLOBALS_REGS_END 0xc6ff

Definition at line 85 of file core.h.

#define DWC3_GLOBALS_REGS_START 0xc100

Definition at line 84 of file core.h.

#define DWC3_GPRTBIMAP0 0xc138

Definition at line 105 of file core.h.

#define DWC3_GPRTBIMAP1 0xc13c

Definition at line 106 of file core.h.

#define DWC3_GPRTBIMAP_FS0 0xc188

Definition at line 119 of file core.h.

#define DWC3_GPRTBIMAP_FS1 0xc18c

Definition at line 120 of file core.h.

#define DWC3_GPRTBIMAP_HS0 0xc180

Definition at line 117 of file core.h.

#define DWC3_GPRTBIMAP_HS1 0xc184

Definition at line 118 of file core.h.

#define DWC3_GRXFIFOSIZ ( n ) (0xc380 + (n * 0x04))

Definition at line 130 of file core.h.

#define DWC3_GRXTHRCFG 0xc10c

Definition at line 95 of file core.h.

#define DWC3_GSBUSCFG0 0xc100

Definition at line 92 of file core.h.

#define DWC3_GSBUSCFG1 0xc104

Definition at line 93 of file core.h.

#define DWC3_GSNPSID 0xc120

Definition at line 99 of file core.h.

#define DWC3_GSNPSID_MASK 0xffff0000

Definition at line 78 of file core.h.

#define DWC3_GSNPSREV_MASK 0xffff

Definition at line 79 of file core.h.

#define DWC3_GSTS 0xc118

Definition at line 98 of file core.h.

#define DWC3_GTXFIFOSIZ ( n ) (0xc300 + (n * 0x04))

Definition at line 129 of file core.h.

#define DWC3_GTXFIFOSIZ_TXFDEF ( n ) ((n) & 0xffff)

Definition at line 191 of file core.h.

#define DWC3_GTXFIFOSIZ_TXFSTADDR ( n ) ((n) & 0xffff0000)

Definition at line 192 of file core.h.

#define DWC3_GTXTHRCFG 0xc108

Definition at line 94 of file core.h.

#define DWC3_GUCTL 0xc12c

Definition at line 102 of file core.h.

#define DWC3_GUID 0xc128

Definition at line 101 of file core.h.

#define DWC3_GUSB2I2CCTL ( n ) (0xc240 + (n * 0x04))

Definition at line 123 of file core.h.

#define DWC3_GUSB2PHYACC ( n ) (0xc280 + (n * 0x04))

Definition at line 125 of file core.h.

#define DWC3_GUSB2PHYCFG ( n ) (0xc200 + (n * 0x04))

Definition at line 122 of file core.h.

#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)

Definition at line 183 of file core.h.

#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)

Definition at line 184 of file core.h.

#define DWC3_GUSB3PIPECTL ( n ) (0xc2c0 + (n * 0x04))

Definition at line 127 of file core.h.

#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)

Definition at line 187 of file core.h.

#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)

Definition at line 188 of file core.h.

#define DWC3_HAS_OTG BIT(3)

Definition at line 859 of file core.h.

#define DWC3_HAS_PERIPHERAL BIT(0)

Definition at line 857 of file core.h.

#define DWC3_HAS_XHCI BIT(1)

Definition at line 858 of file core.h.

#define DWC3_MAX_HIBER_SCRATCHBUFS 15

Definition at line 204 of file core.h.

#define DWC3_MDWIDTH ( n ) (((n) & 0xff00) >> 8)

Definition at line 572 of file core.h.

#define DWC3_MODE ( n ) ((n) & 0x7)

Definition at line 565 of file core.h.

#define DWC3_MODE_DEVICE 0

Definition at line 567 of file core.h.

#define DWC3_MODE_DRD 2

Definition at line 569 of file core.h.

#define DWC3_MODE_HOST 1

Definition at line 568 of file core.h.

#define DWC3_MODE_HUB 3

Definition at line 570 of file core.h.

#define DWC3_NUM_INT ( n ) (((n) & (0x3f << 15)) >> 15)

Definition at line 575 of file core.h.

#define DWC3_OCFG 0xcc00

Definition at line 153 of file core.h.

#define DWC3_OCTL 0xcc04

Definition at line 154 of file core.h.

#define DWC3_OEVTEN 0xcc08

Definition at line 155 of file core.h.

#define DWC3_OSTS 0xcc0C

Definition at line 156 of file core.h.

#define DWC3_OTG_REGS_END 0xccff

Definition at line 89 of file core.h.

#define DWC3_OTG_REGS_START 0xcc00

Definition at line 88 of file core.h.

#define DWC3_RAM1_DEPTH ( n ) ((n) & 0xffff)

Definition at line 578 of file core.h.

#define DWC3_REVISION_173A 0x5533173a

Definition at line 683 of file core.h.

#define DWC3_REVISION_175A 0x5533175a

Definition at line 684 of file core.h.

#define DWC3_REVISION_180A 0x5533180a

Definition at line 685 of file core.h.

#define DWC3_REVISION_183A 0x5533183a

Definition at line 686 of file core.h.

#define DWC3_REVISION_185A 0x5533185a

Definition at line 687 of file core.h.

#define DWC3_REVISION_187A 0x5533187a

Definition at line 688 of file core.h.

#define DWC3_REVISION_188A 0x5533188a

Definition at line 689 of file core.h.

#define DWC3_REVISION_190A 0x5533190a

Definition at line 690 of file core.h.

#define DWC3_REVISION_194A 0x5533194a

Definition at line 691 of file core.h.

#define DWC3_REVISION_200A 0x5533200a

Definition at line 692 of file core.h.

#define DWC3_REVISION_202A 0x5533202a

Definition at line 693 of file core.h.

#define DWC3_REVISION_210A 0x5533210a

Definition at line 694 of file core.h.

#define DWC3_REVISION_220A 0x5533220a

Definition at line 695 of file core.h.

#define DWC3_TRB_CTRL_CHN (1 << 2)

Definition at line 510 of file core.h.

#define DWC3_TRB_CTRL_CSP (1 << 3)

Definition at line 511 of file core.h.

#define DWC3_TRB_CTRL_HWO (1 << 0)

Definition at line 508 of file core.h.

#define DWC3_TRB_CTRL_IOC (1 << 11)

Definition at line 514 of file core.h.

#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)

Definition at line 513 of file core.h.

#define DWC3_TRB_CTRL_LST (1 << 1)

Definition at line 509 of file core.h.

#define DWC3_TRB_CTRL_SID_SOFN ( n ) (((n) & 0xffff) << 14)

Definition at line 515 of file core.h.

#define DWC3_TRB_CTRL_TRBCTL ( n ) (((n) & 0x3f) << 4)

Definition at line 512 of file core.h.

#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)

Definition at line 390 of file core.h.

#define DWC3_TRB_NUM 32

Definition at line 389 of file core.h.

#define DWC3_TRB_SIZE_LENGTH ( n ) ((n) & DWC3_TRB_SIZE_MASK)

Definition at line 498 of file core.h.

#define DWC3_TRB_SIZE_MASK (0x00ffffff)

Definition at line 497 of file core.h.

#define DWC3_TRB_SIZE_PCM1 ( n ) (((n) & 0x03) << 24)

Definition at line 499 of file core.h.

#define DWC3_TRB_SIZE_TRBSTS ( n ) (((n) & (0x0f << 28)) >> 28)

Definition at line 500 of file core.h.

#define DWC3_TRB_STS_XFER_IN_PROG 4

Definition at line 505 of file core.h.

#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)

Definition at line 521 of file core.h.

#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)

Definition at line 518 of file core.h.

#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)

Definition at line 519 of file core.h.

#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)

Definition at line 520 of file core.h.

#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)

Definition at line 523 of file core.h.

#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)

Definition at line 522 of file core.h.

#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)

Definition at line 524 of file core.h.

#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)

Definition at line 517 of file core.h.

#define DWC3_TRBSTS_MISSED_ISOC 1

Definition at line 503 of file core.h.

#define DWC3_TRBSTS_OK 0

Definition at line 502 of file core.h.

#define DWC3_TRBSTS_SETUP_PENDING 2

Definition at line 504 of file core.h.

#define DWC3_XHCI_REGS_END 0x7fff

Definition at line 83 of file core.h.

#define DWC3_XHCI_REGS_START 0x0

Definition at line 82 of file core.h.

#define DWC3_XHCI_RESOURCES_NUM 2

Definition at line 56 of file core.h.

Enumeration Type Documentation

enum dwc3_device_state

Enumerator:

DWC3_DEFAULT_STATE
DWC3_ADDRESS_STATE
DWC3_CONFIGURED_STATE

Definition at line 490 of file core.h.

enum dwc3_ep0_next

Enumerator:

DWC3_EP0_UNKNOWN
DWC3_EP0_COMPLETE
DWC3_EP0_NRDY_DATA
DWC3_EP0_NRDY_STATUS

Definition at line 457 of file core.h.

enum dwc3_ep0_state

Enumerator:

EP0_UNCONNECTED
EP0_SETUP_PHASE
EP0_DATA_PHASE
EP0_STATUS_PHASE

Definition at line 464 of file core.h.

enum dwc3_link_state

Enumerator:

DWC3_LINK_STATE_U0
DWC3_LINK_STATE_U1
DWC3_LINK_STATE_U2
DWC3_LINK_STATE_U3
DWC3_LINK_STATE_SS_DIS
DWC3_LINK_STATE_RX_DET
DWC3_LINK_STATE_SS_INACT
DWC3_LINK_STATE_POLL
DWC3_LINK_STATE_RECOV
DWC3_LINK_STATE_HRESET
DWC3_LINK_STATE_CMPLY
DWC3_LINK_STATE_LPBK
DWC3_LINK_STATE_RESET
DWC3_LINK_STATE_RESUME
DWC3_LINK_STATE_MASK

Definition at line 471 of file core.h.

enum dwc3_phy

Enumerator:

DWC3_PHY_UNKNOWN
DWC3_PHY_USB3
DWC3_PHY_USB2

Definition at line 451 of file core.h.

Function Documentation

void dwc3_gadget_exit ( struct dwc3 * dwc )

Definition at line 2527 of file gadget.c.

int dwc3_gadget_init ( struct dwc3 * dwc )

dwc3_gadget_init - Initializes gadget related registers : pointer to our controller context structure

Returns 0 on success otherwise negative errno.

Definition at line 2377 of file gadget.c.

int dwc3_gadget_resize_tx_fifos ( struct dwc3 * dwc )

dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case : pointer to our context structure

This function will a best effort FIFO allocation in order to improve FIFO usage and throughput, while still allowing us to enable as many endpoints as possible.

Keep in mind that this operation will be highly dependent on the configured size for RAM1 - which contains TxFifo -, the amount of endpoints enabled on coreConsultant tool, and the width of the Master Bus.

In the ideal world, we would always be able to satisfy the following equation:

((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes

Unfortunately, due to many variables that's not always the case.

Definition at line 171 of file gadget.c.

int dwc3_get_device_id ( void )

Definition at line 73 of file core.c.

void dwc3_host_exit ( struct dwc3 * dwc )

Definition at line 84 of file host.c.

int dwc3_host_init ( struct dwc3 * dwc )

host.c - DesignWare USB3 DRD Controller Host Glue

Authors: Felipe Balbi balbi.nosp@m.@ti..nosp@m.com,

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer, without modification.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of the above-listed copyright holders may not be used to endorse or promote products derived from this software without specific prior written permission.

ALTERNATIVELY, this software may be distributed under the terms of the GNU General Public License ("GPL") version 2, as published by the Free Software Foundation.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition at line 42 of file host.c.

void dwc3_put_device_id ( int id )

Definition at line 94 of file core.c.

void dwc3_set_mode	(	struct dwc3 *	dwc,
		u32	mode
	)

Definition at line 108 of file core.c.

Variable Documentation

struct dwc3_event_gevt __packed

Data Structures

Macros

: a human readable name e.g. ep1out-bulk

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation