#include <linux/dw_dmac.h>

Data Structures
struct	dw_dma_chan_regs

struct	dw_dma_irq_regs

struct	dw_dma_regs

struct	dw_dma_chan

struct	dw_dma

struct	dw_lli

struct	dw_desc

Macros
#define	DW_DMA_MAX_NR_CHANNELS 8

#define	DW_REG(name) u32 name; u32 __pad_##name

#define	dma_readl_native readl

#define	dma_writel_native writel

#define	dma_read_byaddr(addr, name) dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))

#define	DW_PARAMS_NR_CHAN 8 /* number of channels */

#define	DW_PARAMS_NR_MASTER 11 /* number of AHB masters */

#define	DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))

#define	DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */

#define	DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */

#define	DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */

#define	DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */

#define	DW_PARAMS_EN 28 /* encoded parameters */

#define	DWC_PARAMS_MBLK_EN 11 /* multi block transfer */

#define	DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */

#define	DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */

#define	DWC_CTLL_SRC_WIDTH(n) ((n)<<4)

#define	DWC_CTLL_DST_INC (0<<7) /* DAR update/not */

#define	DWC_CTLL_DST_DEC (1<<7)

#define	DWC_CTLL_DST_FIX (2<<7)

#define	DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */

#define	DWC_CTLL_SRC_DEC (1<<9)

#define	DWC_CTLL_SRC_FIX (2<<9)

#define	DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */

#define	DWC_CTLL_SRC_MSIZE(n) ((n)<<14)

#define	DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */

#define	DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */

#define	DWC_CTLL_FC(n) ((n) << 20)

#define	DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */

#define	DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */

#define	DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */

#define	DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */

#define	DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */

#define	DWC_CTLL_SMS(n) ((n)<<25) /* src master select */

#define	DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */

#define	DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */

#define	DWC_CTLH_DONE 0x00001000

#define	DWC_CTLH_BLOCK_TS_MASK 0x00000fff

#define	DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */

#define	DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */

#define	DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */

#define	DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */

#define	DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */

#define	DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */

#define	DWC_CFGL_MAX_BURST(x) ((x) << 20)

#define	DWC_CFGL_RELOAD_SAR (1 << 30)

#define	DWC_CFGL_RELOAD_DAR (1 << 31)

#define	DWC_CFGH_DS_UPD_EN (1 << 5)

#define	DWC_CFGH_SS_UPD_EN (1 << 6)

#define	DWC_SGR_SGI(x) ((x) << 0)

#define	DWC_SGR_SGC(x) ((x) << 20)

#define	DWC_DSR_DSI(x) ((x) << 0)

#define	DWC_DSR_DSC(x) ((x) << 20)

#define	DW_CFG_DMA_EN (1 << 0)

#define	channel_readl(dwc, name) dma_readl_native(&(__dwc_regs(dwc)->name))

#define	channel_writel(dwc, name, val) dma_writel_native((val), &(__dwc_regs(dwc)->name))

#define	dma_readl(dw, name) dma_readl_native(&(__dw_regs(dw)->name))

#define	dma_writel(dw, name, val) dma_writel_native((val), &(__dw_regs(dw)->name))

#define	channel_set_bit(dw, reg, mask) dma_writel(dw, reg, ((mask) << 8) \| (mask))

#define	channel_clear_bit(dw, reg, mask) dma_writel(dw, reg, ((mask) << 8) \| 0)

Enumerations
enum	dw_dma_fc { DW_DMA_FC_D_M2M, DW_DMA_FC_D_M2P, DW_DMA_FC_D_P2M, DW_DMA_FC_D_P2P, DW_DMA_FC_P_P2M, DW_DMA_FC_SP_P2P, DW_DMA_FC_P_M2P, DW_DMA_FC_DP_P2P }

enum	dw_dmac_flags { DW_DMA_IS_CYCLIC = 0, DW_DMA_IS_SOFT_LLP = 1 }

Macro Definition Documentation

#define channel_clear_bit	(	dw,
		reg,
		mask
	)	dma_writel(dw, reg, ((mask) << 8) \| 0)

Definition at line 263 of file dw_dmac_regs.h.

#define channel_readl	(	dwc,
		name
	)	dma_readl_native(&(__dwc_regs(dwc)->name))

Definition at line 226 of file dw_dmac_regs.h.

#define channel_set_bit	(	dw,
		reg,
		mask
	)	dma_writel(dw, reg, ((mask) << 8) \| (mask))

Definition at line 261 of file dw_dmac_regs.h.

#define channel_writel	(	dwc,
		name,
		val
	)	dma_writel_native((val), &(__dwc_regs(dwc)->name))

Definition at line 228 of file dw_dmac_regs.h.

#define dma_read_byaddr	(	addr,
		name
	)	dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))

Definition at line 110 of file dw_dmac_regs.h.

#define dma_readl	(	dw,
		name
	)	dma_readl_native(&(__dw_regs(dw)->name))

Definition at line 256 of file dw_dmac_regs.h.

#define dma_readl_native readl

Definition at line 105 of file dw_dmac_regs.h.

#define dma_writel	(	dw,
		name,
		val
	)	dma_writel_native((val), &(__dw_regs(dw)->name))

Definition at line 258 of file dw_dmac_regs.h.

#define dma_writel_native writel

Definition at line 106 of file dw_dmac_regs.h.

#define DW_CFG_DMA_EN (1 << 0)

Definition at line 179 of file dw_dmac_regs.h.

#define DW_DMA_MAX_NR_CHANNELS 8

Definition at line 14 of file dw_dmac_regs.h.

#define DW_PARAMS_DATA_WIDTH ( n ) (15 + 2 * (n))

Definition at line 116 of file dw_dmac_regs.h.

#define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */

Definition at line 117 of file dw_dmac_regs.h.

#define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */

Definition at line 118 of file dw_dmac_regs.h.

#define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */

Definition at line 119 of file dw_dmac_regs.h.

#define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */

Definition at line 120 of file dw_dmac_regs.h.

#define DW_PARAMS_EN 28 /* encoded parameters */

Definition at line 121 of file dw_dmac_regs.h.

#define DW_PARAMS_NR_CHAN 8 /* number of channels */

Definition at line 114 of file dw_dmac_regs.h.

#define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */

Definition at line 115 of file dw_dmac_regs.h.

#define DW_REG ( name ) u32 name; u32 __pad_##name

Definition at line 32 of file dw_dmac_regs.h.

#define DWC_CFGH_DS_UPD_EN (1 << 5)

Definition at line 167 of file dw_dmac_regs.h.

#define DWC_CFGH_SS_UPD_EN (1 << 6)

Definition at line 168 of file dw_dmac_regs.h.

#define DWC_CFGL_CH_PRIOR ( x ) ((x) << 5) /* priority */

Definition at line 157 of file dw_dmac_regs.h.

#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */

Definition at line 156 of file dw_dmac_regs.h.

#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */

Definition at line 158 of file dw_dmac_regs.h.

#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */

Definition at line 159 of file dw_dmac_regs.h.

#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */

Definition at line 160 of file dw_dmac_regs.h.

#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */

Definition at line 161 of file dw_dmac_regs.h.

#define DWC_CFGL_MAX_BURST ( x ) ((x) << 20)

Definition at line 162 of file dw_dmac_regs.h.

#define DWC_CFGL_RELOAD_DAR (1 << 31)

Definition at line 164 of file dw_dmac_regs.h.

#define DWC_CFGL_RELOAD_SAR (1 << 30)

Definition at line 163 of file dw_dmac_regs.h.

#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff

Definition at line 153 of file dw_dmac_regs.h.

#define DWC_CTLH_DONE 0x00001000

Definition at line 152 of file dw_dmac_regs.h.

#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */

Definition at line 139 of file dw_dmac_regs.h.

#define DWC_CTLL_DMS ( n ) ((n)<<23) /* dst master select */

Definition at line 146 of file dw_dmac_regs.h.

#define DWC_CTLL_DST_DEC (1<<7)

Definition at line 131 of file dw_dmac_regs.h.

#define DWC_CTLL_DST_FIX (2<<7)

Definition at line 132 of file dw_dmac_regs.h.

#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */

Definition at line 130 of file dw_dmac_regs.h.

#define DWC_CTLL_DST_MSIZE ( n ) ((n)<<11) /* burst, #elements */

Definition at line 136 of file dw_dmac_regs.h.

#define DWC_CTLL_DST_WIDTH ( n ) ((n)<<1) /* bytes per element */

Definition at line 128 of file dw_dmac_regs.h.

#define DWC_CTLL_FC ( n ) ((n) << 20)

Definition at line 140 of file dw_dmac_regs.h.

#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */

Definition at line 141 of file dw_dmac_regs.h.

#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */

Definition at line 142 of file dw_dmac_regs.h.

#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */

Definition at line 143 of file dw_dmac_regs.h.

#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */

Definition at line 144 of file dw_dmac_regs.h.

#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */

Definition at line 127 of file dw_dmac_regs.h.

#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */

Definition at line 148 of file dw_dmac_regs.h.

#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */

Definition at line 149 of file dw_dmac_regs.h.

#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */

Definition at line 138 of file dw_dmac_regs.h.

#define DWC_CTLL_SMS ( n ) ((n)<<25) /* src master select */

Definition at line 147 of file dw_dmac_regs.h.

#define DWC_CTLL_SRC_DEC (1<<9)

Definition at line 134 of file dw_dmac_regs.h.

#define DWC_CTLL_SRC_FIX (2<<9)

Definition at line 135 of file dw_dmac_regs.h.

#define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */

Definition at line 133 of file dw_dmac_regs.h.

#define DWC_CTLL_SRC_MSIZE ( n ) ((n)<<14)

Definition at line 137 of file dw_dmac_regs.h.

#define DWC_CTLL_SRC_WIDTH ( n ) ((n)<<4)

Definition at line 129 of file dw_dmac_regs.h.

#define DWC_DSR_DSC ( x ) ((x) << 20)

Definition at line 176 of file dw_dmac_regs.h.

#define DWC_DSR_DSI ( x ) ((x) << 0)

Definition at line 175 of file dw_dmac_regs.h.

#define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */

Definition at line 124 of file dw_dmac_regs.h.

#define DWC_SGR_SGC ( x ) ((x) << 20)

Definition at line 172 of file dw_dmac_regs.h.

#define DWC_SGR_SGI ( x ) ((x) << 0)

Definition at line 171 of file dw_dmac_regs.h.

Enumeration Type Documentation

enum dw_dma_fc

Enumerator:

DW_DMA_FC_D_M2M
DW_DMA_FC_D_M2P
DW_DMA_FC_D_P2M
DW_DMA_FC_D_P2P
DW_DMA_FC_P_P2M
DW_DMA_FC_SP_P2P
DW_DMA_FC_P_M2P
DW_DMA_FC_DP_P2P

Definition at line 17 of file dw_dmac_regs.h.

enum dw_dmac_flags

Enumerator:

DW_DMA_IS_CYCLIC
DW_DMA_IS_SOFT_LLP

Definition at line 181 of file dw_dmac_regs.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation