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#define | XHCI_SBRN_OFFSET (0x60) |
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#define | MAX_HC_SLOTS 256 |
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#define | MAX_HC_PORTS 127 |
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#define | HC_LENGTH(p) XHCI_HC_LENGTH(p) |
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#define | HC_VERSION(p) (((p) >> 16) & 0xffff) |
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#define | HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) |
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#define | HCS_SLOTS_MASK 0xff |
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#define | HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) |
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#define | HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) |
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#define | HCS_IST(p) (((p) >> 0) & 0xf) |
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#define | HCS_ERST_MAX(p) (((p) >> 4) & 0xf) |
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#define | HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) |
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#define | HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) |
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#define | HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) |
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#define | HCC_64BIT_ADDR(p) ((p) & (1 << 0)) |
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#define | HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) |
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#define | HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) |
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#define | HCC_PPC(p) ((p) & (1 << 3)) |
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#define | HCS_INDICATOR(p) ((p) & (1 << 4)) |
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#define | HCC_LIGHT_RESET(p) ((p) & (1 << 5)) |
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#define | HCC_LTC(p) ((p) & (1 << 6)) |
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#define | HCC_NSS(p) ((p) & (1 << 7)) |
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#define | HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) |
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#define | HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) |
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#define | DBOFF_MASK (~0x3) |
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#define | RTSOFF_MASK (~0x1f) |
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#define | NUM_PORT_REGS 4 |
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#define | CMD_RUN XHCI_CMD_RUN |
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#define | CMD_RESET (1 << 1) |
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#define | CMD_EIE XHCI_CMD_EIE |
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#define | CMD_HSEIE XHCI_CMD_HSEIE |
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#define | CMD_LRESET (1 << 7) |
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#define | CMD_CSS (1 << 8) |
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#define | CMD_CRS (1 << 9) |
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#define | CMD_EWE XHCI_CMD_EWE |
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#define | CMD_PM_INDEX (1 << 11) |
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#define | IMAN_IP (1 << 1) |
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#define | IMAN_IE (1 << 0) |
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#define | STS_HALT XHCI_STS_HALT |
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#define | STS_FATAL (1 << 2) |
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#define | STS_EINT (1 << 3) |
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#define | STS_PORT (1 << 4) |
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#define | STS_SAVE (1 << 8) |
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#define | STS_RESTORE (1 << 9) |
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#define | STS_SRE (1 << 10) |
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#define | STS_CNR XHCI_STS_CNR |
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#define | STS_HCE (1 << 12) |
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#define | DEV_NOTE_MASK (0xffff) |
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#define | ENABLE_DEV_NOTE(x) (1 << (x)) |
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#define | DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) |
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#define | CMD_RING_PAUSE (1 << 1) |
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#define | CMD_RING_ABORT (1 << 2) |
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#define | CMD_RING_RUNNING (1 << 3) |
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#define | CMD_RING_RSVD_BITS (0x3f) |
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#define | MAX_DEVS(p) ((p) & 0xff) |
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#define | PORT_CONNECT (1 << 0) |
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#define | PORT_PE (1 << 1) |
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#define | PORT_OC (1 << 3) |
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#define | PORT_RESET (1 << 4) |
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#define | PORT_PLS_MASK (0xf << 5) |
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#define | XDEV_U0 (0x0 << 5) |
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#define | XDEV_U2 (0x2 << 5) |
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#define | XDEV_U3 (0x3 << 5) |
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#define | XDEV_RESUME (0xf << 5) |
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#define | PORT_POWER (1 << 9) |
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#define | DEV_SPEED_MASK (0xf << 10) |
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#define | XDEV_FS (0x1 << 10) |
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#define | XDEV_LS (0x2 << 10) |
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#define | XDEV_HS (0x3 << 10) |
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#define | XDEV_SS (0x4 << 10) |
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#define | DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) |
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#define | DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) |
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#define | DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) |
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#define | DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) |
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#define | DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) |
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#define | SLOT_SPEED_FS (XDEV_FS << 10) |
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#define | SLOT_SPEED_LS (XDEV_LS << 10) |
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#define | SLOT_SPEED_HS (XDEV_HS << 10) |
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#define | SLOT_SPEED_SS (XDEV_SS << 10) |
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#define | PORT_LED_OFF (0 << 14) |
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#define | PORT_LED_AMBER (1 << 14) |
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#define | PORT_LED_GREEN (2 << 14) |
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#define | PORT_LED_MASK (3 << 14) |
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#define | PORT_LINK_STROBE (1 << 16) |
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#define | PORT_CSC (1 << 17) |
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#define | PORT_PEC (1 << 18) |
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#define | PORT_WRC (1 << 19) |
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#define | PORT_OCC (1 << 20) |
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#define | PORT_RC (1 << 21) |
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#define | PORT_PLC (1 << 22) |
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#define | PORT_CEC (1 << 23) |
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#define | PORT_CAS (1 << 24) |
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#define | PORT_WKCONN_E (1 << 25) |
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#define | PORT_WKDISC_E (1 << 26) |
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#define | PORT_WKOC_E (1 << 27) |
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#define | PORT_DEV_REMOVE (1 << 30) |
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#define | PORT_WR (1 << 31) |
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#define | DUPLICATE_ENTRY ((u8)(-1)) |
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#define | PORT_U1_TIMEOUT(p) ((p) & 0xff) |
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#define | PORT_U1_TIMEOUT_MASK 0xff |
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#define | PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) |
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#define | PORT_U2_TIMEOUT_MASK (0xff << 8) |
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#define | PORT_L1S_MASK 7 |
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#define | PORT_L1S_SUCCESS 1 |
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#define | PORT_RWE (1 << 3) |
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#define | PORT_HIRD(p) (((p) & 0xf) << 4) |
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#define | PORT_HIRD_MASK (0xf << 4) |
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#define | PORT_L1DS(p) (((p) & 0xff) << 8) |
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#define | PORT_HLE (1 << 16) |
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#define | ER_IRQ_PENDING(p) ((p) & 0x1) |
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#define | ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) |
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#define | ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) |
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#define | ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) |
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#define | ER_IRQ_INTERVAL_MASK (0xffff) |
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#define | ER_IRQ_COUNTER_MASK (0xffff << 16) |
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#define | ERST_SIZE_MASK (0xffff << 16) |
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#define | ERST_DESI_MASK (0x7) |
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#define | ERST_EHB (1 << 3) |
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#define | ERST_PTR_MASK (0xf) |
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#define | DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) |
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#define | DB_VALUE_HOST 0x00000000 |
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#define | XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) |
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#define | XHCI_EXT_PORT_OFF(x) ((x) & 0xff) |
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#define | XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) |
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#define | XHCI_CTX_TYPE_DEVICE 0x1 |
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#define | XHCI_CTX_TYPE_INPUT 0x2 |
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#define | ROUTE_STRING_MASK (0xfffff) |
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#define | DEV_SPEED (0xf << 20) |
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#define | DEV_MTT (0x1 << 25) |
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#define | DEV_HUB (0x1 << 26) |
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#define | LAST_CTX_MASK (0x1f << 27) |
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#define | LAST_CTX(p) ((p) << 27) |
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#define | LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) |
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#define | SLOT_FLAG (1 << 0) |
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#define | EP0_FLAG (1 << 1) |
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#define | MAX_EXIT (0xffff) |
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#define | ROOT_HUB_PORT(p) (((p) & 0xff) << 16) |
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#define | DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) |
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#define | XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) |
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#define | TT_SLOT (0xff) |
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#define | TT_PORT (0xff << 8) |
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#define | TT_THINK_TIME(p) (((p) & 0x3) << 16) |
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#define | DEV_ADDR_MASK (0xff) |
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#define | SLOT_STATE (0x1f << 27) |
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#define | GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) |
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#define | SLOT_STATE_DISABLED 0 |
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#define | SLOT_STATE_ENABLED SLOT_STATE_DISABLED |
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#define | SLOT_STATE_DEFAULT 1 |
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#define | SLOT_STATE_ADDRESSED 2 |
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#define | SLOT_STATE_CONFIGURED 3 |
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#define | EP_STATE_MASK (0xf) |
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#define | EP_STATE_DISABLED 0 |
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#define | EP_STATE_RUNNING 1 |
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#define | EP_STATE_HALTED 2 |
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#define | EP_STATE_STOPPED 3 |
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#define | EP_STATE_ERROR 4 |
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#define | EP_MULT(p) (((p) & 0x3) << 8) |
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#define | CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) |
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#define | EP_INTERVAL(p) (((p) & 0xff) << 16) |
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#define | EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) |
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#define | CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) |
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#define | EP_MAXPSTREAMS_MASK (0x1f << 10) |
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#define | EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) |
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#define | EP_HAS_LSA (1 << 15) |
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#define | FORCE_EVENT (0x1) |
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#define | ERROR_COUNT(p) (((p) & 0x3) << 1) |
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#define | CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) |
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#define | EP_TYPE(p) ((p) << 3) |
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#define | ISOC_OUT_EP 1 |
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#define | BULK_OUT_EP 2 |
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#define | INT_OUT_EP 3 |
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#define | CTRL_EP 4 |
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#define | ISOC_IN_EP 5 |
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#define | BULK_IN_EP 6 |
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#define | INT_IN_EP 7 |
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#define | MAX_BURST(p) (((p)&0xff) << 8) |
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#define | CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) |
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#define | MAX_PACKET(p) (((p)&0xffff) << 16) |
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#define | MAX_PACKET_MASK (0xffff << 16) |
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#define | MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) |
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#define | GET_MAX_PACKET(p) ((p) & 0x7ff) |
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#define | AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) |
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#define | MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) |
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#define | CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) |
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#define | EP_CTX_CYCLE_MASK (1 << 0) |
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#define | EP_IS_ADDED(ctrl_ctx, i) (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) |
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#define | EP_IS_DROPPED(ctrl_ctx, i) (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) |
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#define | DROP_EP(x) (0x1 << x) |
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#define | ADD_EP(x) (0x1 << x) |
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#define | SCT_FOR_CTX(p) (((p) << 1) & 0x7) |
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#define | SCT_SEC_TR 0 |
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#define | SCT_PRI_TR 1 |
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#define | SCT_SSA_8 2 |
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#define | SCT_SSA_16 3 |
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#define | SCT_SSA_32 4 |
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#define | SCT_SSA_64 5 |
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#define | SCT_SSA_128 6 |
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#define | SCT_SSA_256 7 |
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#define | SMALL_STREAM_ARRAY_SIZE 256 |
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#define | MEDIUM_STREAM_ARRAY_SIZE 1024 |
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#define | FS_BLOCK 1 |
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#define | HS_BLOCK 4 |
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#define | SS_BLOCK 16 |
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#define | DMI_BLOCK 32 |
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#define | DMI_OVERHEAD 8 |
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#define | DMI_OVERHEAD_BURST 4 |
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#define | SS_OVERHEAD 8 |
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#define | SS_OVERHEAD_BURST 32 |
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#define | HS_OVERHEAD 26 |
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#define | FS_OVERHEAD 20 |
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#define | LS_OVERHEAD 128 |
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#define | TT_HS_OVERHEAD (31 + 94) |
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#define | TT_DMI_OVERHEAD (25 + 12) |
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#define | FS_BW_LIMIT 1285 |
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#define | TT_BW_LIMIT 1320 |
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#define | HS_BW_LIMIT 1607 |
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#define | SS_BW_LIMIT_IN 3906 |
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#define | DMI_BW_LIMIT_IN 3906 |
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#define | SS_BW_LIMIT_OUT 3906 |
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#define | DMI_BW_LIMIT_OUT 3906 |
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#define | FS_BW_RESERVED 10 |
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#define | HS_BW_RESERVED 20 |
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#define | SS_BW_RESERVED 10 |
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#define | SET_DEQ_PENDING (1 << 0) |
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#define | EP_HALTED (1 << 1) /* For stall handling */ |
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#define | EP_HALT_PENDING (1 << 2) /* For URB cancellation */ |
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#define | EP_GETTING_STREAMS (1 << 3) |
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#define | EP_HAS_STREAMS (1 << 4) |
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#define | EP_GETTING_NO_STREAMS (1 << 5) |
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#define | XHCI_MAX_INTERVAL 16 |
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#define | XHCI_MAX_RINGS_CACHED 31 |
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#define | TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) |
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#define | COMP_CODE_MASK (0xff << 24) |
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#define | GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) |
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#define | COMP_SUCCESS 1 |
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#define | COMP_DB_ERR 2 |
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#define | COMP_BABBLE 3 |
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#define | COMP_TX_ERR 4 |
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#define | COMP_TRB_ERR 5 |
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#define | COMP_STALL 6 |
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#define | COMP_ENOMEM 7 |
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#define | COMP_BW_ERR 8 |
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#define | COMP_ENOSLOTS 9 |
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#define | COMP_STREAM_ERR 10 |
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#define | COMP_EBADSLT 11 |
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#define | COMP_EBADEP 12 |
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#define | COMP_SHORT_TX 13 |
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#define | COMP_UNDERRUN 14 |
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#define | COMP_OVERRUN 15 |
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#define | COMP_VF_FULL 16 |
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#define | COMP_EINVAL 17 |
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#define | COMP_BW_OVER 18 |
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#define | COMP_CTX_STATE 19 |
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#define | COMP_PING_ERR 20 |
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#define | COMP_ER_FULL 21 |
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#define | COMP_DEV_ERR 22 |
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#define | COMP_MISSED_INT 23 |
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#define | COMP_CMD_STOP 24 |
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#define | COMP_CMD_ABORT 25 |
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#define | COMP_STOP 26 |
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#define | COMP_STOP_INVAL 27 |
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#define | COMP_DBG_ABORT 28 |
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#define | COMP_MEL_ERR 29 |
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#define | COMP_BUFF_OVER 31 |
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#define | COMP_ISSUES 32 |
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#define | COMP_UNKNOWN 33 |
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#define | COMP_STRID_ERR 34 |
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#define | COMP_2ND_BW_ERR 35 |
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#define | COMP_SPLIT_ERR 36 |
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#define | LINK_TOGGLE (0x1<<1) |
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#define | TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) |
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#define | SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) |
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#define | TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) |
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#define | EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) |
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#define | SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) |
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#define | TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) |
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#define | LAST_EP_INDEX 30 |
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#define | TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) |
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#define | STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) |
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#define | GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) |
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#define | TRB_LEN(p) ((p) & 0x1ffff) |
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#define | TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) |
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#define | GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) |
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#define | TRB_TBC(p) (((p) & 0x3) << 7) |
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#define | TRB_TLBPC(p) (((p) & 0xf) << 16) |
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#define | TRB_CYCLE (1<<0) |
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#define | TRB_ENT (1<<1) |
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#define | TRB_ISP (1<<2) |
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#define | TRB_NO_SNOOP (1<<3) |
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#define | TRB_CHAIN (1<<4) |
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#define | TRB_IOC (1<<5) |
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#define | TRB_IDT (1<<6) |
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#define | TRB_BEI (1<<9) |
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#define | TRB_DIR_IN (1<<16) |
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#define | TRB_TX_TYPE(p) ((p) << 16) |
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#define | TRB_DATA_OUT 2 |
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#define | TRB_DATA_IN 3 |
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#define | TRB_SIA (1<<31) |
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#define | TRB_TYPE_BITMASK (0xfc00) |
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#define | TRB_TYPE(p) ((p) << 10) |
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#define | TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) |
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#define | TRB_NORMAL 1 |
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#define | TRB_SETUP 2 |
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#define | TRB_DATA 3 |
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#define | TRB_STATUS 4 |
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#define | TRB_ISOC 5 |
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#define | TRB_LINK 6 |
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#define | TRB_EVENT_DATA 7 |
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#define | TRB_TR_NOOP 8 |
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#define | TRB_ENABLE_SLOT 9 |
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#define | TRB_DISABLE_SLOT 10 |
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#define | TRB_ADDR_DEV 11 |
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#define | TRB_CONFIG_EP 12 |
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#define | TRB_EVAL_CONTEXT 13 |
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#define | TRB_RESET_EP 14 |
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#define | TRB_STOP_RING 15 |
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#define | TRB_SET_DEQ 16 |
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#define | TRB_RESET_DEV 17 |
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#define | TRB_FORCE_EVENT 18 |
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#define | TRB_NEG_BANDWIDTH 19 |
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#define | TRB_SET_LT 20 |
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#define | TRB_GET_BW 21 |
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#define | TRB_FORCE_HEADER 22 |
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#define | TRB_CMD_NOOP 23 |
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#define | TRB_TRANSFER 32 |
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#define | TRB_COMPLETION 33 |
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#define | TRB_PORT_STATUS 34 |
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#define | TRB_BANDWIDTH_EVENT 35 |
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#define | TRB_DOORBELL 36 |
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#define | TRB_HC_EVENT 37 |
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#define | TRB_DEV_NOTE 38 |
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#define | TRB_MFINDEX_WRAP 39 |
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#define | TRB_NEC_CMD_COMP 48 |
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#define | TRB_NEC_GET_FW 49 |
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#define | TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) |
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#define | TRB_TYPE_LINK_LE32(x) |
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#define | TRB_TYPE_NOOP_LE32(x) |
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#define | NEC_FW_MINOR(p) (((p) >> 0) & 0xff) |
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#define | NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) |
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#define | TRBS_PER_SEGMENT 64 |
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#define | MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) |
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#define | SEGMENT_SIZE (TRBS_PER_SEGMENT*16) |
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#define | SEGMENT_SHIFT (__ffs(SEGMENT_SIZE)) |
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#define | TRB_MAX_BUFF_SHIFT 16 |
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#define | TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) |
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#define | XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) |
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#define | ERST_NUM_SEGS 1 |
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#define | ERST_SIZE 64 |
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#define | ERST_ENTRIES 1 |
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#define | POLL_TIMEOUT 60 |
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#define | XHCI_STOP_EP_CMD_TIMEOUT 5 |
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#define | CMD_RING_STATE_RUNNING (1 << 0) |
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#define | CMD_RING_STATE_ABORTED (1 << 1) |
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#define | CMD_RING_STATE_STOPPED (1 << 2) |
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#define | XHCI_STATE_DYING (1 << 0) |
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#define | XHCI_STATE_HALTED (1 << 1) |
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#define | XHCI_LINK_TRB_QUIRK (1 << 0) |
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#define | XHCI_RESET_EP_QUIRK (1 << 1) |
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#define | XHCI_NEC_HOST (1 << 2) |
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#define | XHCI_AMD_PLL_FIX (1 << 3) |
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#define | XHCI_SPURIOUS_SUCCESS (1 << 4) |
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#define | XHCI_EP_LIMIT_QUIRK (1 << 5) |
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#define | XHCI_BROKEN_MSI (1 << 6) |
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#define | XHCI_RESET_ON_RESUME (1 << 7) |
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#define | XHCI_SW_BW_CHECKING (1 << 8) |
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#define | XHCI_AMD_0x96_HOST (1 << 9) |
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#define | XHCI_TRUST_TX_LENGTH (1 << 10) |
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#define | XHCI_LPM_SUPPORT (1 << 11) |
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#define | XHCI_INTEL_HOST (1 << 12) |
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#define | XHCI_SPURIOUS_REBOOT (1 << 13) |
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#define | XHCI_COMP_MODE_QUIRK (1 << 14) |
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#define | XHCI_AVOID_BEI (1 << 15) |
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#define | COMP_MODE_RCVRY_MSECS 2000 |
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#define | XHCI_DEBUG 0 |
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#define | xhci_dbg(xhci, fmt, args...) do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) |
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#define | xhci_info(xhci, fmt, args...) do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) |
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#define | xhci_err(xhci, fmt, args...) dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
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#define | xhci_warn(xhci, fmt, args...) dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
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#define | xhci_warn_ratelimited(xhci, fmt, args...) dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
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#define | xhci_suspend NULL |
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#define | xhci_resume NULL |
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#define | xhci_bus_suspend NULL |
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#define | xhci_bus_resume NULL |
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void | xhci_print_ir_set (struct xhci_hcd *xhci, int set_num) |
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void | xhci_print_registers (struct xhci_hcd *xhci) |
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void | xhci_dbg_regs (struct xhci_hcd *xhci) |
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void | xhci_print_run_regs (struct xhci_hcd *xhci) |
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void | xhci_print_trb_offsets (struct xhci_hcd *xhci, union xhci_trb *trb) |
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void | xhci_debug_trb (struct xhci_hcd *xhci, union xhci_trb *trb) |
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void | xhci_debug_segment (struct xhci_hcd *xhci, struct xhci_segment *seg) |
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void | xhci_debug_ring (struct xhci_hcd *xhci, struct xhci_ring *ring) |
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void | xhci_dbg_erst (struct xhci_hcd *xhci, struct xhci_erst *erst) |
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void | xhci_dbg_cmd_ptrs (struct xhci_hcd *xhci) |
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void | xhci_dbg_ring_ptrs (struct xhci_hcd *xhci, struct xhci_ring *ring) |
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void | xhci_dbg_ctx (struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep) |
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char * | xhci_get_slot_state (struct xhci_hcd *xhci, struct xhci_container_ctx *ctx) |
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void | xhci_dbg_ep_rings (struct xhci_hcd *xhci, unsigned int slot_id, unsigned int ep_index, struct xhci_virt_ep *ep) |
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void | xhci_mem_cleanup (struct xhci_hcd *xhci) |
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int | xhci_mem_init (struct xhci_hcd *xhci, gfp_t flags) |
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void | xhci_free_virt_device (struct xhci_hcd *xhci, int slot_id) |
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int | xhci_alloc_virt_device (struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags) |
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int | xhci_setup_addressable_virt_dev (struct xhci_hcd *xhci, struct usb_device *udev) |
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void | xhci_copy_ep0_dequeue_into_input_ctx (struct xhci_hcd *xhci, struct usb_device *udev) |
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unsigned int | xhci_get_endpoint_index (struct usb_endpoint_descriptor *desc) |
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unsigned int | xhci_get_endpoint_flag (struct usb_endpoint_descriptor *desc) |
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unsigned int | xhci_get_endpoint_flag_from_index (unsigned int ep_index) |
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unsigned int | xhci_last_valid_endpoint (u32 added_ctxs) |
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void | xhci_endpoint_zero (struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep) |
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void | xhci_drop_ep_from_interval_table (struct xhci_hcd *xhci, struct xhci_bw_info *ep_bw, struct xhci_interval_bw_table *bw_table, struct usb_device *udev, struct xhci_virt_ep *virt_ep, struct xhci_tt_bw_info *tt_info) |
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void | xhci_update_tt_active_eps (struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, int old_active_eps) |
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void | xhci_clear_endpoint_bw_info (struct xhci_bw_info *bw_info) |
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void | xhci_update_bw_info (struct xhci_hcd *xhci, struct xhci_container_ctx *in_ctx, struct xhci_input_control_ctx *ctrl_ctx, struct xhci_virt_device *virt_dev) |
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void | xhci_endpoint_copy (struct xhci_hcd *xhci, struct xhci_container_ctx *in_ctx, struct xhci_container_ctx *out_ctx, unsigned int ep_index) |
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void | xhci_slot_copy (struct xhci_hcd *xhci, struct xhci_container_ctx *in_ctx, struct xhci_container_ctx *out_ctx) |
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int | xhci_endpoint_init (struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_device *udev, struct usb_host_endpoint *ep, gfp_t mem_flags) |
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void | xhci_ring_free (struct xhci_hcd *xhci, struct xhci_ring *ring) |
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int | xhci_ring_expansion (struct xhci_hcd *xhci, struct xhci_ring *ring, unsigned int num_trbs, gfp_t flags) |
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void | xhci_free_or_cache_endpoint_ring (struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, unsigned int ep_index) |
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struct xhci_stream_info * | xhci_alloc_stream_info (struct xhci_hcd *xhci, unsigned int num_stream_ctxs, unsigned int num_streams, gfp_t flags) |
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void | xhci_free_stream_info (struct xhci_hcd *xhci, struct xhci_stream_info *stream_info) |
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void | xhci_setup_streams_ep_input_ctx (struct xhci_hcd *xhci, struct xhci_ep_ctx *ep_ctx, struct xhci_stream_info *stream_info) |
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void | xhci_setup_no_streams_ep_input_ctx (struct xhci_hcd *xhci, struct xhci_ep_ctx *ep_ctx, struct xhci_virt_ep *ep) |
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void | xhci_free_device_endpoint_resources (struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, bool drop_control_ep) |
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struct xhci_ring * | xhci_dma_to_transfer_ring (struct xhci_virt_ep *ep, u64 address) |
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struct xhci_ring * | xhci_stream_id_to_ring (struct xhci_virt_device *dev, unsigned int ep_index, unsigned int stream_id) |
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struct xhci_command * | xhci_alloc_command (struct xhci_hcd *xhci, bool allocate_in_ctx, bool allocate_completion, gfp_t mem_flags) |
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void | xhci_urb_free_priv (struct xhci_hcd *xhci, struct urb_priv *urb_priv) |
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void | xhci_free_command (struct xhci_hcd *xhci, struct xhci_command *command) |
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int | handshake (struct xhci_hcd *xhci, void __iomem *ptr, u32 mask, u32 done, int usec) |
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void | xhci_quiesce (struct xhci_hcd *xhci) |
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int | xhci_halt (struct xhci_hcd *xhci) |
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int | xhci_reset (struct xhci_hcd *xhci) |
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int | xhci_init (struct usb_hcd *hcd) |
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int | xhci_run (struct usb_hcd *hcd) |
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void | xhci_stop (struct usb_hcd *hcd) |
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void | xhci_shutdown (struct usb_hcd *hcd) |
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int | xhci_gen_setup (struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) |
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int | xhci_get_frame (struct usb_hcd *hcd) |
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irqreturn_t | xhci_irq (struct usb_hcd *hcd) |
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irqreturn_t | xhci_msi_irq (int irq, struct usb_hcd *hcd) |
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int | xhci_alloc_dev (struct usb_hcd *hcd, struct usb_device *udev) |
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void | xhci_free_dev (struct usb_hcd *hcd, struct usb_device *udev) |
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int | xhci_alloc_tt_info (struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_device *hdev, struct usb_tt *tt, gfp_t mem_flags) |
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int | xhci_alloc_streams (struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint **eps, unsigned int num_eps, unsigned int num_streams, gfp_t mem_flags) |
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int | xhci_free_streams (struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint **eps, unsigned int num_eps, gfp_t mem_flags) |
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int | xhci_address_device (struct usb_hcd *hcd, struct usb_device *udev) |
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int | xhci_update_device (struct usb_hcd *hcd, struct usb_device *udev) |
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int | xhci_set_usb2_hardware_lpm (struct usb_hcd *hcd, struct usb_device *udev, int enable) |
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int | xhci_update_hub_device (struct usb_hcd *hcd, struct usb_device *hdev, struct usb_tt *tt, gfp_t mem_flags) |
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int | xhci_urb_enqueue (struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) |
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int | xhci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb, int status) |
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int | xhci_add_endpoint (struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep) |
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int | xhci_drop_endpoint (struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep) |
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void | xhci_endpoint_reset (struct usb_hcd *hcd, struct usb_host_endpoint *ep) |
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int | xhci_discover_or_reset_device (struct usb_hcd *hcd, struct usb_device *udev) |
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int | xhci_check_bandwidth (struct usb_hcd *hcd, struct usb_device *udev) |
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void | xhci_reset_bandwidth (struct usb_hcd *hcd, struct usb_device *udev) |
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dma_addr_t | xhci_trb_virt_to_dma (struct xhci_segment *seg, union xhci_trb *trb) |
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struct xhci_segment * | trb_in_td (struct xhci_segment *start_seg, union xhci_trb *start_trb, union xhci_trb *end_trb, dma_addr_t suspect_dma) |
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int | xhci_is_vendor_info_code (struct xhci_hcd *xhci, unsigned int trb_comp_code) |
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void | xhci_ring_cmd_db (struct xhci_hcd *xhci) |
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int | xhci_queue_slot_control (struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
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int | xhci_queue_address_device (struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, u32 slot_id) |
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int | xhci_queue_vendor_command (struct xhci_hcd *xhci, u32 field1, u32 field2, u32 field3, u32 field4) |
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int | xhci_queue_stop_endpoint (struct xhci_hcd *xhci, int slot_id, unsigned int ep_index, int suspend) |
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int | xhci_queue_ctrl_tx (struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, int slot_id, unsigned int ep_index) |
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int | xhci_queue_bulk_tx (struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, int slot_id, unsigned int ep_index) |
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int | xhci_queue_intr_tx (struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, int slot_id, unsigned int ep_index) |
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int | xhci_queue_isoc_tx_prepare (struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, int slot_id, unsigned int ep_index) |
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int | xhci_queue_configure_endpoint (struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) |
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int | xhci_queue_evaluate_context (struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) |
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int | xhci_queue_reset_ep (struct xhci_hcd *xhci, int slot_id, unsigned int ep_index) |
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int | xhci_queue_reset_device (struct xhci_hcd *xhci, u32 slot_id) |
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void | xhci_find_new_dequeue_state (struct xhci_hcd *xhci, unsigned int slot_id, unsigned int ep_index, unsigned int stream_id, struct xhci_td *cur_td, struct xhci_dequeue_state *state) |
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void | xhci_queue_new_dequeue_state (struct xhci_hcd *xhci, unsigned int slot_id, unsigned int ep_index, unsigned int stream_id, struct xhci_dequeue_state *deq_state) |
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void | xhci_cleanup_stalled_ring (struct xhci_hcd *xhci, struct usb_device *udev, unsigned int ep_index) |
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void | xhci_queue_config_ep_quirk (struct xhci_hcd *xhci, unsigned int slot_id, unsigned int ep_index, struct xhci_dequeue_state *deq_state) |
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void | xhci_stop_endpoint_command_watchdog (unsigned long arg) |
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int | xhci_cancel_cmd (struct xhci_hcd *xhci, struct xhci_command *command, union xhci_trb *cmd_trb) |
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void | xhci_ring_ep_doorbell (struct xhci_hcd *xhci, unsigned int slot_id, unsigned int ep_index, unsigned int stream_id) |
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void | xhci_set_link_state (struct xhci_hcd *xhci, __le32 __iomem **port_array, int port_id, u32 link_state) |
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int | xhci_enable_usb3_lpm_timeout (struct usb_hcd *hcd, struct usb_device *udev, enum usb3_link_state state) |
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int | xhci_disable_usb3_lpm_timeout (struct usb_hcd *hcd, struct usb_device *udev, enum usb3_link_state state) |
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void | xhci_test_and_clear_bit (struct xhci_hcd *xhci, __le32 __iomem **port_array, int port_id, u32 port_bit) |
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int | xhci_hub_control (struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength) |
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int | xhci_hub_status_data (struct usb_hcd *hcd, char *buf) |
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u32 | xhci_port_state_to_neutral (u32 state) |
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int | xhci_find_slot_id_by_port (struct usb_hcd *hcd, struct xhci_hcd *xhci, u16 port) |
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void | xhci_ring_device (struct xhci_hcd *xhci, int slot_id) |
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struct xhci_input_control_ctx * | xhci_get_input_control_ctx (struct xhci_hcd *xhci, struct xhci_container_ctx *ctx) |
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struct xhci_slot_ctx * | xhci_get_slot_ctx (struct xhci_hcd *xhci, struct xhci_container_ctx *ctx) |
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struct xhci_ep_ctx * | xhci_get_ep_ctx (struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index) |
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