#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_core.h"
Go to the source code of this file.
|
| #define | E7XXX_REVISION " Ver: 2.0.2" |
| |
| #define | EDAC_MOD_STR "e7xxx_edac" |
| |
| #define | e7xxx_printk(level, fmt, arg...) edac_printk(level, "e7xxx", fmt, ##arg) |
| |
| #define | e7xxx_mc_printk(mci, level, fmt, arg...) edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg) |
| |
| #define | PCI_DEVICE_ID_INTEL_7205_0 0x255d |
| |
| #define | PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551 |
| |
| #define | PCI_DEVICE_ID_INTEL_7500_0 0x2540 |
| |
| #define | PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541 |
| |
| #define | PCI_DEVICE_ID_INTEL_7501_0 0x254c |
| |
| #define | PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541 |
| |
| #define | PCI_DEVICE_ID_INTEL_7505_0 0x2550 |
| |
| #define | PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551 |
| |
| #define | E7XXX_NR_CSROWS 8 /* number of csrows */ |
| |
| #define | E7XXX_NR_DIMMS 8 /* 2 channels, 4 dimms/channel */ |
| |
| #define | E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */ |
| |
| #define | E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */ |
| |
| #define | E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */ |
| |
| #define | E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ |
| |
| #define | E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ |
| |
| #define | E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ |
| |
| #define | E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */ |
| |
| #define | E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */ |
| |
| #define | E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */ |
| |
| #define | E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */ |
| |
| #define | E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */ |
| |
| #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */ |
| #define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */ |
| #define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */ |
| #define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */ |
| #define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */ |
| #define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */ |
| #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */ |
| #define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */ |
| #define E7XXX_NR_CSROWS 8 /* number of csrows */ |
| #define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ |
| #define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ |
| #define E7XXX_REVISION " Ver: 2.0.2" |
| #define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ |
| #define EDAC_MOD_STR "e7xxx_edac" |
| #define PCI_DEVICE_ID_INTEL_7205_0 0x255d |
| #define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551 |
| #define PCI_DEVICE_ID_INTEL_7500_0 0x2540 |
| #define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541 |
| #define PCI_DEVICE_ID_INTEL_7501_0 0x254c |
| #define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541 |
| #define PCI_DEVICE_ID_INTEL_7505_0 0x2550 |
| #define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551 |
| MODULE_AUTHOR |
( |
"Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n""Based on.work by Dan Hollis et al" |
| ) |
|
| MODULE_DEVICE_TABLE |
( |
pci |
, |
|
|
e7xxx_pci_tbl |
|
|
) |
| |
| module_exit |
( |
e7xxx_exit |
| ) |
|
| module_init |
( |
e7xxx_init |
| ) |
|
1.8.2