#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/in.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/bitops.h>
#include <linux/jiffies.h>
#include <linux/io.h>
#include <asm/dma.h>
Go to the source code of this file.
|
| #define | BITSET(ioaddr, bnum) ((outb(((inb(ioaddr)) | (bnum)), ioaddr))) |
| |
| #define | BITCLR(ioaddr, bnum) ((outb(((inb(ioaddr)) & (~(bnum))), ioaddr))) |
| |
| #define | ETH16I_IO_EXTENT 32 |
| |
| #define | TX_TIMEOUT (400*HZ/1000) |
| |
| #define | MAX_RX_LOOP 20 |
| |
| #define | ETH16I_INTR_ON 0xef8a /* Higher is receive mask */ |
| |
| #define | ETH16I_INTR_OFF 0x0000 |
| |
| #define | PKT_GOOD BIT(5) |
| |
| #define | PKT_GOOD_RMT BIT(4) |
| |
| #define | PKT_SHORT BIT(3) |
| |
| #define | PKT_ALIGN_ERR BIT(2) |
| |
| #define | PKT_CRC_ERR BIT(1) |
| |
| #define | PKT_RX_BUF_OVERFLOW BIT(0) |
| |
| #define | TX_STATUS_REG 0 |
| |
| #define | TX_DONE BIT(7) |
| |
| #define | NET_BUSY BIT(6) |
| |
| #define | TX_PKT_RCD BIT(5) |
| |
| #define | CR_LOST BIT(4) |
| |
| #define | TX_JABBER_ERR BIT(3) |
| |
| #define | COLLISION BIT(2) |
| |
| #define | COLLISIONS_16 BIT(1) |
| |
| #define | RX_STATUS_REG 1 |
| |
| #define | RX_PKT BIT(7) /* Packet received */ |
| |
| #define | BUS_RD_ERR BIT(6) |
| |
| #define | SHORT_PKT_ERR BIT(3) |
| |
| #define | ALIGN_ERR BIT(2) |
| |
| #define | CRC_ERR BIT(1) |
| |
| #define | RX_BUF_OVERFLOW BIT(0) |
| |
| #define | TX_INTR_REG 2 |
| |
| #define | TX_INTR_DONE BIT(7) |
| |
| #define | TX_INTR_COL BIT(2) |
| |
| #define | TX_INTR_16_COL BIT(1) |
| |
| #define | RX_INTR_REG 3 |
| |
| #define | RX_INTR_RECEIVE BIT(7) |
| |
| #define | RX_INTR_SHORT_PKT BIT(3) |
| |
| #define | RX_INTR_CRC_ERR BIT(1) |
| |
| #define | RX_INTR_BUF_OVERFLOW BIT(0) |
| |
| #define | TRANSMIT_MODE_REG 4 |
| |
| #define | LOOPBACK_CONTROL BIT(1) |
| |
| #define | CONTROL_OUTPUT BIT(2) |
| |
| #define | RECEIVE_MODE_REG 5 |
| |
| #define | RX_BUFFER_EMPTY BIT(6) |
| |
| #define | ACCEPT_BAD_PACKETS BIT(5) |
| |
| #define | RECEIVE_SHORT_ADDR BIT(4) |
| |
| #define | ACCEPT_SHORT_PACKETS BIT(3) |
| |
| #define | REMOTE_RESET BIT(2) |
| |
| #define | ADDRESS_FILTER_MODE BIT(1) | BIT(0) |
| |
| #define | REJECT_ALL 0 |
| |
| #define | ACCEPT_ALL 3 |
| |
| #define | MODE_1 1 /* NODE ID, BC, MC, 2-24th bit */ |
| |
| #define | MODE_2 2 /* NODE ID, BC, MC, Hash Table */ |
| |
| #define | CONFIG_REG_0 6 |
| |
| #define | DLC_EN BIT(7) |
| |
| #define | SRAM_CYCLE_TIME_100NS BIT(6) |
| |
| #define | SYSTEM_BUS_WIDTH_8 BIT(5) /* 1 = 8bit, 0 = 16bit */ |
| |
| #define | BUFFER_WIDTH_8 BIT(4) /* 1 = 8bit, 0 = 16bit */ |
| |
| #define | TBS1 BIT(3) |
| |
| #define | TBS0 BIT(2) |
| |
| #define | SRAM_BS1 BIT(1) /* 00=8kb, 01=16kb */ |
| |
| #define | SRAM_BS0 BIT(0) /* 10=32kb, 11=64kb */ |
| |
| #define | ETH16I_TX_BUF_SIZE 3 /* 2 = 8kb, 3 = 16kb */ |
| |
| #define | TX_BUF_1x2048 0 |
| |
| #define | TX_BUF_2x2048 1 |
| |
| #define | TX_BUF_2x4098 2 |
| |
| #define | TX_BUF_2x8192 3 |
| |
| #define | CONFIG_REG_1 7 |
| |
| #define | POWERUP BIT(5) |
| |
| #define | TRANSMIT_START_REG 10 |
| |
| #define | TRANSMIT_START_RB 2 |
| |
| #define | TX_START BIT(7) /* Rest of register bit indicate*/ |
| |
| #define | NODE_ID_0 8 |
| |
| #define | NODE_ID_RB 0 |
| |
| #define | HASH_TABLE_0 8 |
| |
| #define | HASH_TABLE_RB 1 |
| |
| #define | BUFFER_MEM_PORT_LB 8 |
| |
| #define | DATAPORT BUFFER_MEM_PORT_LB |
| |
| #define | BUFFER_MEM_PORT_HB 9 |
| |
| #define | COL_16_REG 11 |
| |
| #define | HALT_ON_16 0x00 |
| |
| #define | RETRANS_AND_HALT_ON_16 0x02 |
| |
| #define | MAX_COL_16 10 |
| |
| #define | TRANSCEIVER_MODE_REG 13 |
| |
| #define | TRANSCEIVER_MODE_RB 2 |
| |
| #define | IO_BASE_UNLOCK BIT(7) |
| |
| #define | LOWER_SQUELCH_TRESH BIT(6) |
| |
| #define | LINK_TEST_DISABLE BIT(5) |
| |
| #define | AUI_SELECT BIT(4) |
| |
| #define | DIS_AUTO_PORT_SEL BIT(3) |
| |
| #define | FILTER_SELF_RX_REG 14 |
| |
| #define | SKIP_RX_PACKET BIT(2) |
| |
| #define | FILTER_SELF_RECEIVE BIT(0) |
| |
| #define | EEPROM_CTRL_REG 16 |
| |
| #define | EEPROM_DATA_REG 17 |
| |
| #define | CS_0 0x00 |
| |
| #define | CS_1 0x20 |
| |
| #define | SK_0 0x00 |
| |
| #define | SK_1 0x40 |
| |
| #define | DI_0 0x00 |
| |
| #define | DI_1 0x80 |
| |
| #define | EEPROM_READ 0x80 |
| |
| #define | E_NODEID_0 0x02 |
| |
| #define | E_NODEID_1 0x03 |
| |
| #define | E_NODEID_2 0x04 |
| |
| #define | E_PORT_SELECT 0x14 |
| |
| #define | E_PORT_BNC 0x00 |
| |
| #define | E_PORT_DIX 0x01 |
| |
| #define | E_PORT_TP 0x02 |
| |
| #define | E_PORT_AUTO 0x03 |
| |
| #define | E_PORT_FROM_EPROM 0x04 |
| |
| #define | E_PRODUCT_CFG 0x30 |
| |
| #define | eeprom_slow_io() do { int _i = 40; while(--_i > 0) { inb(0x80); }}while(0) |
| |
| #define | JUMPERLESS_CONFIG 19 |
| |
| #define | ID_ROM_0 24 |
| |
| #define | ID_ROM_7 31 |
| |
| #define | RESET ID_ROM_0 |
| |
| #define | NUM_OF_ISA_IRQS 4 |
| |
| #define | EISA_IRQ_REG 0xc89 |
| |
| #define | NUM_OF_EISA_IRQS 8 |
| |
| #define | ETH16I_DEBUG 0 |
| |
| #define ACCEPT_BAD_PACKETS BIT(5) |
| #define ACCEPT_SHORT_PACKETS BIT(3) |
| #define ADDRESS_FILTER_MODE BIT(1) | BIT(0) |
| #define AUI_SELECT BIT(4) |
| #define BITCLR |
( |
|
ioaddr, |
|
|
|
bnum |
|
) |
| ((outb(((inb(ioaddr)) & (~(bnum))), ioaddr))) |
| #define BITSET |
( |
|
ioaddr, |
|
|
|
bnum |
|
) |
| ((outb(((inb(ioaddr)) | (bnum)), ioaddr))) |
| #define BUFFER_MEM_PORT_HB 9 |
| #define BUFFER_MEM_PORT_LB 8 |
| #define BUFFER_WIDTH_8 BIT(4) /* 1 = 8bit, 0 = 16bit */ |
| #define BUS_RD_ERR BIT(6) |
| #define COLLISIONS_16 BIT(1) |
| #define CONTROL_OUTPUT BIT(2) |
| #define DIS_AUTO_PORT_SEL BIT(3) |
| #define E_PORT_FROM_EPROM 0x04 |
| #define E_PORT_SELECT 0x14 |
| #define E_PRODUCT_CFG 0x30 |
| #define EEPROM_CTRL_REG 16 |
| #define EEPROM_DATA_REG 17 |
| #define eeprom_slow_io |
( |
| ) |
do { int _i = 40; while(--_i > 0) { inb(0x80); }}while(0) |
| #define EISA_IRQ_REG 0xc89 |
| #define ETH16I_INTR_OFF 0x0000 |
| #define ETH16I_INTR_ON 0xef8a /* Higher is receive mask */ |
| #define ETH16I_IO_EXTENT 32 |
| #define ETH16I_TX_BUF_SIZE 3 /* 2 = 8kb, 3 = 16kb */ |
| #define FILTER_SELF_RECEIVE BIT(0) |
| #define FILTER_SELF_RX_REG 14 |
| #define IO_BASE_UNLOCK BIT(7) |
| #define JUMPERLESS_CONFIG 19 |
| #define LINK_TEST_DISABLE BIT(5) |
| #define LOOPBACK_CONTROL BIT(1) |
| #define LOWER_SQUELCH_TRESH BIT(6) |
| #define MODE_1 1 /* NODE ID, BC, MC, 2-24th bit */ |
| #define MODE_2 2 /* NODE ID, BC, MC, Hash Table */ |
| #define NUM_OF_EISA_IRQS 8 |
| #define NUM_OF_ISA_IRQS 4 |
| #define PKT_ALIGN_ERR BIT(2) |
| #define PKT_CRC_ERR BIT(1) |
| #define PKT_GOOD_RMT BIT(4) |
| #define PKT_RX_BUF_OVERFLOW BIT(0) |
| #define RECEIVE_MODE_REG 5 |
| #define RECEIVE_SHORT_ADDR BIT(4) |
| #define REMOTE_RESET BIT(2) |
| #define RETRANS_AND_HALT_ON_16 0x02 |
| #define RX_BUF_OVERFLOW BIT(0) |
| #define RX_BUFFER_EMPTY BIT(6) |
| #define RX_INTR_BUF_OVERFLOW BIT(0) |
| #define RX_INTR_CRC_ERR BIT(1) |
| #define RX_INTR_RECEIVE BIT(7) |
| #define RX_INTR_SHORT_PKT BIT(3) |
| #define SHORT_PKT_ERR BIT(3) |
| #define SKIP_RX_PACKET BIT(2) |
| #define SRAM_BS0 BIT(0) /* 10=32kb, 11=64kb */ |
| #define SRAM_BS1 BIT(1) /* 00=8kb, 01=16kb */ |
| #define SRAM_CYCLE_TIME_100NS BIT(6) |
| #define SYSTEM_BUS_WIDTH_8 BIT(5) /* 1 = 8bit, 0 = 16bit */ |
| #define TRANSCEIVER_MODE_RB 2 |
| #define TRANSCEIVER_MODE_REG 13 |
| #define TRANSMIT_MODE_REG 4 |
| #define TRANSMIT_START_RB 2 |
| #define TRANSMIT_START_REG 10 |
| #define TX_INTR_16_COL BIT(1) |
| #define TX_INTR_COL BIT(2) |
| #define TX_INTR_DONE BIT(7) |
| #define TX_JABBER_ERR BIT(3) |
| #define TX_PKT_RCD BIT(5) |
| #define TX_START BIT(7) /* Rest of register bit indicate*/ |
| #define TX_TIMEOUT (400*HZ/1000) |
1.8.2