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exynos_mipi_dsi_common.c
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1 /* linux/drivers/video/exynos/exynos_mipi_dsi_common.c
2  *
3  * Samsung SoC MIPI-DSI common driver.
4  *
5  * Copyright (c) 2012 Samsung Electronics Co., Ltd
6  *
7  * InKi Dae, <[email protected]>
8  * Donghwa Lee, <[email protected]>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13 */
14 
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/mutex.h>
19 #include <linux/wait.h>
20 #include <linux/fs.h>
21 #include <linux/mm.h>
22 #include <linux/fb.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26 #include <linux/memory.h>
27 #include <linux/delay.h>
28 #include <linux/kthread.h>
29 
30 #include <video/mipi_display.h>
31 #include <video/exynos_mipi_dsim.h>
32 
33 #include <mach/map.h>
34 
35 #include "exynos_mipi_dsi_regs.h"
36 #include "exynos_mipi_dsi_lowlevel.h"
37 #include "exynos_mipi_dsi_common.h"
38 
39 #define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
40 #define MIPI_RX_FIFO_READ_DONE 0x30800002
41 #define MIPI_MAX_RX_FIFO 20
42 #define MHZ (1000 * 1000)
43 #define FIN_HZ (24 * MHZ)
44 
45 #define DFIN_PLL_MIN_HZ (6 * MHZ)
46 #define DFIN_PLL_MAX_HZ (12 * MHZ)
47 
48 #define DFVCO_MIN_HZ (500 * MHZ)
49 #define DFVCO_MAX_HZ (1000 * MHZ)
50 
51 #define TRY_GET_FIFO_TIMEOUT (5000 * 2)
52 #define TRY_FIFO_CLEAR (10)
53 
54 /* MIPI-DSIM status types. */
55 enum {
56  DSIM_STATE_INIT, /* should be initialized. */
57  DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
58  DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
59  DSIM_STATE_ULPS
60 };
61 
62 /* define DSI lane types. */
63 enum {
64  DSIM_LANE_CLOCK = (1 << 0),
65  DSIM_LANE_DATA0 = (1 << 1),
66  DSIM_LANE_DATA1 = (1 << 2),
67  DSIM_LANE_DATA2 = (1 << 3),
68  DSIM_LANE_DATA3 = (1 << 4)
69 };
70 
71 static unsigned int dpll_table[15] = {
72  100, 120, 170, 220, 270,
73  320, 390, 450, 510, 560,
74  640, 690, 770, 870, 950
75 };
76 
77 irqreturn_t exynos_mipi_dsi_interrupt_handler(int irq, void *dev_id)
78 {
79  struct mipi_dsim_device *dsim = dev_id;
80  unsigned int intsrc, intmsk;
81 
82  intsrc = exynos_mipi_dsi_read_interrupt(dsim);
83  intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim);
84  intmsk = ~intmsk & intsrc;
85 
86  if (intsrc & INTMSK_RX_DONE) {
87  complete(&dsim_rd_comp);
88  dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n");
89  }
90  if (intsrc & INTMSK_FIFO_EMPTY) {
91  complete(&dsim_wr_comp);
92  dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n");
93  }
94 
95  exynos_mipi_dsi_clear_interrupt(dsim, intmsk);
96 
97  return IRQ_HANDLED;
98 }
99 
100 /*
101  * write long packet to mipi dsi slave
102  * @dsim: mipi dsim device structure.
103  * @data0: packet data to send.
104  * @data1: size of packet data
105  */
106 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
107  const unsigned char *data0, unsigned int data_size)
108 {
109  unsigned int data_cnt = 0, payload = 0;
110 
111  /* in case that data count is more then 4 */
112  for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) {
113  /*
114  * after sending 4bytes per one time,
115  * send remainder data less then 4.
116  */
117  if ((data_size - data_cnt) < 4) {
118  if ((data_size - data_cnt) == 3) {
119  payload = data0[data_cnt] |
120  data0[data_cnt + 1] << 8 |
121  data0[data_cnt + 2] << 16;
122  dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
123  payload, data0[data_cnt],
124  data0[data_cnt + 1],
125  data0[data_cnt + 2]);
126  } else if ((data_size - data_cnt) == 2) {
127  payload = data0[data_cnt] |
128  data0[data_cnt + 1] << 8;
129  dev_dbg(dsim->dev,
130  "count = 2 payload = %x, %x %x\n", payload,
131  data0[data_cnt],
132  data0[data_cnt + 1]);
133  } else if ((data_size - data_cnt) == 1) {
134  payload = data0[data_cnt];
135  }
136 
137  exynos_mipi_dsi_wr_tx_data(dsim, payload);
138  /* send 4bytes per one time. */
139  } else {
140  payload = data0[data_cnt] |
141  data0[data_cnt + 1] << 8 |
142  data0[data_cnt + 2] << 16 |
143  data0[data_cnt + 3] << 24;
144 
145  dev_dbg(dsim->dev,
146  "count = 4 payload = %x, %x %x %x %x\n",
147  payload, *(u8 *)(data0 + data_cnt),
148  data0[data_cnt + 1],
149  data0[data_cnt + 2],
150  data0[data_cnt + 3]);
151 
152  exynos_mipi_dsi_wr_tx_data(dsim, payload);
153  }
154  }
155 }
156 
157 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
158  const unsigned char *data0, unsigned int data_size)
159 {
160  unsigned int check_rx_ack = 0;
161 
162  if (dsim->state == DSIM_STATE_ULPS) {
163  dev_err(dsim->dev, "state is ULPS.\n");
164 
165  return -EINVAL;
166  }
167 
168  /* FIXME!!! why does it need this delay? */
169  msleep(20);
170 
171  mutex_lock(&dsim->lock);
172 
173  switch (data_id) {
174  /* short packet types of packet types for command. */
175  case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
176  case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
177  case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
178  case MIPI_DSI_DCS_SHORT_WRITE:
179  case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
180  case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
181  exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
182  if (check_rx_ack) {
183  /* process response func should be implemented */
184  mutex_unlock(&dsim->lock);
185  return 0;
186  } else {
187  mutex_unlock(&dsim->lock);
188  return -EINVAL;
189  }
190 
191  /* general command */
192  case MIPI_DSI_COLOR_MODE_OFF:
193  case MIPI_DSI_COLOR_MODE_ON:
194  case MIPI_DSI_SHUTDOWN_PERIPHERAL:
195  case MIPI_DSI_TURN_ON_PERIPHERAL:
196  exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
197  if (check_rx_ack) {
198  /* process response func should be implemented. */
199  mutex_unlock(&dsim->lock);
200  return 0;
201  } else {
202  mutex_unlock(&dsim->lock);
203  return -EINVAL;
204  }
205 
206  /* packet types for video data */
207  case MIPI_DSI_V_SYNC_START:
208  case MIPI_DSI_V_SYNC_END:
209  case MIPI_DSI_H_SYNC_START:
210  case MIPI_DSI_H_SYNC_END:
211  case MIPI_DSI_END_OF_TRANSMISSION:
212  mutex_unlock(&dsim->lock);
213  return 0;
214 
215  /* long packet type and null packet */
216  case MIPI_DSI_NULL_PACKET:
217  case MIPI_DSI_BLANKING_PACKET:
218  mutex_unlock(&dsim->lock);
219  return 0;
220  case MIPI_DSI_GENERIC_LONG_WRITE:
221  case MIPI_DSI_DCS_LONG_WRITE:
222  {
223  unsigned int size, payload = 0;
224  INIT_COMPLETION(dsim_wr_comp);
225 
226  size = data_size * 4;
227 
228  /* if data count is less then 4, then send 3bytes data. */
229  if (data_size < 4) {
230  payload = data0[0] |
231  data0[1] << 8 |
232  data0[2] << 16;
233 
234  exynos_mipi_dsi_wr_tx_data(dsim, payload);
235 
236  dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
237  data_size, payload, data0[0],
238  data0[1], data0[2]);
239 
240  /* in case that data count is more then 4 */
241  } else
242  exynos_mipi_dsi_long_data_wr(dsim, data0, data_size);
243 
244  /* put data into header fifo */
245  exynos_mipi_dsi_wr_tx_header(dsim, data_id, data_size & 0xff,
246  (data_size & 0xff00) >> 8);
247 
248  if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp,
249  MIPI_FIFO_TIMEOUT)) {
250  dev_warn(dsim->dev, "command write timeout.\n");
251  mutex_unlock(&dsim->lock);
252  return -EAGAIN;
253  }
254 
255  if (check_rx_ack) {
256  /* process response func should be implemented. */
257  mutex_unlock(&dsim->lock);
258  return 0;
259  } else {
260  mutex_unlock(&dsim->lock);
261  return -EINVAL;
262  }
263  }
264 
265  /* packet typo for video data */
266  case MIPI_DSI_PACKED_PIXEL_STREAM_16:
267  case MIPI_DSI_PACKED_PIXEL_STREAM_18:
268  case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
269  case MIPI_DSI_PACKED_PIXEL_STREAM_24:
270  if (check_rx_ack) {
271  /* process response func should be implemented. */
272  mutex_unlock(&dsim->lock);
273  return 0;
274  } else {
275  mutex_unlock(&dsim->lock);
276  return -EINVAL;
277  }
278  default:
279  dev_warn(dsim->dev,
280  "data id %x is not supported current DSI spec.\n",
281  data_id);
282 
283  mutex_unlock(&dsim->lock);
284  return -EINVAL;
285  }
286 }
287 
288 static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
289  unsigned int req_size, unsigned int rx_data, u8 *rx_buf)
290 {
291  unsigned int rcv_pkt, i, j;
292  u16 rxsize;
293 
294  /* for long packet */
295  rxsize = (u16)((rx_data & 0x00ffff00) >> 8);
296  dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);
297  if (rxsize != req_size) {
298  dev_dbg(dsim->dev,
299  "received size mismatch received: %d, requested: %d\n",
300  rxsize, req_size);
301  goto err;
302  }
303 
304  for (i = 0; i < (rxsize >> 2); i++) {
305  rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
306  dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
307  for (j = 0; j < 4; j++) {
308  rx_buf[(i * 4) + j] =
309  (u8)(rcv_pkt >> (j * 8)) & 0xff;
310  dev_dbg(dsim->dev, "received value : %02x\n",
311  (rcv_pkt >> (j * 8)) & 0xff);
312  }
313  }
314  if (rxsize % 4) {
315  rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
316  dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
317  for (j = 0; j < (rxsize % 4); j++) {
318  rx_buf[(i * 4) + j] =
319  (u8)(rcv_pkt >> (j * 8)) & 0xff;
320  dev_dbg(dsim->dev, "received value : %02x\n",
321  (rcv_pkt >> (j * 8)) & 0xff);
322  }
323  }
324 
325  return rxsize;
326 
327 err:
328  return -EINVAL;
329 }
330 
331 static unsigned int exynos_mipi_dsi_response_size(unsigned int req_size)
332 {
333  switch (req_size) {
334  case 1:
335  return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE;
336  case 2:
337  return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE;
338  default:
339  return MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE;
340  }
341 }
342 
343 int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
344  unsigned int data0, unsigned int req_size, u8 *rx_buf)
345 {
346  unsigned int rx_data, rcv_pkt, i;
347  u8 response = 0;
348  u16 rxsize;
349 
350  if (dsim->state == DSIM_STATE_ULPS) {
351  dev_err(dsim->dev, "state is ULPS.\n");
352 
353  return -EINVAL;
354  }
355 
356  /* FIXME!!! */
357  msleep(20);
358 
359  mutex_lock(&dsim->lock);
360  INIT_COMPLETION(dsim_rd_comp);
361  exynos_mipi_dsi_rd_tx_header(dsim,
362  MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size);
363 
364  response = exynos_mipi_dsi_response_size(req_size);
365 
366  switch (data_id) {
367  case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
368  case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
369  case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
370  case MIPI_DSI_DCS_READ:
371  exynos_mipi_dsi_rd_tx_header(dsim,
372  data_id, data0);
373  /* process response func should be implemented. */
374  break;
375  default:
376  dev_warn(dsim->dev,
377  "data id %x is not supported current DSI spec.\n",
378  data_id);
379 
380  return -EINVAL;
381  }
382 
383  if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp,
384  MIPI_FIFO_TIMEOUT)) {
385  pr_err("RX done interrupt timeout\n");
386  mutex_unlock(&dsim->lock);
387  return 0;
388  }
389 
390  msleep(20);
391 
392  rx_data = exynos_mipi_dsi_rd_rx_fifo(dsim);
393 
394  if ((u8)(rx_data & 0xff) != response) {
395  printk(KERN_ERR
396  "mipi dsi wrong response rx_data : %x, response:%x\n",
397  rx_data, response);
398  goto clear_rx_fifo;
399  }
400 
401  if (req_size <= 2) {
402  /* for short packet */
403  for (i = 0; i < req_size; i++)
404  rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff;
405  rxsize = req_size;
406  } else {
407  /* for long packet */
408  rxsize = exynos_mipi_dsi_long_data_rd(dsim, req_size, rx_data,
409  rx_buf);
410  if (rxsize != req_size)
411  goto clear_rx_fifo;
412  }
413 
414  rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
415 
416  msleep(20);
417 
418  if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) {
419  dev_info(dsim->dev,
420  "Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt);
421  goto clear_rx_fifo;
422  }
423 
424  mutex_unlock(&dsim->lock);
425 
426  return rxsize;
427 
428 clear_rx_fifo:
429  i = 0;
430  while (1) {
431  rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
432  if ((rcv_pkt == MIPI_RX_FIFO_READ_DONE)
433  || (i > MIPI_MAX_RX_FIFO))
434  break;
435  dev_dbg(dsim->dev,
436  "mipi dsi clear rx fifo : %08x\n", rcv_pkt);
437  i++;
438  }
439  dev_info(dsim->dev,
440  "mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt);
441 
442  mutex_unlock(&dsim->lock);
443 
444  return 0;
445 }
446 
447 static int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim,
448  unsigned int enable)
449 {
450  int sw_timeout;
451 
452  if (enable) {
453  sw_timeout = 1000;
454 
455  exynos_mipi_dsi_enable_pll(dsim, 1);
456  while (1) {
457  sw_timeout--;
458  if (exynos_mipi_dsi_is_pll_stable(dsim))
459  return 0;
460  if (sw_timeout == 0)
461  return -EINVAL;
462  }
463  } else
464  exynos_mipi_dsi_enable_pll(dsim, 0);
465 
466  return 0;
467 }
468 
469 static unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
470  unsigned int pre_divider, unsigned int main_divider,
471  unsigned int scaler)
472 {
473  unsigned long dfin_pll, dfvco, dpll_out;
474  unsigned int i, freq_band = 0xf;
475 
476  dfin_pll = (FIN_HZ / pre_divider);
477 
478  /******************************************************
479  * Serial Clock(=ByteClk X 8) FreqBand[3:0] *
480  ******************************************************
481  * ~ 99.99 MHz 0000
482  * 100 ~ 119.99 MHz 0001
483  * 120 ~ 159.99 MHz 0010
484  * 160 ~ 199.99 MHz 0011
485  * 200 ~ 239.99 MHz 0100
486  * 140 ~ 319.99 MHz 0101
487  * 320 ~ 389.99 MHz 0110
488  * 390 ~ 449.99 MHz 0111
489  * 450 ~ 509.99 MHz 1000
490  * 510 ~ 559.99 MHz 1001
491  * 560 ~ 639.99 MHz 1010
492  * 640 ~ 689.99 MHz 1011
493  * 690 ~ 769.99 MHz 1100
494  * 770 ~ 869.99 MHz 1101
495  * 870 ~ 949.99 MHz 1110
496  * 950 ~ 1000 MHz 1111
497  ******************************************************/
498  if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
499  dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
500  exynos_mipi_dsi_enable_afc(dsim, 0, 0);
501  } else {
502  if (dfin_pll < 7 * MHZ)
503  exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
504  else if (dfin_pll < 8 * MHZ)
505  exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
506  else if (dfin_pll < 9 * MHZ)
507  exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
508  else if (dfin_pll < 10 * MHZ)
509  exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
510  else if (dfin_pll < 11 * MHZ)
511  exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
512  else
513  exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
514  }
515 
516  dfvco = dfin_pll * main_divider;
517  dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
518  dfvco, dfin_pll, main_divider);
519  if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
520  dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
521 
522  dpll_out = dfvco / (1 << scaler);
523  dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
524  dpll_out, dfvco, scaler);
525 
526  for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
527  if (dpll_out < dpll_table[i] * MHZ) {
528  freq_band = i;
529  break;
530  }
531  }
532 
533  dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
534 
535  exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
536 
537  exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
538  exynos_mipi_dsi_prep_ctrl(dsim, 0);
539 
540  /* Freq Band */
541  exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
542 
543  /* Stable time */
544  exynos_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
545 
546  /* Enable PLL */
547  dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
548  (dpll_out / MHZ));
549 
550  return dpll_out;
551 }
552 
553 static int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
554  unsigned int byte_clk_sel, unsigned int enable)
555 {
556  unsigned int esc_div;
557  unsigned long esc_clk_error_rate;
558  unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
559 
560  if (enable) {
561  dsim->e_clk_src = byte_clk_sel;
562 
563  /* Escape mode clock and byte clock source */
564  exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
565 
566  /* DPHY, DSIM Link : D-PHY clock out */
567  if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
568  hs_clk = exynos_mipi_dsi_change_pll(dsim,
569  dsim->dsim_config->p, dsim->dsim_config->m,
570  dsim->dsim_config->s);
571  if (hs_clk == 0) {
572  dev_err(dsim->dev,
573  "failed to get hs clock.\n");
574  return -EINVAL;
575  }
576 
577  byte_clk = hs_clk / 8;
578  exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
579  exynos_mipi_dsi_pll_on(dsim, 1);
580  /* DPHY : D-PHY clock out, DSIM link : external clock out */
581  } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) {
582  dev_warn(dsim->dev, "this project is not support\n");
583  dev_warn(dsim->dev,
584  "external clock source for MIPI DSIM.\n");
585  } else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) {
586  dev_warn(dsim->dev, "this project is not support\n");
587  dev_warn(dsim->dev,
588  "external clock source for MIPI DSIM\n");
589  }
590 
591  /* escape clock divider */
592  esc_div = byte_clk / (dsim->dsim_config->esc_clk);
593  dev_dbg(dsim->dev,
594  "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
595  esc_div, byte_clk, dsim->dsim_config->esc_clk);
596  if ((byte_clk / esc_div) >= (20 * MHZ) ||
597  (byte_clk / esc_div) >
598  dsim->dsim_config->esc_clk)
599  esc_div += 1;
600 
601  escape_clk = byte_clk / esc_div;
602  dev_dbg(dsim->dev,
603  "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
604  escape_clk, byte_clk, esc_div);
605 
606  /* enable escape clock. */
607  exynos_mipi_dsi_enable_byte_clock(dsim, 1);
608 
609  /* enable byte clk and escape clock */
610  exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
611  /* escape clock on lane */
612  exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
613  (DSIM_LANE_CLOCK | dsim->data_lane), 1);
614 
615  dev_dbg(dsim->dev, "byte clock is %luMHz\n",
616  (byte_clk / MHZ));
617  dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
618  (dsim->dsim_config->esc_clk / MHZ));
619  dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
620  dev_dbg(dsim->dev, "escape clock is %luMHz\n",
621  ((byte_clk / esc_div) / MHZ));
622 
623  if ((byte_clk / esc_div) > escape_clk) {
624  esc_clk_error_rate = escape_clk /
625  (byte_clk / esc_div);
626  dev_warn(dsim->dev, "error rate is %lu over.\n",
627  (esc_clk_error_rate / 100));
628  } else if ((byte_clk / esc_div) < (escape_clk)) {
629  esc_clk_error_rate = (byte_clk / esc_div) /
630  escape_clk;
631  dev_warn(dsim->dev, "error rate is %lu under.\n",
632  (esc_clk_error_rate / 100));
633  }
634  } else {
635  exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
636  (DSIM_LANE_CLOCK | dsim->data_lane), 0);
637  exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
638 
639  /* disable escape clock. */
640  exynos_mipi_dsi_enable_byte_clock(dsim, 0);
641 
642  if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
643  exynos_mipi_dsi_pll_on(dsim, 0);
644  }
645 
646  return 0;
647 }
648 
649 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
650 {
651  dsim->state = DSIM_STATE_INIT;
652 
653  switch (dsim->dsim_config->e_no_data_lane) {
654  case DSIM_DATA_LANE_1:
655  dsim->data_lane = DSIM_LANE_DATA0;
656  break;
657  case DSIM_DATA_LANE_2:
658  dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
659  break;
660  case DSIM_DATA_LANE_3:
661  dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
662  DSIM_LANE_DATA2;
663  break;
664  case DSIM_DATA_LANE_4:
665  dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
666  DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
667  break;
668  default:
669  dev_info(dsim->dev, "data lane is invalid.\n");
670  return -EINVAL;
671  };
672 
673  exynos_mipi_dsi_sw_reset(dsim);
674  exynos_mipi_dsi_func_reset(dsim);
675 
676  exynos_mipi_dsi_dp_dn_swap(dsim, 0);
677 
678  return 0;
679 }
680 
681 void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)
682 {
683  unsigned int src = 0;
684 
685  src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE);
686  exynos_mipi_dsi_set_interrupt(dsim, src, 1);
687 
688  src = 0;
689  src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY);
690  exynos_mipi_dsi_set_interrupt_mask(dsim, src, 1);
691 }
692 
693 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
694  unsigned int enable)
695 {
696  /* enable only frame done interrupt */
697  exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
698 
699  return 0;
700 }
701 
702 void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
703  unsigned int enable)
704 {
705 
706  /* consider Main display and Sub display. */
707 
708  exynos_mipi_dsi_set_main_stand_by(dsim, enable);
709 }
710 
711 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
712  struct mipi_dsim_config *dsim_config)
713 {
714  struct mipi_dsim_platform_data *dsim_pd;
715  struct fb_videomode *timing;
716 
717  dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
718  timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
719 
720  /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
721  if (dsim_config->e_interface == (u32) DSIM_VIDEO) {
722  if (dsim_config->auto_vertical_cnt == 0) {
723  exynos_mipi_dsi_set_main_disp_vporch(dsim,
724  dsim_config->cmd_allow,
725  timing->lower_margin,
726  timing->upper_margin);
727  exynos_mipi_dsi_set_main_disp_hporch(dsim,
728  timing->right_margin,
729  timing->left_margin);
730  exynos_mipi_dsi_set_main_disp_sync_area(dsim,
731  timing->vsync_len,
732  timing->hsync_len);
733  }
734  }
735 
736  exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
737  timing->yres);
738 
739  exynos_mipi_dsi_display_config(dsim, dsim_config);
740 
741  dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n",
742  timing->xres, timing->yres);
743 
744  return 0;
745 }
746 
747 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
748 {
749  unsigned int time_out = 100;
750 
751  switch (dsim->state) {
752  case DSIM_STATE_INIT:
753  exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
754 
755  /* dsi configuration */
756  exynos_mipi_dsi_init_config(dsim);
757  exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
758  exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
759 
760  /* set clock configuration */
761  exynos_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
762 
763  /* check clock and data lane state are stop state */
764  while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
765  time_out--;
766  if (time_out == 0) {
767  dev_err(dsim->dev,
768  "DSI Master is not stop state.\n");
769  dev_err(dsim->dev,
770  "Check initialization process\n");
771 
772  return -EINVAL;
773  }
774  }
775  if (time_out != 0) {
776  dev_info(dsim->dev,
777  "DSI Master driver has been completed.\n");
778  dev_info(dsim->dev, "DSI Master state is stop state\n");
779  }
780 
781  dsim->state = DSIM_STATE_STOP;
782 
783  /* BTA sequence counters */
784  exynos_mipi_dsi_set_stop_state_counter(dsim,
785  dsim->dsim_config->stop_holding_cnt);
786  exynos_mipi_dsi_set_bta_timeout(dsim,
787  dsim->dsim_config->bta_timeout);
788  exynos_mipi_dsi_set_lpdr_timeout(dsim,
789  dsim->dsim_config->rx_timeout);
790 
791  return 0;
792  default:
793  dev_info(dsim->dev, "DSI Master is already init.\n");
794  return 0;
795  }
796 
797  return 0;
798 }
799 
800 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
801 {
802  if (dsim->state != DSIM_STATE_STOP) {
803  dev_warn(dsim->dev, "DSIM is not in stop state.\n");
804  return 0;
805  }
806 
807  if (dsim->e_clk_src == DSIM_EXT_CLK_BYPASS) {
808  dev_warn(dsim->dev, "clock source is external bypass.\n");
809  return 0;
810  }
811 
812  dsim->state = DSIM_STATE_HSCLKEN;
813 
814  /* set LCDC and CPU transfer mode to HS. */
815  exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
816  exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
817  exynos_mipi_dsi_enable_hs_clock(dsim, 1);
818 
819  return 0;
820 }
821 
822 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
823  unsigned int mode)
824 {
825  if (mode) {
826  if (dsim->state != DSIM_STATE_HSCLKEN) {
827  dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
828  return -EINVAL;
829  }
830 
831  exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
832  } else {
833  if (dsim->state == DSIM_STATE_INIT || dsim->state ==
834  DSIM_STATE_ULPS) {
835  dev_err(dsim->dev,
836  "DSI Master is not STOP or HSDT state.\n");
837  return -EINVAL;
838  }
839 
840  exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
841  }
842 
843  return 0;
844 }
845 
846 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
847 {
848  return _exynos_mipi_dsi_get_frame_done_status(dsim);
849 }
850 
851 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
852 {
853  _exynos_mipi_dsi_clear_frame_done(dsim);
854 
855  return 0;
856 }
857 
858 int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
859  unsigned int val)
860 {
861  int try = TRY_FIFO_CLEAR;
862 
863  exynos_mipi_dsi_sw_reset_release(dsim);
864  exynos_mipi_dsi_func_reset(dsim);
865 
866  do {
867  if (exynos_mipi_dsi_get_sw_reset_release(dsim)) {
868  exynos_mipi_dsi_init_interrupt(dsim);
869  dev_dbg(dsim->dev, "reset release done.\n");
870  return 0;
871  }
872  } while (--try);
873 
874  dev_err(dsim->dev, "failed to clear dsim fifo.\n");
875  return -EAGAIN;
876 }
877 
878 MODULE_AUTHOR("InKi Dae <[email protected]>");
879 MODULE_DESCRIPTION("Samusung SoC MIPI-DSI common driver");
880 MODULE_LICENSE("GPL");
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