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hda_intel.c File Reference
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/mutex.h>
#include <linux/reboot.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>
#include <linux/firmware.h>
#include "hda_codec.h"

Go to the source code of this file.

Data Structures

struct  azx_dev
 
struct  azx_rb
 
struct  azx_pcm
 
struct  azx
 

Macros

#define hda_snoop   true
 
#define azx_snoop(chip)   true
 
#define SFX   "hda-intel: "
 
#define ICH6_REG_GCAP   0x00
 
#define ICH6_GCAP_64OK   (1 << 0) /* 64bit address support */
 
#define ICH6_GCAP_NSDO   (3 << 1) /* # of serial data out signals */
 
#define ICH6_GCAP_BSS   (31 << 3) /* # of bidirectional streams */
 
#define ICH6_GCAP_ISS   (15 << 8) /* # of input streams */
 
#define ICH6_GCAP_OSS   (15 << 12) /* # of output streams */
 
#define ICH6_REG_VMIN   0x02
 
#define ICH6_REG_VMAJ   0x03
 
#define ICH6_REG_OUTPAY   0x04
 
#define ICH6_REG_INPAY   0x06
 
#define ICH6_REG_GCTL   0x08
 
#define ICH6_GCTL_RESET   (1 << 0) /* controller reset */
 
#define ICH6_GCTL_FCNTRL   (1 << 1) /* flush control */
 
#define ICH6_GCTL_UNSOL   (1 << 8) /* accept unsol. response enable */
 
#define ICH6_REG_WAKEEN   0x0c
 
#define ICH6_REG_STATESTS   0x0e
 
#define ICH6_REG_GSTS   0x10
 
#define ICH6_GSTS_FSTS   (1 << 1) /* flush status */
 
#define ICH6_REG_INTCTL   0x20
 
#define ICH6_REG_INTSTS   0x24
 
#define ICH6_REG_WALLCLK   0x30 /* 24Mhz source */
 
#define ICH6_REG_OLD_SSYNC   0x34 /* SSYNC for old ICH */
 
#define ICH6_REG_SSYNC   0x38
 
#define ICH6_REG_CORBLBASE   0x40
 
#define ICH6_REG_CORBUBASE   0x44
 
#define ICH6_REG_CORBWP   0x48
 
#define ICH6_REG_CORBRP   0x4a
 
#define ICH6_CORBRP_RST   (1 << 15) /* read pointer reset */
 
#define ICH6_REG_CORBCTL   0x4c
 
#define ICH6_CORBCTL_RUN   (1 << 1) /* enable DMA */
 
#define ICH6_CORBCTL_CMEIE   (1 << 0) /* enable memory error irq */
 
#define ICH6_REG_CORBSTS   0x4d
 
#define ICH6_CORBSTS_CMEI   (1 << 0) /* memory error indication */
 
#define ICH6_REG_CORBSIZE   0x4e
 
#define ICH6_REG_RIRBLBASE   0x50
 
#define ICH6_REG_RIRBUBASE   0x54
 
#define ICH6_REG_RIRBWP   0x58
 
#define ICH6_RIRBWP_RST   (1 << 15) /* write pointer reset */
 
#define ICH6_REG_RINTCNT   0x5a
 
#define ICH6_REG_RIRBCTL   0x5c
 
#define ICH6_RBCTL_IRQ_EN   (1 << 0) /* enable IRQ */
 
#define ICH6_RBCTL_DMA_EN   (1 << 1) /* enable DMA */
 
#define ICH6_RBCTL_OVERRUN_EN   (1 << 2) /* enable overrun irq */
 
#define ICH6_REG_RIRBSTS   0x5d
 
#define ICH6_RBSTS_IRQ   (1 << 0) /* response irq */
 
#define ICH6_RBSTS_OVERRUN   (1 << 2) /* overrun irq */
 
#define ICH6_REG_RIRBSIZE   0x5e
 
#define ICH6_REG_IC   0x60
 
#define ICH6_REG_IR   0x64
 
#define ICH6_REG_IRS   0x68
 
#define ICH6_IRS_VALID   (1<<1)
 
#define ICH6_IRS_BUSY   (1<<0)
 
#define ICH6_REG_DPLBASE   0x70
 
#define ICH6_REG_DPUBASE   0x74
 
#define ICH6_DPLBASE_ENABLE   0x1 /* Enable position buffer */
 
#define ICH6_REG_SD_CTL   0x00
 
#define ICH6_REG_SD_STS   0x03
 
#define ICH6_REG_SD_LPIB   0x04
 
#define ICH6_REG_SD_CBL   0x08
 
#define ICH6_REG_SD_LVI   0x0c
 
#define ICH6_REG_SD_FIFOW   0x0e
 
#define ICH6_REG_SD_FIFOSIZE   0x10
 
#define ICH6_REG_SD_FORMAT   0x12
 
#define ICH6_REG_SD_BDLPL   0x18
 
#define ICH6_REG_SD_BDLPU   0x1c
 
#define ICH6_PCIREG_TCSEL   0x44
 
#define ICH6_NUM_CAPTURE   4
 
#define ICH6_NUM_PLAYBACK   4
 
#define ULI_NUM_CAPTURE   5
 
#define ULI_NUM_PLAYBACK   6
 
#define ATIHDMI_NUM_CAPTURE   0
 
#define ATIHDMI_NUM_PLAYBACK   1
 
#define TERA_NUM_CAPTURE   3
 
#define TERA_NUM_PLAYBACK   4
 
#define MAX_AZX_DEV   16
 
#define BDL_SIZE   4096
 
#define AZX_MAX_BDL_ENTRIES   (BDL_SIZE / 16)
 
#define AZX_MAX_FRAG   32
 
#define AZX_MAX_BUF_SIZE   (1024*1024*1024)
 
#define RIRB_INT_RESPONSE   0x01
 
#define RIRB_INT_OVERRUN   0x04
 
#define RIRB_INT_MASK   0x05
 
#define AZX_MAX_CODECS   8
 
#define AZX_DEFAULT_CODECS   4
 
#define STATESTS_INT_MASK   ((1 << AZX_MAX_CODECS) - 1)
 
#define SD_CTL_STREAM_RESET   0x01 /* stream reset bit */
 
#define SD_CTL_DMA_START   0x02 /* stream DMA start bit */
 
#define SD_CTL_STRIPE   (3 << 16) /* stripe control */
 
#define SD_CTL_TRAFFIC_PRIO   (1 << 18) /* traffic priority */
 
#define SD_CTL_DIR   (1 << 19) /* bi-directional stream */
 
#define SD_CTL_STREAM_TAG_MASK   (0xf << 20)
 
#define SD_CTL_STREAM_TAG_SHIFT   20
 
#define SD_INT_DESC_ERR   0x10 /* descriptor error interrupt */
 
#define SD_INT_FIFO_ERR   0x08 /* FIFO error interrupt */
 
#define SD_INT_COMPLETE   0x04 /* completion interrupt */
 
#define SD_INT_MASK
 
#define SD_STS_FIFO_READY   0x20 /* FIFO ready */
 
#define ICH6_INT_ALL_STREAM   0xff /* all stream interrupts */
 
#define ICH6_INT_CTRL_EN   0x40000000 /* controller interrupt enable bit */
 
#define ICH6_INT_GLOBAL_EN   0x80000000 /* global interrupt enable bit */
 
#define ICH6_MAX_CORB_ENTRIES   256
 
#define ICH6_MAX_RIRB_ENTRIES   256
 
#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 
#define ATI_SB450_HDAUDIO_ENABLE_SNOOP   0x02
 
#define NVIDIA_HDA_TRANSREG_ADDR   0x4e
 
#define NVIDIA_HDA_ENABLE_COHBITS   0x0f
 
#define NVIDIA_HDA_ISTRM_COH   0x4d
 
#define NVIDIA_HDA_OSTRM_COH   0x4c
 
#define NVIDIA_HDA_ENABLE_COHBIT   0x01
 
#define INTEL_SCH_HDA_DEVC   0x78
 
#define INTEL_SCH_HDA_DEVC_NOSNOOP   (0x1<<11)
 
#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET   0x90
 
#define VIA_HDAC_DEVICE_ID   0x3288
 
#define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 
#define AZX_DCAPS_NO_TCSEL   (1 << 8) /* No Intel TCSEL bit */
 
#define AZX_DCAPS_NO_MSI   (1 << 9) /* No MSI support */
 
#define AZX_DCAPS_ATI_SNOOP   (1 << 10) /* ATI snoop enable */
 
#define AZX_DCAPS_NVIDIA_SNOOP   (1 << 11) /* Nvidia snoop enable */
 
#define AZX_DCAPS_SCH_SNOOP   (1 << 12) /* SCH/PCH snoop enable */
 
#define AZX_DCAPS_RIRB_DELAY   (1 << 13) /* Long delay in read loop */
 
#define AZX_DCAPS_RIRB_PRE_DELAY   (1 << 14) /* Put a delay before read */
 
#define AZX_DCAPS_CTX_WORKAROUND   (1 << 15) /* X-Fi workaround */
 
#define AZX_DCAPS_POSFIX_LPIB   (1 << 16) /* Use LPIB as default */
 
#define AZX_DCAPS_POSFIX_VIA   (1 << 17) /* Use VIACOMBO as default */
 
#define AZX_DCAPS_NO_64BIT   (1 << 18) /* No 64bit address */
 
#define AZX_DCAPS_SYNC_WRITE   (1 << 19) /* sync each cmd write */
 
#define AZX_DCAPS_OLD_SSYNC   (1 << 20) /* Old SSYNC reg for ICH */
 
#define AZX_DCAPS_BUFSIZE   (1 << 21) /* no buffer size alignment */
 
#define AZX_DCAPS_ALIGN_BUFSIZE   (1 << 22) /* buffer size alignment */
 
#define AZX_DCAPS_4K_BDLE_BOUNDARY   (1 << 23) /* BDLE in 4k boundary */
 
#define AZX_DCAPS_COUNT_LPIB_DELAY   (1 << 25) /* Take LPIB as delay */
 
#define AZX_DCAPS_PM_RUNTIME   (1 << 26) /* runtime PM support */
 
#define AZX_DCAPS_INTEL_PCH
 
#define AZX_DCAPS_PRESET_ATI_SB
 
#define AZX_DCAPS_PRESET_ATI_HDMI   (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 
#define AZX_DCAPS_PRESET_NVIDIA
 
#define AZX_DCAPS_PRESET_CTHDA   (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 
#define use_vga_switcheroo(chip)   0
 
#define DELAYED_INIT_MARK   __devinit
 
#define DELAYED_INITDATA_MARK   __devinitdata
 
#define azx_writel(chip, reg, value)   writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 
#define azx_readl(chip, reg)   readl((chip)->remap_addr + ICH6_REG_##reg)
 
#define azx_writew(chip, reg, value)   writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 
#define azx_readw(chip, reg)   readw((chip)->remap_addr + ICH6_REG_##reg)
 
#define azx_writeb(chip, reg, value)   writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 
#define azx_readb(chip, reg)   readb((chip)->remap_addr + ICH6_REG_##reg)
 
#define azx_sd_writel(dev, reg, value)   writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 
#define azx_sd_readl(dev, reg)   readl((dev)->sd_addr + ICH6_REG_##reg)
 
#define azx_sd_writew(dev, reg, value)   writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 
#define azx_sd_readw(dev, reg)   readw((dev)->sd_addr + ICH6_REG_##reg)
 
#define azx_sd_writeb(dev, reg, value)   writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 
#define azx_sd_readb(dev, reg)   readb((dev)->sd_addr + ICH6_REG_##reg)
 
#define get_azx_dev(substream)   (substream->runtime->private_data)
 
#define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 
#define azx_pcm_mmap   NULL
 
#define MAX_PREALLOC_SIZE   (32 * 1024 * 1024)
 
#define azx_add_card_list(chip)   /* NOP */
 
#define azx_del_card_list(chip)   /* NOP */
 
#define AZX_PM_OPS   NULL
 
#define init_vga_switcheroo(chip)   /* NOP */
 
#define register_vga_switcheroo(chip)   0
 
#define check_hdmi_disabled(pci)   false
 
#define AZX_FORCE_CODEC_MASK   0x100
 

Enumerations

enum  {
  SDI0, SDI1, SDI2, SDI3,
  SDO0, SDO1, SDO2, SDO3
}
 
enum  {
  POS_FIX_AUTO, POS_FIX_LPIB, POS_FIX_POSBUF, POS_FIX_VIACOMBO,
  POS_FIX_COMBO
}
 
enum  {
  AZX_DRIVER_ICH, AZX_DRIVER_PCH, AZX_DRIVER_SCH, AZX_DRIVER_ATI,
  AZX_DRIVER_ATIHDMI, AZX_DRIVER_ATIHDMI_NS, AZX_DRIVER_VIA, AZX_DRIVER_SIS,
  AZX_DRIVER_ULI, AZX_DRIVER_NVIDIA, AZX_DRIVER_TERA, AZX_DRIVER_CTX,
  AZX_DRIVER_CTHDA, AZX_DRIVER_GENERIC, AZX_NUM_DRIVERS
}
 

Functions

 module_param_array (index, int, NULL, 0444)
 
 MODULE_PARM_DESC (index,"Index value for Intel HD audio interface.")
 
 module_param_array (id, charp, NULL, 0444)
 
 MODULE_PARM_DESC (id,"ID string for Intel HD audio interface.")
 
 module_param_array (enable, bool, NULL, 0444)
 
 MODULE_PARM_DESC (enable,"Enable Intel HD audio interface.")
 
 module_param_array (model, charp, NULL, 0444)
 
 MODULE_PARM_DESC (model,"Use the given board model.")
 
 module_param_array (position_fix, int, NULL, 0444)
 
 MODULE_PARM_DESC (position_fix,"DMA pointer read method.""(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).")
 
 module_param_array (bdl_pos_adj, int, NULL, 0644)
 
 MODULE_PARM_DESC (bdl_pos_adj,"BDL position adjustment offset.")
 
 module_param_array (probe_mask, int, NULL, 0444)
 
 MODULE_PARM_DESC (probe_mask,"Bitmask to probe codecs (default = -1).")
 
 module_param_array (probe_only, int, NULL, 0444)
 
 MODULE_PARM_DESC (probe_only,"Only probing and no codec initialization.")
 
 module_param (single_cmd, bool, 0444)
 
 MODULE_PARM_DESC (single_cmd,"Use single command to communicate with codecs ""(for debugging only).")
 
 module_param (enable_msi, bint, 0444)
 
 MODULE_PARM_DESC (enable_msi,"Enable Message Signaled Interrupt (MSI)")
 
 module_param (align_buffer_size, bint, 0644)
 
 MODULE_PARM_DESC (align_buffer_size,"Force buffer and period sizes to be multiple of 128 bytes.")
 
 MODULE_LICENSE ("GPL")
 
 MODULE_SUPPORTED_DEVICE ("{{Intel, ICH6},""{Intel, ICH6M},""{Intel, ICH7},""{Intel, ESB2},""{Intel, ICH8},""{Intel, ICH9},""{Intel, ICH10},""{Intel, PCH},""{Intel, CPT},""{Intel, PPT},""{Intel, LPT},""{Intel, LPT_LP},""{Intel, HPT},""{Intel, PBG},""{Intel, SCH},""{ATI, SB450},""{ATI, SB600},""{ATI, RS600},""{ATI, RS690},""{ATI, RS780},""{ATI, R600},""{ATI, RV630},""{ATI, RV610},""{ATI, RV670},""{ATI, RV635},""{ATI, RV620},""{ATI, RV770},""{VIA, VT8251},""{VIA, VT8237A},""{SiS, SIS966},""{ULI, M5461}}")
 
 MODULE_DESCRIPTION ("Intel HDA driver")
 
 MODULE_DEVICE_TABLE (pci, azx_ids)
 
 module_pci_driver (azx_driver)
 

Macro Definition Documentation

#define ATI_SB450_HDAUDIO_ENABLE_SNOOP   0x02

Definition at line 358 of file hda_intel.c.

#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42

Definition at line 357 of file hda_intel.c.

#define ATIHDMI_NUM_CAPTURE   0

Definition at line 292 of file hda_intel.c.

#define ATIHDMI_NUM_PLAYBACK   1

Definition at line 293 of file hda_intel.c.

#define azx_add_card_list (   chip)    /* NOP */

Definition at line 2490 of file hda_intel.c.

#define AZX_DCAPS_4K_BDLE_BOUNDARY   (1 << 23) /* BDLE in 4k boundary */

Definition at line 557 of file hda_intel.c.

#define AZX_DCAPS_ALIGN_BUFSIZE   (1 << 22) /* buffer size alignment */

Definition at line 556 of file hda_intel.c.

#define AZX_DCAPS_ATI_SNOOP   (1 << 10) /* ATI snoop enable */

Definition at line 544 of file hda_intel.c.

#define AZX_DCAPS_BUFSIZE   (1 << 21) /* no buffer size alignment */

Definition at line 555 of file hda_intel.c.

#define AZX_DCAPS_COUNT_LPIB_DELAY   (1 << 25) /* Take LPIB as delay */

Definition at line 558 of file hda_intel.c.

#define AZX_DCAPS_CTX_WORKAROUND   (1 << 15) /* X-Fi workaround */

Definition at line 549 of file hda_intel.c.

#define AZX_DCAPS_INTEL_PCH
Value:
AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME)

Definition at line 562 of file hda_intel.c.

#define AZX_DCAPS_NO_64BIT   (1 << 18) /* No 64bit address */

Definition at line 552 of file hda_intel.c.

#define AZX_DCAPS_NO_MSI   (1 << 9) /* No MSI support */

Definition at line 543 of file hda_intel.c.

#define AZX_DCAPS_NO_TCSEL   (1 << 8) /* No Intel TCSEL bit */

Definition at line 542 of file hda_intel.c.

#define AZX_DCAPS_NVIDIA_SNOOP   (1 << 11) /* Nvidia snoop enable */

Definition at line 545 of file hda_intel.c.

#define AZX_DCAPS_OLD_SSYNC   (1 << 20) /* Old SSYNC reg for ICH */

Definition at line 554 of file hda_intel.c.

#define AZX_DCAPS_PM_RUNTIME   (1 << 26) /* runtime PM support */

Definition at line 559 of file hda_intel.c.

#define AZX_DCAPS_POSFIX_LPIB   (1 << 16) /* Use LPIB as default */

Definition at line 550 of file hda_intel.c.

#define AZX_DCAPS_POSFIX_VIA   (1 << 17) /* Use VIACOMBO as default */

Definition at line 551 of file hda_intel.c.

#define AZX_DCAPS_PRESET_ATI_HDMI   (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)

Definition at line 572 of file hda_intel.c.

#define AZX_DCAPS_PRESET_ATI_SB
Value:

Definition at line 567 of file hda_intel.c.

#define AZX_DCAPS_PRESET_CTHDA   (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)

Definition at line 580 of file hda_intel.c.

#define AZX_DCAPS_PRESET_NVIDIA
Value:

Definition at line 576 of file hda_intel.c.

#define AZX_DCAPS_RIRB_DELAY   (1 << 13) /* Long delay in read loop */

Definition at line 547 of file hda_intel.c.

#define AZX_DCAPS_RIRB_PRE_DELAY   (1 << 14) /* Put a delay before read */

Definition at line 548 of file hda_intel.c.

#define AZX_DCAPS_SCH_SNOOP   (1 << 12) /* SCH/PCH snoop enable */

Definition at line 546 of file hda_intel.c.

#define AZX_DCAPS_SYNC_WRITE   (1 << 19) /* sync each cmd write */

Definition at line 553 of file hda_intel.c.

#define AZX_DEFAULT_CODECS   4

Definition at line 316 of file hda_intel.c.

#define azx_del_card_list (   chip)    /* NOP */

Definition at line 2491 of file hda_intel.c.

#define AZX_FORCE_CODEC_MASK   0x100

Definition at line 2906 of file hda_intel.c.

#define AZX_MAX_BDL_ENTRIES   (BDL_SIZE / 16)

Definition at line 304 of file hda_intel.c.

#define AZX_MAX_BUF_SIZE   (1024*1024*1024)

Definition at line 307 of file hda_intel.c.

#define AZX_MAX_CODECS   8

Definition at line 315 of file hda_intel.c.

#define AZX_MAX_FRAG   32

Definition at line 305 of file hda_intel.c.

#define azx_pcm_mmap   NULL

Definition at line 2287 of file hda_intel.c.

#define AZX_PM_OPS   NULL

Definition at line 2588 of file hda_intel.c.

#define azx_readb (   chip,
  reg 
)    readb((chip)->remap_addr + ICH6_REG_##reg)

Definition at line 630 of file hda_intel.c.

#define azx_readl (   chip,
  reg 
)    readl((chip)->remap_addr + ICH6_REG_##reg)

Definition at line 622 of file hda_intel.c.

#define azx_readw (   chip,
  reg 
)    readw((chip)->remap_addr + ICH6_REG_##reg)

Definition at line 626 of file hda_intel.c.

#define azx_sd_readb (   dev,
  reg 
)    readb((dev)->sd_addr + ICH6_REG_##reg)

Definition at line 643 of file hda_intel.c.

#define azx_sd_readl (   dev,
  reg 
)    readl((dev)->sd_addr + ICH6_REG_##reg)

Definition at line 635 of file hda_intel.c.

#define azx_sd_readw (   dev,
  reg 
)    readw((dev)->sd_addr + ICH6_REG_##reg)

Definition at line 639 of file hda_intel.c.

#define azx_sd_writeb (   dev,
  reg,
  value 
)    writeb(value, (dev)->sd_addr + ICH6_REG_##reg)

Definition at line 641 of file hda_intel.c.

#define azx_sd_writel (   dev,
  reg,
  value 
)    writel(value, (dev)->sd_addr + ICH6_REG_##reg)

Definition at line 633 of file hda_intel.c.

#define azx_sd_writew (   dev,
  reg,
  value 
)    writew(value, (dev)->sd_addr + ICH6_REG_##reg)

Definition at line 637 of file hda_intel.c.

#define azx_snoop (   chip)    true

Definition at line 147 of file hda_intel.c.

#define azx_writeb (   chip,
  reg,
  value 
)    writeb(value, (chip)->remap_addr + ICH6_REG_##reg)

Definition at line 628 of file hda_intel.c.

#define azx_writel (   chip,
  reg,
  value 
)    writel(value, (chip)->remap_addr + ICH6_REG_##reg)

Definition at line 620 of file hda_intel.c.

#define azx_writew (   chip,
  reg,
  value 
)    writew(value, (chip)->remap_addr + ICH6_REG_##reg)

Definition at line 624 of file hda_intel.c.

#define BDL_SIZE   4096

Definition at line 303 of file hda_intel.c.

#define check_hdmi_disabled (   pci)    false

Definition at line 2720 of file hda_intel.c.

#define DELAYED_INIT_MARK   __devinit

Definition at line 596 of file hda_intel.c.

#define DELAYED_INITDATA_MARK   __devinitdata

Definition at line 597 of file hda_intel.c.

#define get_azx_dev (   substream)    (substream->runtime->private_data)

Definition at line 647 of file hda_intel.c.

#define hda_snoop   true

Definition at line 146 of file hda_intel.c.

#define ICH6_CORBCTL_CMEIE   (1 << 0) /* enable memory error irq */

Definition at line 231 of file hda_intel.c.

#define ICH6_CORBCTL_RUN   (1 << 1) /* enable DMA */

Definition at line 230 of file hda_intel.c.

#define ICH6_CORBRP_RST   (1 << 15) /* read pointer reset */

Definition at line 228 of file hda_intel.c.

#define ICH6_CORBSTS_CMEI   (1 << 0) /* memory error indication */

Definition at line 233 of file hda_intel.c.

#define ICH6_DPLBASE_ENABLE   0x1 /* Enable position buffer */

Definition at line 258 of file hda_intel.c.

#define ICH6_GCAP_64OK   (1 << 0) /* 64bit address support */

Definition at line 202 of file hda_intel.c.

#define ICH6_GCAP_BSS   (31 << 3) /* # of bidirectional streams */

Definition at line 204 of file hda_intel.c.

#define ICH6_GCAP_ISS   (15 << 8) /* # of input streams */

Definition at line 205 of file hda_intel.c.

#define ICH6_GCAP_NSDO   (3 << 1) /* # of serial data out signals */

Definition at line 203 of file hda_intel.c.

#define ICH6_GCAP_OSS   (15 << 12) /* # of output streams */

Definition at line 206 of file hda_intel.c.

#define ICH6_GCTL_FCNTRL   (1 << 1) /* flush control */

Definition at line 213 of file hda_intel.c.

#define ICH6_GCTL_RESET   (1 << 0) /* controller reset */

Definition at line 212 of file hda_intel.c.

#define ICH6_GCTL_UNSOL   (1 << 8) /* accept unsol. response enable */

Definition at line 214 of file hda_intel.c.

#define ICH6_GSTS_FSTS   (1 << 1) /* flush status */

Definition at line 218 of file hda_intel.c.

#define ICH6_INT_ALL_STREAM   0xff /* all stream interrupts */

Definition at line 339 of file hda_intel.c.

#define ICH6_INT_CTRL_EN   0x40000000 /* controller interrupt enable bit */

Definition at line 340 of file hda_intel.c.

#define ICH6_INT_GLOBAL_EN   0x80000000 /* global interrupt enable bit */

Definition at line 341 of file hda_intel.c.

#define ICH6_IRS_BUSY   (1<<0)

Definition at line 254 of file hda_intel.c.

#define ICH6_IRS_VALID   (1<<1)

Definition at line 253 of file hda_intel.c.

#define ICH6_MAX_CORB_ENTRIES   256

Definition at line 344 of file hda_intel.c.

#define ICH6_MAX_RIRB_ENTRIES   256

Definition at line 345 of file hda_intel.c.

#define ICH6_NUM_CAPTURE   4

Definition at line 284 of file hda_intel.c.

#define ICH6_NUM_PLAYBACK   4

Definition at line 285 of file hda_intel.c.

#define ICH6_PCIREG_TCSEL   0x44

Definition at line 276 of file hda_intel.c.

#define ICH6_RBCTL_DMA_EN   (1 << 1) /* enable DMA */

Definition at line 243 of file hda_intel.c.

#define ICH6_RBCTL_IRQ_EN   (1 << 0) /* enable IRQ */

Definition at line 242 of file hda_intel.c.

#define ICH6_RBCTL_OVERRUN_EN   (1 << 2) /* enable overrun irq */

Definition at line 244 of file hda_intel.c.

#define ICH6_RBSTS_IRQ   (1 << 0) /* response irq */

Definition at line 246 of file hda_intel.c.

#define ICH6_RBSTS_OVERRUN   (1 << 2) /* overrun irq */

Definition at line 247 of file hda_intel.c.

#define ICH6_REG_CORBCTL   0x4c

Definition at line 229 of file hda_intel.c.

#define ICH6_REG_CORBLBASE   0x40

Definition at line 224 of file hda_intel.c.

#define ICH6_REG_CORBRP   0x4a

Definition at line 227 of file hda_intel.c.

#define ICH6_REG_CORBSIZE   0x4e

Definition at line 234 of file hda_intel.c.

#define ICH6_REG_CORBSTS   0x4d

Definition at line 232 of file hda_intel.c.

#define ICH6_REG_CORBUBASE   0x44

Definition at line 225 of file hda_intel.c.

#define ICH6_REG_CORBWP   0x48

Definition at line 226 of file hda_intel.c.

#define ICH6_REG_DPLBASE   0x70

Definition at line 256 of file hda_intel.c.

#define ICH6_REG_DPUBASE   0x74

Definition at line 257 of file hda_intel.c.

#define ICH6_REG_GCAP   0x00

Definition at line 201 of file hda_intel.c.

#define ICH6_REG_GCTL   0x08

Definition at line 211 of file hda_intel.c.

#define ICH6_REG_GSTS   0x10

Definition at line 217 of file hda_intel.c.

#define ICH6_REG_IC   0x60

Definition at line 250 of file hda_intel.c.

#define ICH6_REG_INPAY   0x06

Definition at line 210 of file hda_intel.c.

#define ICH6_REG_INTCTL   0x20

Definition at line 219 of file hda_intel.c.

#define ICH6_REG_INTSTS   0x24

Definition at line 220 of file hda_intel.c.

#define ICH6_REG_IR   0x64

Definition at line 251 of file hda_intel.c.

#define ICH6_REG_IRS   0x68

Definition at line 252 of file hda_intel.c.

#define ICH6_REG_OLD_SSYNC   0x34 /* SSYNC for old ICH */

Definition at line 222 of file hda_intel.c.

#define ICH6_REG_OUTPAY   0x04

Definition at line 209 of file hda_intel.c.

#define ICH6_REG_RINTCNT   0x5a

Definition at line 240 of file hda_intel.c.

#define ICH6_REG_RIRBCTL   0x5c

Definition at line 241 of file hda_intel.c.

#define ICH6_REG_RIRBLBASE   0x50

Definition at line 236 of file hda_intel.c.

#define ICH6_REG_RIRBSIZE   0x5e

Definition at line 248 of file hda_intel.c.

#define ICH6_REG_RIRBSTS   0x5d

Definition at line 245 of file hda_intel.c.

#define ICH6_REG_RIRBUBASE   0x54

Definition at line 237 of file hda_intel.c.

#define ICH6_REG_RIRBWP   0x58

Definition at line 238 of file hda_intel.c.

#define ICH6_REG_SD_BDLPL   0x18

Definition at line 272 of file hda_intel.c.

#define ICH6_REG_SD_BDLPU   0x1c

Definition at line 273 of file hda_intel.c.

#define ICH6_REG_SD_CBL   0x08

Definition at line 267 of file hda_intel.c.

#define ICH6_REG_SD_CTL   0x00

Definition at line 264 of file hda_intel.c.

#define ICH6_REG_SD_FIFOSIZE   0x10

Definition at line 270 of file hda_intel.c.

#define ICH6_REG_SD_FIFOW   0x0e

Definition at line 269 of file hda_intel.c.

#define ICH6_REG_SD_FORMAT   0x12

Definition at line 271 of file hda_intel.c.

#define ICH6_REG_SD_LPIB   0x04

Definition at line 266 of file hda_intel.c.

#define ICH6_REG_SD_LVI   0x0c

Definition at line 268 of file hda_intel.c.

#define ICH6_REG_SD_STS   0x03

Definition at line 265 of file hda_intel.c.

#define ICH6_REG_SSYNC   0x38

Definition at line 223 of file hda_intel.c.

#define ICH6_REG_STATESTS   0x0e

Definition at line 216 of file hda_intel.c.

#define ICH6_REG_VMAJ   0x03

Definition at line 208 of file hda_intel.c.

#define ICH6_REG_VMIN   0x02

Definition at line 207 of file hda_intel.c.

#define ICH6_REG_WAKEEN   0x0c

Definition at line 215 of file hda_intel.c.

#define ICH6_REG_WALLCLK   0x30 /* 24Mhz source */

Definition at line 221 of file hda_intel.c.

#define ICH6_RIRB_EX_UNSOL_EV   (1<<4)

Definition at line 809 of file hda_intel.c.

#define ICH6_RIRBWP_RST   (1 << 15) /* write pointer reset */

Definition at line 239 of file hda_intel.c.

#define init_vga_switcheroo (   chip)    /* NOP */

Definition at line 2718 of file hda_intel.c.

#define INTEL_SCH_HDA_DEVC   0x78

Definition at line 368 of file hda_intel.c.

#define INTEL_SCH_HDA_DEVC_NOSNOOP   (0x1<<11)

Definition at line 369 of file hda_intel.c.

#define MAX_AZX_DEV   16

Definition at line 300 of file hda_intel.c.

#define MAX_PREALLOC_SIZE   (32 * 1024 * 1024)

Definition at line 2312 of file hda_intel.c.

#define NVIDIA_HDA_ENABLE_COHBIT   0x01

Definition at line 365 of file hda_intel.c.

#define NVIDIA_HDA_ENABLE_COHBITS   0x0f

Definition at line 362 of file hda_intel.c.

#define NVIDIA_HDA_ISTRM_COH   0x4d

Definition at line 363 of file hda_intel.c.

#define NVIDIA_HDA_OSTRM_COH   0x4c

Definition at line 364 of file hda_intel.c.

#define NVIDIA_HDA_TRANSREG_ADDR   0x4e

Definition at line 361 of file hda_intel.c.

#define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403

Definition at line 377 of file hda_intel.c.

#define register_vga_switcheroo (   chip)    0

Definition at line 2719 of file hda_intel.c.

#define RIRB_INT_MASK   0x05

Definition at line 312 of file hda_intel.c.

#define RIRB_INT_OVERRUN   0x04

Definition at line 311 of file hda_intel.c.

#define RIRB_INT_RESPONSE   0x01

Definition at line 310 of file hda_intel.c.

#define SD_CTL_DIR   (1 << 19) /* bi-directional stream */

Definition at line 324 of file hda_intel.c.

#define SD_CTL_DMA_START   0x02 /* stream DMA start bit */

Definition at line 321 of file hda_intel.c.

#define SD_CTL_STREAM_RESET   0x01 /* stream reset bit */

Definition at line 320 of file hda_intel.c.

#define SD_CTL_STREAM_TAG_MASK   (0xf << 20)

Definition at line 325 of file hda_intel.c.

#define SD_CTL_STREAM_TAG_SHIFT   20

Definition at line 326 of file hda_intel.c.

#define SD_CTL_STRIPE   (3 << 16) /* stripe control */

Definition at line 322 of file hda_intel.c.

#define SD_CTL_TRAFFIC_PRIO   (1 << 18) /* traffic priority */

Definition at line 323 of file hda_intel.c.

#define SD_INT_COMPLETE   0x04 /* completion interrupt */

Definition at line 331 of file hda_intel.c.

#define SD_INT_DESC_ERR   0x10 /* descriptor error interrupt */

Definition at line 329 of file hda_intel.c.

#define SD_INT_FIFO_ERR   0x08 /* FIFO error interrupt */

Definition at line 330 of file hda_intel.c.

#define SD_INT_MASK
Value:
SD_INT_COMPLETE)

Definition at line 332 of file hda_intel.c.

#define SD_STS_FIFO_READY   0x20 /* FIFO ready */

Definition at line 336 of file hda_intel.c.

#define SFX   "hda-intel: "

Definition at line 188 of file hda_intel.c.

#define STATESTS_INT_MASK   ((1 << AZX_MAX_CODECS) - 1)

Definition at line 317 of file hda_intel.c.

#define TERA_NUM_CAPTURE   3

Definition at line 296 of file hda_intel.c.

#define TERA_NUM_PLAYBACK   4

Definition at line 297 of file hda_intel.c.

#define ULI_NUM_CAPTURE   5

Definition at line 288 of file hda_intel.c.

#define ULI_NUM_PLAYBACK   6

Definition at line 289 of file hda_intel.c.

#define use_vga_switcheroo (   chip)    0

Definition at line 589 of file hda_intel.c.

#define VIA_HDAC_DEVICE_ID   0x3288

Definition at line 374 of file hda_intel.c.

#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET   0x90

Definition at line 372 of file hda_intel.c.

Enumeration Type Documentation

anonymous enum
Enumerator:
SDI0 
SDI1 
SDI2 
SDI3 
SDO0 
SDO1 
SDO2 
SDO3 

Definition at line 261 of file hda_intel.c.

anonymous enum
Enumerator:
POS_FIX_AUTO 
POS_FIX_LPIB 
POS_FIX_POSBUF 
POS_FIX_VIACOMBO 
POS_FIX_COMBO 

Definition at line 348 of file hda_intel.c.

anonymous enum
Enumerator:
AZX_DRIVER_ICH 
AZX_DRIVER_PCH 
AZX_DRIVER_SCH 
AZX_DRIVER_ATI 
AZX_DRIVER_ATIHDMI 
AZX_DRIVER_ATIHDMI_NS 
AZX_DRIVER_VIA 
AZX_DRIVER_SIS 
AZX_DRIVER_ULI 
AZX_DRIVER_NVIDIA 
AZX_DRIVER_TERA 
AZX_DRIVER_CTX 
AZX_DRIVER_CTHDA 
AZX_DRIVER_GENERIC 
AZX_NUM_DRIVERS 

Definition at line 522 of file hda_intel.c.

Function Documentation

MODULE_DESCRIPTION ( "Intel HDA driver )
MODULE_DEVICE_TABLE ( pci  ,
azx_ids   
)
MODULE_LICENSE ( "GPL"  )
module_param ( single_cmd  ,
bool  ,
0444   
)
module_param ( enable_msi  ,
bint  ,
0444   
)
module_param ( align_buffer_size  ,
bint  ,
0644   
)
module_param_array ( index  ,
int  ,
NULL  ,
0444   
)
module_param_array ( id  ,
charp  ,
NULL  ,
0444   
)
module_param_array ( enable  ,
bool  ,
NULL  ,
0444   
)
module_param_array ( model  ,
charp  ,
NULL  ,
0444   
)
module_param_array ( position_fix  ,
int  ,
NULL  ,
0444   
)
module_param_array ( bdl_pos_adj  ,
int  ,
NULL  ,
0644   
)
module_param_array ( probe_mask  ,
int  ,
NULL  ,
0444   
)
module_param_array ( probe_only  ,
int  ,
NULL  ,
0444   
)
MODULE_PARM_DESC ( index  ,
"Index value for Intel HD audio interface."   
)
MODULE_PARM_DESC ( id  ,
"ID string for Intel HD audio interface."   
)
MODULE_PARM_DESC ( enable  ,
"Enable Intel HD audio interface."   
)
MODULE_PARM_DESC ( model  ,
"Use the given board model."   
)
MODULE_PARM_DESC ( position_fix  ,
"DMA pointer read method.""(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."   
)
MODULE_PARM_DESC ( bdl_pos_adj  ,
"BDL position adjustment offset."   
)
MODULE_PARM_DESC ( probe_mask  ,
"Bitmask to probe codecs (default = -1)."   
)
MODULE_PARM_DESC ( probe_only  ,
"Only probing and no codec initialization."   
)
MODULE_PARM_DESC ( single_cmd  ,
"Use single command to communicate with codecs ""(for debugging only)."   
)
MODULE_PARM_DESC ( enable_msi  ,
"Enable Message Signaled Interrupt (MSI)"   
)
MODULE_PARM_DESC ( align_buffer_size  ,
"Force buffer and period sizes to be multiple of 128 bytes."   
)
module_pci_driver ( azx_driver  )
MODULE_SUPPORTED_DEVICE ( "{{Intel, ICH6},""{Intel, ICH6M},""{Intel, ICH7},""{Intel, ESB2},""{Intel, ICH8},""{Intel, ICH9},""{Intel, ICH10},""{Intel, PCH},""{Intel, CPT},""{Intel, PPT},""{Intel, LPT},""{Intel, LPT_LP},""{Intel, HPT},""{Intel, PBG},""{Intel, SCH},""{ATI, SB450},""{ATI, SB600},""{ATI, RS600},""{ATI, RS690},""{ATI, RS780},""{ATI, R600},""{ATI, RV630},""{ATI, RV610},""{ATI, RV670},""{ATI, RV635},""{ATI, RV620},""{ATI, RV770},""{VIA, VT8251},""{VIA, VT8237A},""{SiS, SIS966},""{ULI, M5461}}"  )