5 #include <linux/wireless.h>
6 #include <linux/netdevice.h>
15 #define MAX_PARM_DEVICES 8
16 #define PARM_MIN_MAX "1-" __MODULE_STRING(MAX_PARM_DEVICES)
17 #define DEF_INTS -1, -1, -1, -1, -1, -1, -1
18 #define GET_INT_PARM(var,idx) var[var[idx] < 0 ? 0 : idx]
27 #define ETH_P_HOSTAP ETH_P_CONTROL
72 #define LWNG_CAP_DID_BASE (4 | (1 << 6))
73 #define LWNG_CAPHDR_VERSION 0x80211001
142 #define HFA384X_LEVEL_TO_dBm(v) 0x100 + (v) * 100 / 255 - 100
144 #define HFA384X_LEVEL_TO_dBm_sign(v) (v) * 100 / 255 - 100
219 #define HFA384X_SCAN_IN_PROGRESS 0
220 #define HFA384X_SCAN_HOST_INITIATED 1
221 #define HFA384X_SCAN_FIRMWARE_INITIATED 2
222 #define HFA384X_SCAN_INQUIRY_FROM_HOST 3
225 #define HFA384X_SCAN_MAX_RESULTS 32
288 #if defined(PRISM2_PCCARD) || defined(PRISM2_PLX)
290 #define HFA384X_CMD_OFF 0x00
291 #define HFA384X_PARAM0_OFF 0x02
292 #define HFA384X_PARAM1_OFF 0x04
293 #define HFA384X_PARAM2_OFF 0x06
294 #define HFA384X_STATUS_OFF 0x08
295 #define HFA384X_RESP0_OFF 0x0A
296 #define HFA384X_RESP1_OFF 0x0C
297 #define HFA384X_RESP2_OFF 0x0E
298 #define HFA384X_INFOFID_OFF 0x10
299 #define HFA384X_CONTROL_OFF 0x14
300 #define HFA384X_SELECT0_OFF 0x18
301 #define HFA384X_SELECT1_OFF 0x1A
302 #define HFA384X_OFFSET0_OFF 0x1C
303 #define HFA384X_OFFSET1_OFF 0x1E
304 #define HFA384X_RXFID_OFF 0x20
305 #define HFA384X_ALLOCFID_OFF 0x22
306 #define HFA384X_TXCOMPLFID_OFF 0x24
307 #define HFA384X_SWSUPPORT0_OFF 0x28
308 #define HFA384X_SWSUPPORT1_OFF 0x2A
309 #define HFA384X_SWSUPPORT2_OFF 0x2C
310 #define HFA384X_EVSTAT_OFF 0x30
311 #define HFA384X_INTEN_OFF 0x32
312 #define HFA384X_EVACK_OFF 0x34
313 #define HFA384X_DATA0_OFF 0x36
314 #define HFA384X_DATA1_OFF 0x38
315 #define HFA384X_AUXPAGE_OFF 0x3A
316 #define HFA384X_AUXOFFSET_OFF 0x3C
317 #define HFA384X_AUXDATA_OFF 0x3E
322 #define HFA384X_CMD_OFF 0x00
323 #define HFA384X_PARAM0_OFF 0x04
324 #define HFA384X_PARAM1_OFF 0x08
325 #define HFA384X_PARAM2_OFF 0x0C
326 #define HFA384X_STATUS_OFF 0x10
327 #define HFA384X_RESP0_OFF 0x14
328 #define HFA384X_RESP1_OFF 0x18
329 #define HFA384X_RESP2_OFF 0x1C
330 #define HFA384X_INFOFID_OFF 0x20
331 #define HFA384X_CONTROL_OFF 0x28
332 #define HFA384X_SELECT0_OFF 0x30
333 #define HFA384X_SELECT1_OFF 0x34
334 #define HFA384X_OFFSET0_OFF 0x38
335 #define HFA384X_OFFSET1_OFF 0x3C
336 #define HFA384X_RXFID_OFF 0x40
337 #define HFA384X_ALLOCFID_OFF 0x44
338 #define HFA384X_TXCOMPLFID_OFF 0x48
339 #define HFA384X_PCICOR_OFF 0x4C
340 #define HFA384X_SWSUPPORT0_OFF 0x50
341 #define HFA384X_SWSUPPORT1_OFF 0x54
342 #define HFA384X_SWSUPPORT2_OFF 0x58
343 #define HFA384X_PCIHCR_OFF 0x5C
344 #define HFA384X_EVSTAT_OFF 0x60
345 #define HFA384X_INTEN_OFF 0x64
346 #define HFA384X_EVACK_OFF 0x68
347 #define HFA384X_DATA0_OFF 0x6C
348 #define HFA384X_DATA1_OFF 0x70
349 #define HFA384X_AUXPAGE_OFF 0x74
350 #define HFA384X_AUXOFFSET_OFF 0x78
351 #define HFA384X_AUXDATA_OFF 0x7C
352 #define HFA384X_PCI_M0_ADDRH_OFF 0x80
353 #define HFA384X_PCI_M0_ADDRL_OFF 0x84
354 #define HFA384X_PCI_M0_LEN_OFF 0x88
355 #define HFA384X_PCI_M0_CTL_OFF 0x8C
356 #define HFA384X_PCI_STATUS_OFF 0x98
357 #define HFA384X_PCI_M1_ADDRH_OFF 0xA0
358 #define HFA384X_PCI_M1_ADDRL_OFF 0xA4
359 #define HFA384X_PCI_M1_LEN_OFF 0xA8
360 #define HFA384X_PCI_M1_CTL_OFF 0xAC
364 #define HFA384X_PCI_CTL_FROM_BAP (BIT(5) | BIT(1) | BIT(0))
365 #define HFA384X_PCI_CTL_TO_BAP (BIT(5) | BIT(0))
371 #define HFA384X_CMDCODE_INIT 0x00
372 #define HFA384X_CMDCODE_ENABLE 0x01
373 #define HFA384X_CMDCODE_DISABLE 0x02
374 #define HFA384X_CMDCODE_ALLOC 0x0A
375 #define HFA384X_CMDCODE_TRANSMIT 0x0B
376 #define HFA384X_CMDCODE_INQUIRE 0x11
377 #define HFA384X_CMDCODE_ACCESS 0x21
378 #define HFA384X_CMDCODE_ACCESS_WRITE (0x21 | BIT(8))
379 #define HFA384X_CMDCODE_DOWNLOAD 0x22
380 #define HFA384X_CMDCODE_READMIF 0x30
381 #define HFA384X_CMDCODE_WRITEMIF 0x31
382 #define HFA384X_CMDCODE_TEST 0x38
384 #define HFA384X_CMDCODE_MASK 0x3F
387 #define HFA384X_TEST_CHANGE_CHANNEL 0x08
388 #define HFA384X_TEST_MONITOR 0x0B
389 #define HFA384X_TEST_STOP 0x0F
390 #define HFA384X_TEST_CFG_BITS 0x15
391 #define HFA384X_TEST_CFG_BIT_ALC BIT(3)
393 #define HFA384X_CMD_BUSY BIT(15)
395 #define HFA384X_CMD_TX_RECLAIM BIT(8)
397 #define HFA384X_OFFSET_ERR BIT(14)
398 #define HFA384X_OFFSET_BUSY BIT(15)
402 #define HFA384X_PROGMODE_DISABLE 0
403 #define HFA384X_PROGMODE_ENABLE_VOLATILE 1
404 #define HFA384X_PROGMODE_ENABLE_NON_VOLATILE 2
405 #define HFA384X_PROGMODE_PROGRAM_NON_VOLATILE 3
407 #define HFA384X_AUX_MAGIC0 0xfe01
408 #define HFA384X_AUX_MAGIC1 0xdc23
409 #define HFA384X_AUX_MAGIC2 0xba45
411 #define HFA384X_AUX_PORT_DISABLED 0
412 #define HFA384X_AUX_PORT_DISABLE BIT(14)
413 #define HFA384X_AUX_PORT_ENABLE BIT(15)
414 #define HFA384X_AUX_PORT_ENABLED (BIT(14) | BIT(15))
415 #define HFA384X_AUX_PORT_MASK (BIT(14) | BIT(15))
417 #define PRISM2_PDA_SIZE 1024
421 #define HFA384X_EV_TICK BIT(15)
422 #define HFA384X_EV_WTERR BIT(14)
423 #define HFA384X_EV_INFDROP BIT(13)
425 #define HFA384X_EV_PCI_M1 BIT(9)
426 #define HFA384X_EV_PCI_M0 BIT(8)
428 #define HFA384X_EV_INFO BIT(7)
429 #define HFA384X_EV_DTIM BIT(5)
430 #define HFA384X_EV_CMD BIT(4)
431 #define HFA384X_EV_ALLOC BIT(3)
432 #define HFA384X_EV_TXEXC BIT(2)
433 #define HFA384X_EV_TX BIT(1)
434 #define HFA384X_EV_RX BIT(0)
438 #define HFA384X_INFO_HANDOVERADDR 0xF000
439 #define HFA384X_INFO_HANDOVERDEAUTHADDR 0xF001
440 #define HFA384X_INFO_COMMTALLIES 0xF100
441 #define HFA384X_INFO_SCANRESULTS 0xF101
442 #define HFA384X_INFO_CHANNELINFORESULTS 0xF102
443 #define HFA384X_INFO_HOSTSCANRESULTS 0xF103
444 #define HFA384X_INFO_LINKSTATUS 0xF200
445 #define HFA384X_INFO_ASSOCSTATUS 0xF201
446 #define HFA384X_INFO_AUTHREQ 0xF202
447 #define HFA384X_INFO_PSUSERCNT 0xF203
448 #define HFA384X_INFO_KEYIDCHANGED 0xF204
461 #define HFA384X_RATES_1MBPS BIT(0)
462 #define HFA384X_RATES_2MBPS BIT(1)
463 #define HFA384X_RATES_5MBPS BIT(2)
464 #define HFA384X_RATES_11MBPS BIT(3)
466 #define HFA384X_ROAMING_FIRMWARE 1
467 #define HFA384X_ROAMING_HOST 2
468 #define HFA384X_ROAMING_DISABLED 3
470 #define HFA384X_WEPFLAGS_PRIVACYINVOKED BIT(0)
471 #define HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED BIT(1)
472 #define HFA384X_WEPFLAGS_HOSTENCRYPT BIT(4)
473 #define HFA384X_WEPFLAGS_HOSTDECRYPT BIT(7)
475 #define HFA384X_RX_STATUS_MSGTYPE (BIT(15) | BIT(14) | BIT(13))
476 #define HFA384X_RX_STATUS_PCF BIT(12)
477 #define HFA384X_RX_STATUS_MACPORT (BIT(10) | BIT(9) | BIT(8))
478 #define HFA384X_RX_STATUS_UNDECR BIT(1)
479 #define HFA384X_RX_STATUS_FCSERR BIT(0)
481 #define HFA384X_RX_STATUS_GET_MSGTYPE(s) \
482 (((s) & HFA384X_RX_STATUS_MSGTYPE) >> 13)
483 #define HFA384X_RX_STATUS_GET_MACPORT(s) \
484 (((s) & HFA384X_RX_STATUS_MACPORT) >> 8)
490 #define HFA384X_TX_CTRL_ALT_RTRY BIT(5)
491 #define HFA384X_TX_CTRL_802_11 BIT(3)
492 #define HFA384X_TX_CTRL_802_3 0
493 #define HFA384X_TX_CTRL_TX_EX BIT(2)
494 #define HFA384X_TX_CTRL_TX_OK BIT(1)
496 #define HFA384X_TX_STATUS_RETRYERR BIT(0)
497 #define HFA384X_TX_STATUS_AGEDERR BIT(1)
498 #define HFA384X_TX_STATUS_DISCON BIT(2)
499 #define HFA384X_TX_STATUS_FORMERR BIT(3)
502 #define HFA386X_CR_TX_CONFIGURE 0x12
503 #define HFA386X_CR_RX_CONFIGURE 0x14
504 #define HFA386X_CR_A_D_TEST_MODES2 0x1A
505 #define HFA386X_CR_MANUAL_TX_POWER 0x3E
506 #define HFA386X_CR_MEASURED_TX_POWER 0x74
511 #define PRISM2_TXFID_COUNT 8
512 #define PRISM2_DATA_MAXLEN 2304
513 #define PRISM2_TXFID_LEN (PRISM2_DATA_MAXLEN + sizeof(struct hfa384x_tx_frame))
514 #define PRISM2_TXFID_EMPTY 0xffff
515 #define PRISM2_TXFID_RESERVED 0xfffe
516 #define PRISM2_DUMMY_FID 0xffff
517 #define MAX_SSID_LEN 32
518 #define MAX_NAME_LEN 32
520 #define PRISM2_DUMP_RX_HDR BIT(0)
521 #define PRISM2_DUMP_TX_HDR BIT(1)
522 #define PRISM2_DUMP_TXEXC_HDR BIT(2)
524 struct hostap_tx_callback_info {
528 struct hostap_tx_callback_info *
next;
536 #define PRISM2_FRAG_CACHE_LEN 4
538 struct prism2_frag_entry {
539 unsigned long first_frag_time;
541 unsigned int last_frag;
548 struct hostap_cmd_queue {
551 volatile enum { CMD_SLEEP, CMD_CALLBACK, CMD_COMPLETED }
type;
557 volatile int issued, issuing;
564 #define HOSTAP_HW_NO_DISABLE BIT(0)
565 #define HOSTAP_HW_ENABLE_CMDCOMPL BIT(1)
569 struct prism2_helper_functions {
602 int need_tx_headroom;
604 enum { HOSTAP_HW_PCCARD, HOSTAP_HW_PLX, HOSTAP_HW_PCI }
hw_type;
608 struct prism2_download_data {
612 struct prism2_download_data_area {
620 #define HOSTAP_MAX_BSS_COUNT 64
621 #define MAX_WPA_IE_LEN 64
623 struct hostap_bss_info {
625 unsigned long last_update;
648 int master_dev_auto_open;
659 struct mutex rid_bap_mtx;
665 u16 txfid[PRISM2_TXFID_COUNT];
668 u16 intransmitfid[PRISM2_TXFID_COUNT];
675 #define HOSTAP_BITS_TRANSMIT 0
676 #define HOSTAP_BITS_BAP_TASKLET 1
677 #define HOSTAP_BITS_BAP_TASKLET2 2
682 char essid[MAX_SSID_LEN + 1];
686 u16 scan_channel_mask;
698 int fw_tx_rate_control;
711 PRISM2_TXPOWER_AUTO = 0, PRISM2_TXPOWER_OFF,
712 PRISM2_TXPOWER_FIXED, PRISM2_TXPOWER_UNKNOWN
721 #define HOSTAP_CMD_QUEUE_MAX_LEN 16
736 int wds_max_connections;
738 #define HOSTAP_WDS_BROADCAST_RA BIT(0)
739 #define HOSTAP_WDS_AP_CLIENT BIT(1)
740 #define HOSTAP_WDS_STANDARD_FRAME BIT(2)
743 int manual_retry_count;
747 unsigned long scan_timestamp;
749 PRISM2_MONITOR_80211 = 0, PRISM2_MONITOR_PRISM = 1,
750 PRISM2_MONITOR_CAPHDR = 2, PRISM2_MONITOR_RADIOTAP = 3
752 int monitor_allow_fcserr;
766 #define WEP_KEY_LEN 13
779 struct prism2_frag_entry frag_cache[PRISM2_FRAG_CACHE_LEN];
780 unsigned int frag_next_idx;
784 int antsel_tx, antsel_rx;
792 struct prism2_helper_functions *
func;
796 #define PRISM2_FW_VER(major, minor, variant) \
797 (((major) << 16) | ((minor) << 8) | variant)
808 struct hostap_tx_callback_info *tx_callback;
818 unsigned long last_join_time;
820 int last_scan_results_count;
821 enum { PRISM2_SCAN, PRISM2_HOSTSCAN } last_scan_type;
823 unsigned long pending_info;
824 #define PRISM2_INFO_PENDING_LINKSTATUS 0
825 #define PRISM2_INFO_PENDING_SCANRESULTS 1
826 int prev_link_status;
827 int prev_linkstatus_connected;
830 #ifdef PRISM2_CALLBACK
840 int passive_scan_interval;
841 int passive_scan_channel;
842 enum { PASSIVE_SCAN_WAIT, PASSIVE_SCAN_LISTEN } passive_scan_state;
845 unsigned long last_tick_timer;
846 unsigned int sw_tick_stuck;
850 unsigned long last_comms_qual_update;
863 int tkip_countermeasures;
864 int drop_unencrypted;
868 size_t generic_elem_len;
870 #ifdef PRISM2_DOWNLOAD_SUPPORT
872 struct prism2_download_data *dl_pri;
873 struct prism2_download_data *dl_sec;
876 #ifdef PRISM2_IO_DEBUG
877 #define PRISM2_IO_DEBUG_SIZE 10000
878 u32 io_debug[PRISM2_IO_DEBUG_SIZE];
880 int io_debug_enabled;
891 struct hostap_interface {
894 struct local_info *local;
900 HOSTAP_INTERFACE_MASTER,
901 HOSTAP_INTERFACE_MAIN,
903 HOSTAP_INTERFACE_STA,
904 HOSTAP_INTERFACE_WDS,
908 struct hostap_interface_wds {
915 #define HOSTAP_SKB_TX_DATA_MAGIC 0xf08a36a2
923 struct hostap_skb_tx_data {
924 unsigned int __padding_for_default_qdiscs;
927 #define HOSTAP_TX_FLAGS_WDS BIT(0)
928 #define HOSTAP_TX_FLAGS_BUFFERED_FRAME BIT(1)
929 #define HOSTAP_TX_FLAGS_ADD_MOREDATA BIT(2)
932 struct hostap_interface *iface;
938 #ifndef PRISM2_NO_DEBUG
940 #define DEBUG_FID BIT(0)
941 #define DEBUG_PS BIT(1)
942 #define DEBUG_FLOW BIT(2)
943 #define DEBUG_AP BIT(3)
944 #define DEBUG_HW BIT(4)
945 #define DEBUG_EXTRA BIT(5)
946 #define DEBUG_EXTRA2 BIT(6)
947 #define DEBUG_PS2 BIT(7)
948 #define DEBUG_MASK (DEBUG_PS | DEBUG_AP | DEBUG_HW | DEBUG_EXTRA)
949 #define PDEBUG(n, args...) \
950 do { if ((n) & DEBUG_MASK) printk(KERN_DEBUG args); } while (0)
951 #define PDEBUG2(n, args...) \
952 do { if ((n) & DEBUG_MASK) printk(args); } while (0)
956 #define PDEBUG(n, args...)
957 #define PDEBUG2(n, args...)
963 #define PRISM2_IO_DEBUG_CMD_INB 0
964 #define PRISM2_IO_DEBUG_CMD_INW 1
965 #define PRISM2_IO_DEBUG_CMD_INSW 2
966 #define PRISM2_IO_DEBUG_CMD_OUTB 3
967 #define PRISM2_IO_DEBUG_CMD_OUTW 4
968 #define PRISM2_IO_DEBUG_CMD_OUTSW 5
969 #define PRISM2_IO_DEBUG_CMD_ERROR 6
970 #define PRISM2_IO_DEBUG_CMD_INTERRUPT 7
972 #ifdef PRISM2_IO_DEBUG
974 #define PRISM2_IO_DEBUG_ENTRY(cmd, reg, value) \
975 (((cmd) << 24) | ((reg) << 16) | value)
980 struct hostap_interface *iface = netdev_priv(dev);
983 if (!local->io_debug_enabled)
986 local->io_debug[local->io_debug_head] =
jiffies & 0xffffffff;
987 if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
988 local->io_debug_head = 0;
989 local->io_debug[local->io_debug_head] =
990 PRISM2_IO_DEBUG_ENTRY(cmd, reg, value);
991 if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
992 local->io_debug_head = 0;
996 static inline void prism2_io_debug_error(
struct net_device *dev,
int err)
998 struct hostap_interface *iface = netdev_priv(dev);
1000 unsigned long flags;
1002 if (!local->io_debug_enabled)
1006 prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_ERROR, 0, err);
1007 if (local->io_debug_enabled == 1) {
1008 local->io_debug_enabled = 0;
1011 spin_unlock_irqrestore(&local->lock, flags);
1016 static inline void prism2_io_debug_add(
struct net_device *dev,
int cmd,
1021 static inline void prism2_io_debug_error(
struct net_device *dev,
int err)
1028 #ifdef PRISM2_CALLBACK
1031 PRISM2_CALLBACK_ENABLE,
1034 PRISM2_CALLBACK_DISABLE,
1037 PRISM2_CALLBACK_RX_START, PRISM2_CALLBACK_RX_END,
1038 PRISM2_CALLBACK_TX_START, PRISM2_CALLBACK_TX_END
1042 #define prism2_callback(d, e) do { } while (0)