Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
Data Structures | Macros | Enumerations | Functions
i3000_edac.c File Reference
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_core.h"

Go to the source code of this file.

Data Structures

struct  i3000_dev_info
 
struct  i3000_error_info
 

Macros

#define I3000_REVISION   "1.1"
 
#define EDAC_MOD_STR   "i3000_edac"
 
#define I3000_RANKS   8
 
#define I3000_RANKS_PER_CHANNEL   4
 
#define I3000_CHANNELS   2
 
#define I3000_MCHBAR   0x44 /* MCH Memory Mapped Register BAR */
 
#define I3000_MCHBAR_MASK   0xffffc000
 
#define I3000_MMR_WINDOW_SIZE   16384
 
#define I3000_EDEAP
 
#define I3000_DEAP
 
#define I3000_DEAP_GRAIN   (1 << 7)
 
#define I3000_DERRSYN
 
#define I3000_ERRSTS
 
#define I3000_ERRSTS_BITS   0x0b03 /* bits which indicate errors */
 
#define I3000_ERRSTS_UE   0x0002
 
#define I3000_ERRSTS_CE   0x0001
 
#define I3000_ERRCMD
 
#define I3000_DRB_SHIFT   25 /* 32MiB grain */
 
#define I3000_C0DRB
 
#define I3000_C1DRB
 
#define I3000_C0DRA
 
#define I3000_C1DRA   0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
 
#define I3000_C0DRC0
 
#define I3000_C0DRC1
 

Enumerations

enum  i3000p_chips { I3000 = 0 }
 

Functions

 MODULE_DEVICE_TABLE (pci, i3000_pci_tbl)
 
 module_init (i3000_init)
 
 module_exit (i3000_exit)
 
 MODULE_LICENSE ("GPL")
 
 MODULE_AUTHOR ("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott")
 
 MODULE_DESCRIPTION ("MC support for Intel 3000 memory hub controllers")
 
 module_param (edac_op_state, int, 0444)
 
 MODULE_PARM_DESC (edac_op_state,"EDAC Error Reporting state: 0=Poll,1=NMI")
 

Macro Definition Documentation

#define EDAC_MOD_STR   "i3000_edac"

Definition at line 21 of file i3000_edac.c.

#define I3000_C0DRA
Value:
0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
*
* 7 reserved
* 6:4 DRAM odd Rank Attribute
* 3 reserved
* 2:0 DRAM even Rank Attribute
*
* Each attribute defines the page
* size of the corresponding rank:
* 000: unpopulated
* 001: reserved
* 010: 4 KB
* 011: 8 KB
* 100: 16 KB
* Others: reserved
*/

Definition at line 77 of file i3000_edac.c.

#define I3000_C0DRB
Value:
0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
*
* 7:0 Channel 0 DRAM Rank Boundary Address
*/

Definition at line 74 of file i3000_edac.c.

#define I3000_C0DRC0
Value:
0x120 /* DRAM Controller Mode 0 (32b)
*
* 31:30 reserved
* 29 Initialization Complete (IC)
* 28:11 reserved
* 10:8 Refresh Mode Select (RMS)
* 7 reserved
* 6:4 Mode Select (SMS)
* 3:2 reserved
* 1:0 DRAM Type (DT)
*/

Definition at line 90 of file i3000_edac.c.

#define I3000_C0DRC1
Value:
0x124 /* DRAM Controller Mode 1 (32b)
*
* 31 Enhanced Addressing Enable (ENHADE)
* 30:0 reserved
*/

Definition at line 92 of file i3000_edac.c.

#define I3000_C1DRA   0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */

Definition at line 78 of file i3000_edac.c.

#define I3000_C1DRB
Value:
0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
*
* 7:0 Channel 1 DRAM Rank Boundary Address
*/

Definition at line 75 of file i3000_edac.c.

#define I3000_CHANNELS   2

Definition at line 25 of file i3000_edac.c.

#define I3000_DEAP
Value:
0x58 /* DRAM Error Address Pointer (32b)
*
* 31:7 address
* 6:1 reserved
* 0 Error channel 0/1
*/

Definition at line 34 of file i3000_edac.c.

#define I3000_DEAP_GRAIN   (1 << 7)

Definition at line 35 of file i3000_edac.c.

#define I3000_DERRSYN
Value:
0x5c /* DRAM Error Syndrome (8b)
*
* 7:0 DRAM ECC Syndrome
*/

Definition at line 61 of file i3000_edac.c.

#define I3000_DRB_SHIFT   25 /* 32MiB grain */

Definition at line 72 of file i3000_edac.c.

#define I3000_EDEAP
Value:
0x70 /* Extended DRAM Error Address Pointer (8b)
*
* 7:1 reserved
* 0 bit 32 of address
*/

Definition at line 33 of file i3000_edac.c.

#define I3000_ERRCMD
Value:
0xca /* Error Command (16b)
*
* 15:12 reserved
* 11 SERR on MCH Thermal Sensor Event
* (TSESERR)
* 10 reserved
* 9 SERR on LOCK to non-DRAM Memory
* (LCKERR)
* 8 SERR on DRAM Refresh Timeout
* (DRTOERR)
* 7:2 reserved
* 1 SERR Multi-Bit DRAM ECC Error
* (DMERR)
* 0 SERR on Single-Bit ECC Error
* (DSERR)
*/

Definition at line 68 of file i3000_edac.c.

#define I3000_ERRSTS
Value:
0xc8 /* Error Status Register (16b)
*
* 15:12 reserved
* 11 MCH Thermal Sensor Event
* for SMI/SCI/SERR
* 10 reserved
* 9 LOCK to non-DRAM Memory Flag (LCKF)
* 8 Received Refresh Timeout Flag (RRTOF)
* 7:2 reserved
* 1 Multi-bit DRAM ECC Error Flag (DMERR)
* 0 Single-bit DRAM ECC Error Flag (DSERR)
*/

Definition at line 63 of file i3000_edac.c.

#define I3000_ERRSTS_BITS   0x0b03 /* bits which indicate errors */

Definition at line 64 of file i3000_edac.c.

#define I3000_ERRSTS_CE   0x0001

Definition at line 66 of file i3000_edac.c.

#define I3000_ERRSTS_UE   0x0002

Definition at line 65 of file i3000_edac.c.

#define I3000_MCHBAR   0x44 /* MCH Memory Mapped Register BAR */

Definition at line 29 of file i3000_edac.c.

#define I3000_MCHBAR_MASK   0xffffc000

Definition at line 30 of file i3000_edac.c.

#define I3000_MMR_WINDOW_SIZE   16384

Definition at line 31 of file i3000_edac.c.

#define I3000_RANKS   8

Definition at line 23 of file i3000_edac.c.

#define I3000_RANKS_PER_CHANNEL   4

Definition at line 24 of file i3000_edac.c.

#define I3000_REVISION   "1.1"

Definition at line 19 of file i3000_edac.c.

Enumeration Type Documentation

enum i3000p_chips
Enumerator:
I3000 

Definition at line 94 of file i3000_edac.c.

Function Documentation

MODULE_AUTHOR ( "Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott"  )
MODULE_DESCRIPTION ( "MC support for Intel 3000 memory hub controllers"  )
MODULE_DEVICE_TABLE ( pci  ,
i3000_pci_tbl   
)
module_exit ( i3000_exit  )
module_init ( i3000_init  )
MODULE_LICENSE ( "GPL"  )
module_param ( edac_op_state  ,
int  ,
0444   
)
MODULE_PARM_DESC ( edac_op_state  ,
"EDAC Error Reporting state:  0 = Poll 
)
Generated on Thu Jan 10 2013 15:28:51 for Linux Kernel by   doxygen 1.8.2