#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include <linux/io.h>
#include "edac_core.h"
#include <asm-generic/io-64-nonatomic-lo-hi.h>

Data Structures
struct	i3200_priv

struct	i3200_dev_info

struct	i3200_error_info

Macros
#define	I3200_REVISION "1.1"

#define	EDAC_MOD_STR "i3200_edac"

#define	PCI_DEVICE_ID_INTEL_3200_HB 0x29f0

#define	I3200_DIMMS 4

#define	I3200_RANKS 8

#define	I3200_RANKS_PER_CHANNEL 4

#define	I3200_CHANNELS 2

#define	I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */

#define	I3200_MCHBAR_HIGH 0x4c

#define	I3200_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */

#define	I3200_MMR_WINDOW_SIZE 16384

#define	I3200_TOM

#define	I3200_TOM_MASK 0x3ff /* bits 9:0 */

#define	I3200_TOM_SHIFT 26 /* 64MiB grain */

#define	I3200_ERRSTS

#define	I3200_ERRSTS_UE 0x0002

#define	I3200_ERRSTS_CE 0x0001

#define	I3200_ERRSTS_BITS (I3200_ERRSTS_UE \| I3200_ERRSTS_CE)

#define	I3200_C0DRB

#define	I3200_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */

#define	I3200_DRB_MASK 0x3ff /* bits 9:0 */

#define	I3200_DRB_SHIFT 26 /* 64MiB grain */

#define	I3200_C0ECCERRLOG

#define	I3200_C1ECCERRLOG 0x680 /* Chan 1 ECC Error Log (64b) */

#define	I3200_ECCERRLOG_CE 0x1

#define	I3200_ECCERRLOG_UE 0x2

#define	I3200_ECCERRLOG_RANK_BITS 0x18000000

#define	I3200_ECCERRLOG_RANK_SHIFT 27

#define	I3200_ECCERRLOG_SYNDROME_BITS 0xff0000

#define	I3200_ECCERRLOG_SYNDROME_SHIFT 16

#define	I3200_CAPID0 0xe0 /* P.95 of spec for details */

Enumerations
enum	i3200_chips { I3200 = 0 }

Functions
void __iomem *	i3200_map_mchbar (struct pci_dev *pdev)

	MODULE_DEVICE_TABLE (pci, i3200_pci_tbl)

	module_init (i3200_init)

	module_exit (i3200_exit)

	MODULE_LICENSE ("GPL")

	MODULE_AUTHOR ("Akamai Technologies, Inc.")

	MODULE_DESCRIPTION ("MC support for Intel 3200 memory hub controllers")

	module_param (edac_op_state, int, 0444)

	MODULE_PARM_DESC (edac_op_state,"EDAC Error Reporting state: 0=Poll,1=NMI")

Macro Definition Documentation

#define EDAC_MOD_STR "i3200_edac"

Definition at line 22 of file i3200_edac.c.

#define I3200_C0DRB

Value:

0x200   /* Channel 0 DRAM Rank Boundary (16b x 4)
         *
         * 15:10 reserved
         *  9:0  Channel 0 DRAM Rank Boundary Address
         */

Definition at line 50 of file i3200_edac.c.

#define I3200_C0ECCERRLOG

Value:

0x280   /* Channel 0 ECC Error Log (64b)
         *
         * 63:48 Error Column Address (ERRCOL)
         * 47:32 Error Row Address (ERRROW)
         * 31:29 Error Bank Address (ERRBANK)
         * 28:27 Error Rank Address (ERRRANK)
         * 26:24 reserved
         * 23:16 Error Syndrome (ERRSYND)
         * 15: 2 reserved
         *    1  Multiple Bit Error Status (MERRSTS)
         *    0  Correctable Error Status (CERRSTS)
         */

Definition at line 55 of file i3200_edac.c.

#define I3200_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */

Definition at line 51 of file i3200_edac.c.

#define I3200_C1ECCERRLOG 0x680 /* Chan 1 ECC Error Log (64b) */

Definition at line 56 of file i3200_edac.c.

#define I3200_CAPID0 0xe0 /* P.95 of spec for details */

Definition at line 63 of file i3200_edac.c.

#define I3200_CHANNELS 2

Definition at line 29 of file i3200_edac.c.

#define I3200_DIMMS 4

Definition at line 26 of file i3200_edac.c.

#define I3200_DRB_MASK 0x3ff /* bits 9:0 */

Definition at line 52 of file i3200_edac.c.

#define I3200_DRB_SHIFT 26 /* 64MiB grain */

Definition at line 53 of file i3200_edac.c.

#define I3200_ECCERRLOG_CE 0x1

Definition at line 57 of file i3200_edac.c.

#define I3200_ECCERRLOG_RANK_BITS 0x18000000

Definition at line 59 of file i3200_edac.c.

#define I3200_ECCERRLOG_RANK_SHIFT 27

Definition at line 60 of file i3200_edac.c.

#define I3200_ECCERRLOG_SYNDROME_BITS 0xff0000

Definition at line 61 of file i3200_edac.c.

#define I3200_ECCERRLOG_SYNDROME_SHIFT 16

Definition at line 62 of file i3200_edac.c.

#define I3200_ECCERRLOG_UE 0x2

Definition at line 58 of file i3200_edac.c.

#define I3200_ERRSTS

Value:

0xc8    /* Error Status Register (16b)
         *
         * 15    reserved
         * 14    Isochronous TBWRR Run Behind FIFO Full
         *       (ITCV)
         * 13    Isochronous TBWRR Run Behind FIFO Put
         *       (ITSTV)
         * 12    reserved
         * 11    MCH Thermal Sensor Event
         *       for SMI/SCI/SERR (GTSE)
         * 10    reserved
         *  9    LOCK to non-DRAM Memory Flag (LCKF)
         *  8    reserved
         *  7    DRAM Throttle Flag (DTF)
         *  6:2  reserved
         *  1    Multi-bit DRAM ECC Error Flag (DMERR)
         *  0    Single-bit DRAM ECC Error Flag (DSERR)
         */

Definition at line 42 of file i3200_edac.c.

#define I3200_ERRSTS_BITS (I3200_ERRSTS_UE | I3200_ERRSTS_CE)

Definition at line 45 of file i3200_edac.c.

#define I3200_ERRSTS_CE 0x0001

Definition at line 44 of file i3200_edac.c.

#define I3200_ERRSTS_UE 0x0002

Definition at line 43 of file i3200_edac.c.

#define I3200_MCHBAR_HIGH 0x4c

Definition at line 34 of file i3200_edac.c.

#define I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */

Definition at line 33 of file i3200_edac.c.

#define I3200_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */

Definition at line 35 of file i3200_edac.c.

#define I3200_MMR_WINDOW_SIZE 16384

Definition at line 36 of file i3200_edac.c.

#define I3200_RANKS 8

Definition at line 27 of file i3200_edac.c.

#define I3200_RANKS_PER_CHANNEL 4

Definition at line 28 of file i3200_edac.c.

#define I3200_REVISION "1.1"

Definition at line 20 of file i3200_edac.c.

#define I3200_TOM

Value:

0xa0    /* Top of Memory (16b)
         *
         * 15:10 reserved
         *  9:0  total populated physical memory
         */

Definition at line 38 of file i3200_edac.c.

#define I3200_TOM_MASK 0x3ff /* bits 9:0 */

Definition at line 39 of file i3200_edac.c.

#define I3200_TOM_SHIFT 26 /* 64MiB grain */

Definition at line 40 of file i3200_edac.c.

#define PCI_DEVICE_ID_INTEL_3200_HB 0x29f0

Definition at line 24 of file i3200_edac.c.

Enumeration Type Documentation

enum i3200_chips

Enumerator:

I3200

Definition at line 98 of file i3200_edac.c.

Function Documentation

void __iomem* i3200_map_mchbar ( struct pci_dev * pdev )

Definition at line 218 of file i3200_edac.c.

MODULE_AUTHOR	(	"Akamai	Technologies,
		Inc."
	)

MODULE_DESCRIPTION ( "MC support for Intel 3200 memory hub controllers" )

MODULE_DEVICE_TABLE	(	pci	,
		i3200_pci_tbl
	)

module_exit ( i3200_exit )

module_init ( i3200_init )

MODULE_LICENSE ( "GPL" )

module_param	(	edac_op_state	,
		int	,
		0444
	)

MODULE_PARM_DESC	(	edac_op_state	,
		"EDAC Error Reporting state:	0 = `Poll`
	)

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation