|
| #define | EP_NO(ep) ((ep->bEndpointAddress) & ~USB_DIR_IN) /* IN:1, OUT:0 */ |
| |
| #define | EP_DIR(ep) ((ep->bEndpointAddress) & USB_DIR_IN ? 1 : 0) |
| |
| #define | IMX_USB_NB_EP 6 |
| |
| #define | USB_FRAME (0x00) /* USB frame */ |
| |
| #define | USB_SPEC (0x04) /* USB Spec */ |
| |
| #define | USB_STAT (0x08) /* USB Status */ |
| |
| #define | USB_CTRL (0x0C) /* USB Control */ |
| |
| #define | USB_DADR (0x10) /* USB Desc RAM addr */ |
| |
| #define | USB_DDAT (0x14) /* USB Desc RAM/EP buffer data */ |
| |
| #define | USB_INTR (0x18) /* USB interrupt */ |
| |
| #define | USB_MASK (0x1C) /* USB Mask */ |
| |
| #define | USB_ENAB (0x24) /* USB Enable */ |
| |
| #define | USB_EP_STAT(x) (0x30 + (x*0x30)) /* USB status/control */ |
| |
| #define | USB_EP_INTR(x) (0x34 + (x*0x30)) /* USB interrupt */ |
| |
| #define | USB_EP_MASK(x) (0x38 + (x*0x30)) /* USB mask */ |
| |
| #define | USB_EP_FDAT(x) (0x3C + (x*0x30)) /* USB FIFO data */ |
| |
| #define | USB_EP_FDAT0(x) (0x3C + (x*0x30)) /* USB FIFO data */ |
| |
| #define | USB_EP_FDAT1(x) (0x3D + (x*0x30)) /* USB FIFO data */ |
| |
| #define | USB_EP_FDAT2(x) (0x3E + (x*0x30)) /* USB FIFO data */ |
| |
| #define | USB_EP_FDAT3(x) (0x3F + (x*0x30)) /* USB FIFO data */ |
| |
| #define | USB_EP_FSTAT(x) (0x40 + (x*0x30)) /* USB FIFO status */ |
| |
| #define | USB_EP_FCTRL(x) (0x44 + (x*0x30)) /* USB FIFO control */ |
| |
| #define | USB_EP_LRFP(x) (0x48 + (x*0x30)) /* USB last rd f. pointer */ |
| |
| #define | USB_EP_LWFP(x) (0x4C + (x*0x30)) /* USB last wr f. pointer */ |
| |
| #define | USB_EP_FALRM(x) (0x50 + (x*0x30)) /* USB FIFO alarm */ |
| |
| #define | USB_EP_FRDP(x) (0x54 + (x*0x30)) /* USB FIFO read pointer */ |
| |
| #define | USB_EP_FWRP(x) (0x58 + (x*0x30)) /* USB FIFO write pointer */ |
| |
| #define | CTRL_CMDOVER (1<<6) /* UDC status */ |
| |
| #define | CTRL_CMDERROR (1<<5) /* UDC status */ |
| |
| #define | CTRL_FE_ENA (1<<3) /* Enable Font End logic */ |
| |
| #define | CTRL_UDC_RST (1<<2) /* UDC reset */ |
| |
| #define | CTRL_AFE_ENA (1<<1) /* Analog Font end enable */ |
| |
| #define | CTRL_RESUME (1<<0) /* UDC resume */ |
| |
| #define | STAT_RST (1<<8) |
| |
| #define | STAT_SUSP (1<<7) |
| |
| #define | STAT_CFG (3<<5) |
| |
| #define | STAT_INTF (3<<3) |
| |
| #define | STAT_ALTSET (7<<0) |
| |
| #define | INTR_WAKEUP (1<<31) /* Wake up Interrupt */ |
| |
| #define | INTR_MSOF (1<<7) /* Missed Start of Frame */ |
| |
| #define | INTR_SOF (1<<6) /* Start of Frame */ |
| |
| #define | INTR_RESET_STOP (1<<5) /* Reset Signaling stop */ |
| |
| #define | INTR_RESET_START (1<<4) /* Reset Signaling start */ |
| |
| #define | INTR_RESUME (1<<3) /* Suspend to resume */ |
| |
| #define | INTR_SUSPEND (1<<2) /* Active to suspend */ |
| |
| #define | INTR_FRAME_MATCH (1<<1) /* Frame matched */ |
| |
| #define | INTR_CFG_CHG (1<<0) /* Configuration change occurred */ |
| |
| #define | ENAB_RST (1<<31) /* Reset USB modules */ |
| |
| #define | ENAB_ENAB (1<<30) /* Enable USB modules*/ |
| |
| #define | ENAB_SUSPEND (1<<29) /* Suspend USB modules */ |
| |
| #define | ENAB_ENDIAN (1<<28) /* Endian of USB modules */ |
| |
| #define | ENAB_PWRMD (1<<0) /* Power mode of USB modules */ |
| |
| #define | DADR_CFG (1<<31) /* Configuration */ |
| |
| #define | DADR_BSY (1<<30) /* Busy status */ |
| |
| #define | DADR_DADR (0x1FF) /* Descriptor Ram Address */ |
| |
| #define | DDAT_DDAT (0xFF) /* Descriptor Endpoint Buffer */ |
| |
| #define | EPSTAT_BCOUNT (0x7F<<16) /* Endpoint FIFO byte count */ |
| |
| #define | EPSTAT_SIP (1<<8) /* Endpoint setup in progress */ |
| |
| #define | EPSTAT_DIR (1<<7) /* Endpoint transfer direction */ |
| |
| #define | EPSTAT_MAX (3<<5) /* Endpoint Max packet size */ |
| |
| #define | EPSTAT_TYP (3<<3) /* Endpoint type */ |
| |
| #define | EPSTAT_ZLPS (1<<2) /* Send zero length packet */ |
| |
| #define | EPSTAT_FLUSH (1<<1) /* Endpoint FIFO Flush */ |
| |
| #define | EPSTAT_STALL (1<<0) /* Force stall */ |
| |
| #define | FSTAT_FRAME_STAT (0xF<<24) /* Frame status bit [0-3] */ |
| |
| #define | FSTAT_ERR (1<<22) /* FIFO error */ |
| |
| #define | FSTAT_UF (1<<21) /* FIFO underflow */ |
| |
| #define | FSTAT_OF (1<<20) /* FIFO overflow */ |
| |
| #define | FSTAT_FR (1<<19) /* FIFO frame ready */ |
| |
| #define | FSTAT_FULL (1<<18) /* FIFO full */ |
| |
| #define | FSTAT_ALRM (1<<17) /* FIFO alarm */ |
| |
| #define | FSTAT_EMPTY (1<<16) /* FIFO empty */ |
| |
| #define | FCTRL_WFR (1<<29) /* Write frame end */ |
| |
| #define | EPINTR_FIFO_FULL (1<<8) /* fifo full */ |
| |
| #define | EPINTR_FIFO_EMPTY (1<<7) /* fifo empty */ |
| |
| #define | EPINTR_FIFO_ERROR (1<<6) /* fifo error */ |
| |
| #define | EPINTR_FIFO_HIGH (1<<5) /* fifo high */ |
| |
| #define | EPINTR_FIFO_LOW (1<<4) /* fifo low */ |
| |
| #define | EPINTR_MDEVREQ (1<<3) /* multi Device request */ |
| |
| #define | EPINTR_EOT (1<<2) /* fifo end of transfer */ |
| |
| #define | EPINTR_DEVREQ (1<<1) /* Device request */ |
| |
| #define | EPINTR_EOF (1<<0) /* fifo end of frame */ |
| |
| #define | D_REQ(dev, args...) do {} while (0) |
| |
| #define | D_TRX(dev, args...) do {} while (0) |
| |
| #define | D_INI(dev, args...) do {} while (0) |
| |
| #define | D_EP0(dev, args...) do {} while (0) |
| |
| #define | D_EPX(dev, args...) do {} while (0) |
| |
| #define | dump_ep_intr(x, y, z, i) do {} while (0) |
| |
| #define | dump_intr(x, y, z) do {} while (0) |
| |
| #define | dump_ep_stat(x, y) do {} while (0) |
| |
| #define | dump_usb_stat(x, y) do {} while (0) |
| |
| #define | dump_req(x, y, z) do {} while (0) |
| |
| #define | D_ERR(dev, args...) do {} while (0) |
| |
1.8.2