#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/usb/otg.h>

Data Structures
struct	stats

struct	udc_usb_ep

struct	pxa_ep

struct	pxa27x_request

struct	udc_stats

struct	pxa_udc

Macros
#define	UDCCR 0x0000 /* UDC Control Register */

#define	UDCICR0 0x0004 /* UDC Interrupt Control Register0 */

#define	UDCICR1 0x0008 /* UDC Interrupt Control Register1 */

#define	UDCISR0 0x000C /* UDC Interrupt Status Register 0 */

#define	UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */

#define	UDCFNR 0x0014 /* UDC Frame Number Register */

#define	UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */

#define	UP2OCR 0x0020 /* USB Port 2 Output Control register */

#define	UP3OCR 0x0024 /* USB Port 3 Output Control register */

#define	UDCCSRn(x) (0x0100 + ((x)<<2)) /* UDC Control/Status register */

#define	UDCBCRn(x) (0x0200 + ((x)<<2)) /* UDC Byte Count Register */

#define	UDCDRn(x) (0x0300 + ((x)<<2)) /* UDC Data Register */

#define	UDCCRn(x) (0x0400 + ((x)<<2)) /* UDC Control Register */

#define	UDCCR_OEN (1 << 31) /* On-the-Go Enable */

#define	UDCCR_AALTHNP

#define	UDCCR_AHNP

#define	UDCCR_BHNP

#define	UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */

#define	UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */

#define	UDCCR_ACN_S 11

#define	UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */

#define	UDCCR_AIN_S 8

#define	UDCCR_AAISN

#define	UDCCR_AAISN_S 5

#define	UDCCR_SMAC

#define	UDCCR_EMCE

#define	UDCCR_UDR (1 << 2) /* UDC Resume */

#define	UDCCR_UDA (1 << 1) /* UDC Active */

#define	UDCCR_UDE (1 << 0) /* UDC Enable */

#define	UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))

#define	UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */

#define	UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */

#define	UDCICR1_IERU (1 << 29) /* IntEn - Resume */

#define	UDCICR1_IESU (1 << 28) /* IntEn - Suspend */

#define	UDCICR1_IERS (1 << 27) /* IntEn - Reset */

#define	UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */

#define	UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */

#define	UDCICR_INT_MASK (UDCICR_FIFOERR \| UDCICR_PKTCOMPL)

#define	UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))

#define	UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */

#define	UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */

#define	UDCISR1_IRRU (1 << 29) /* IntReq - Resume */

#define	UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */

#define	UDCISR1_IRRS (1 << 27) /* IntReq - Reset */

#define	UDCISR_INT_MASK (UDCICR_FIFOERR \| UDCICR_PKTCOMPL)

#define	UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */

#define	UDCOTGICR_IEXR

#define	UDCOTGICR_IEXF

#define	UDCOTGICR_IEVV40R

#define	UDCOTGICR_IEVV40F

#define	UDCOTGICR_IEVV44R

#define	UDCOTGICR_IEVV44F

#define	UDCOTGICR_IESVR

#define	UDCOTGICR_IESVF

#define	UDCOTGICR_IESDR

#define	UDCOTGICR_IESDF

#define	UDCOTGICR_IEIDR

#define	UDCOTGICR_IEIDF

#define	UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */

#define	UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */

#define	UP2OCR_DPPDE (1 << 2) /* D+ Pull Down Enable */

#define	UP2OCR_DMPDE (1 << 3) /* D- Pull Down Enable */

#define	UP2OCR_DPPUE (1 << 4) /* D+ Pull Up Enable */

#define	UP2OCR_DMPUE (1 << 5) /* D- Pull Up Enable */

#define	UP2OCR_DPPUBE (1 << 6) /* D+ Pull Up Bypass Enable */

#define	UP2OCR_DMPUBE (1 << 7) /* D- Pull Up Bypass Enable */

#define	UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */

#define	UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */

#define	UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */

#define	UP2OCR_HXS (1 << 16) /* Transceiver Output Select */

#define	UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */

#define	UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */

#define	UDCCSR0_ACM (1 << 9) /* Ack Control Mode */

#define	UDCCSR0_AREN (1 << 8) /* Ack Response Enable */

#define	UDCCSR0_SA (1 << 7) /* Setup Active */

#define	UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */

#define	UDCCSR0_FST (1 << 5) /* Force Stall */

#define	UDCCSR0_SST (1 << 4) /* Sent Stall */

#define	UDCCSR0_DME (1 << 3) /* DMA Enable */

#define	UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */

#define	UDCCSR0_IPR (1 << 1) /* IN Packet Ready */

#define	UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */

#define	UDCCSR_DPE (1 << 9) /* Data Packet Error */

#define	UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */

#define	UDCCSR_SP (1 << 7) /* Short Packet Control/Status */

#define	UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */

#define	UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */

#define	UDCCSR_FST (1 << 5) /* Force STALL */

#define	UDCCSR_SST (1 << 4) /* Sent STALL */

#define	UDCCSR_DME (1 << 3) /* DMA Enable */

#define	UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */

#define	UDCCSR_PC (1 << 1) /* Packet Complete */

#define	UDCCSR_FS (1 << 0) /* FIFO needs service */

#define	UDCCONR_CN (0x03 << 25) /* Configuration Number */

#define	UDCCONR_CN_S 25

#define	UDCCONR_IN (0x07 << 22) /* Interface Number */

#define	UDCCONR_IN_S 22

#define	UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */

#define	UDCCONR_AISN_S 19

#define	UDCCONR_EN (0x0f << 15) /* Endpoint Number */

#define	UDCCONR_EN_S 15

#define	UDCCONR_ET (0x03 << 13) /* Endpoint Type: */

#define	UDCCONR_ET_S 13

#define	UDCCONR_ET_INT (0x03 << 13) /* Interrupt */

#define	UDCCONR_ET_BULK (0x02 << 13) /* Bulk */

#define	UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */

#define	UDCCONR_ET_NU (0x00 << 13) /* Not used */

#define	UDCCONR_ED (1 << 12) /* Endpoint Direction */

#define	UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */

#define	UDCCONR_MPS_S 2

#define	UDCCONR_DE (1 << 1) /* Double Buffering Enable */

#define	UDCCONR_EE (1 << 0) /* Endpoint Enable */

#define	UDCCR_MASK_BITS (UDCCR_OEN \| UDCCR_SMAC \| UDCCR_UDR \| UDCCR_UDE)

#define	UDCCSR_WR_MASK (UDCCSR_DME \| UDCCSR_FST)

#define	UDC_FNR_MASK (0x7ff)

#define	UDC_BCR_MASK (0x3ff)

#define	ofs_UDCCR(ep) (UDCCRn(ep->idx))

#define	ofs_UDCCSR(ep) (UDCCSRn(ep->idx))

#define	ofs_UDCBCR(ep) (UDCBCRn(ep->idx))

#define	ofs_UDCDR(ep) (UDCDRn(ep->idx))

#define	udc_ep_readl(ep, reg) __raw_readl((ep)->dev->regs + ofs_##reg(ep))

#define	udc_ep_writel(ep, reg, value) __raw_writel((value), ep->dev->regs + ofs_##reg(ep))

#define	udc_ep_readb(ep, reg) __raw_readb((ep)->dev->regs + ofs_##reg(ep))

#define	udc_ep_writeb(ep, reg, value) __raw_writeb((value), ep->dev->regs + ofs_##reg(ep))

#define	udc_readl(dev, reg) __raw_readl((dev)->regs + (reg))

#define	udc_writel(udc, reg, value) __raw_writel((value), (udc)->regs + (reg))

#define	UDCCSR_MASK (UDCCSR_FST \| UDCCSR_DME)

#define	UDCCISR0_EP_MASK ~0

#define	UDCCISR1_EP_MASK 0xffff

#define	UDCCSR0_CTRL_REQ_MASK (UDCCSR0_OPC \| UDCCSR0_SA \| UDCCSR0_RNE)

#define	EPIDX(ep) (ep->idx)

#define	EPADDR(ep) (ep->addr)

#define	EPXFERTYPE(ep) (ep->type)

#define	EPNAME(ep) (ep->name)

#define	is_ep0(ep) (!ep->idx)

#define	EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC)

#define	USB_EP_DEF(addr, bname, dir, type, maxpkt)

#define	USB_EP_BULK(addr, bname, dir) USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE)

#define	USB_EP_ISO(addr, bname, dir) USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE)

#define	USB_EP_INT(addr, bname, dir) USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE)

#define	USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1)

#define	USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0)

#define	USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1)

#define	USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0)

#define	USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1)

#define	USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, 0, EP0_FIFO_SIZE)

#define	PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset)

#define	PXA_EP_BULK(_idx, addr, dir, config, iface, alt)

#define	PXA_EP_ISO(_idx, addr, dir, config, iface, alt)

#define	PXA_EP_INT(_idx, addr, dir, config, iface, alt)

#define	PXA_EP_IN_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 1, c, f, a)

#define	PXA_EP_OUT_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 0, c, f, a)

#define	PXA_EP_IN_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 1, c, f, a)

#define	PXA_EP_OUT_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 0, c, f, a)

#define	PXA_EP_IN_INT(i, adr, c, f, a) PXA_EP_INT(i, adr, 1, c, f, a)

#define	PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0)

: endpoint name (for trace/debug purpose)
struct pxa_ep - pxa endpoint : udc device : requests queue : lock to pxa_ep data (queues and stats) : true when endpoint enabled (not stopped by gadget layer) : number of recursions of handle_ep() function Prevents deadlocks or infinite recursions of types : irq->handle_ep()->req_done()->req.complete()->pxa_ep_queue()->handle_ep() or pxa_ep_queue()->handle_ep()->req_done()->req.complete()->pxa_ep_queue() : endpoint index (1 => epA, 2 => epB, ..., 24 => epX) : 1 if IN endpoint, 0 if OUT endpoint : usb endpoint number : configuration in which this endpoint is active
#define	EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]

#define	EP0_FIFO_SIZE 16U

#define	BULK_FIFO_SIZE 64U

#define	ISO_FIFO_SIZE 256U

#define	INT_FIFO_SIZE 16U

#define	NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */

#define	NR_PXA_ENDPOINTS (1 + 14) /* ep0 + epA + epB + .. + epX */

#define	ep_dbg(ep, fmt, arg...) dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)

#define	ep_vdbg(ep, fmt, arg...) dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)

#define	ep_err(ep, fmt, arg...) dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)

#define	ep_info(ep, fmt, arg...) dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)

#define	ep_warn(ep, fmt, arg...) dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)

enum	ep0_state { EP0_IDLE, EP0_IN_DATA_PHASE, EP0_OUT_DATA_PHASE, EP0_CONFIG, EP0_STALL, STATE_DEV_DISABLED = 0, STATE_DEV_OPENED, STATE_DEV_UNCONNECTED, STATE_DEV_CONNECTED, STATE_DEV_SETUP, STATE_DEV_UNBOUND, EP0_IDLE, EP0_IN_DATA_PHASE, EP0_OUT_DATA_PHASE, EP0_END_XFER, EP0_STALL, WAIT_FOR_SETUP, SETUP_STAGE, IN_DATA_STAGE, OUT_DATA_STAGE, IN_STATUS_STAGE, OUT_STATUS_STAGE, STALL, WAIT_ACK_SET_CONF_INTERF, EP0_IDLE, EP0_IN_DATA_PHASE, EP0_OUT_DATA_PHASE, EP0_END_XFER, EP0_STALL }

Macro Definition Documentation

#define BULK_FIFO_SIZE 64U

Definition at line 383 of file pxa27x_udc.h.

#define EP0_FIFO_SIZE 16U

Definition at line 382 of file pxa27x_udc.h.

#define EP0_STNAME ( udc ) ep0_state_name[(udc)->ep0state]

Definition at line 380 of file pxa27x_udc.h.

#define ep_dbg	(	ep,
		fmt,
		arg...
	)	dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)

Definition at line 467 of file pxa27x_udc.h.

#define ep_err	(	ep,
		fmt,
		arg...
	)	dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)

Definition at line 471 of file pxa27x_udc.h.

#define ep_info	(	ep,
		fmt,
		arg...
	)	dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)

Definition at line 473 of file pxa27x_udc.h.

#define ep_vdbg	(	ep,
		fmt,
		arg...
	)	dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)

Definition at line 469 of file pxa27x_udc.h.

#define ep_warn	(	ep,
		fmt,
		arg...
	)	dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)

Definition at line 475 of file pxa27x_udc.h.

#define EPADDR ( ep ) (ep->addr)

Definition at line 185 of file pxa27x_udc.h.

#define EPIDX ( ep ) (ep->idx)

Definition at line 184 of file pxa27x_udc.h.

#define EPNAME ( ep ) (ep->name)

Definition at line 187 of file pxa27x_udc.h.

#define EPXFERTYPE ( ep ) (ep->type)

Definition at line 186 of file pxa27x_udc.h.

#define EPXFERTYPE_is_ISO ( ep ) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC)

Definition at line 189 of file pxa27x_udc.h.

#define INT_FIFO_SIZE 16U

Definition at line 385 of file pxa27x_udc.h.

#define is_ep0 ( ep ) (!ep->idx)

Definition at line 188 of file pxa27x_udc.h.

#define ISO_FIFO_SIZE 256U

Definition at line 384 of file pxa27x_udc.h.

#define NR_PXA_ENDPOINTS (1 + 14) /* ep0 + epA + epB + .. + epX */

Definition at line 395 of file pxa27x_udc.h.

#define NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */

Definition at line 394 of file pxa27x_udc.h.

#define ofs_UDCBCR ( ep ) (UDCBCRn(ep->idx))

Definition at line 162 of file pxa27x_udc.h.

#define ofs_UDCCR ( ep ) (UDCCRn(ep->idx))

Definition at line 160 of file pxa27x_udc.h.

#define ofs_UDCCSR ( ep ) (UDCCSRn(ep->idx))

Definition at line 161 of file pxa27x_udc.h.

#define ofs_UDCDR ( ep ) (UDCDRn(ep->idx))

Definition at line 163 of file pxa27x_udc.h.

#define PXA_EP_BULK	(	_idx,
		addr,
		dir,
		config,
		iface,
		alt
	)

Value:

PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \

config, iface, alt)

Definition at line 248 of file pxa27x_udc.h.

#define PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0)

Definition at line 262 of file pxa27x_udc.h.

#define PXA_EP_DEF	(	_idx,
		_addr,
		dir,
		_type,
		maxpkt,
		_config,
		iface,
		altset
	)

Value:

{ \
    .dev = &memory, \
    .name = "ep" #_idx, \
    .idx = _idx, .enabled = 0, \
    .dir_in = dir, .addr = _addr, \
    .config = _config, .interface = iface, .alternate = altset, \
    .type = _type, .fifo_size = maxpkt, \
}

Definition at line 239 of file pxa27x_udc.h.

#define PXA_EP_IN_BULK	(	i,
		adr,
		c,
		f,
		a
	)	PXA_EP_BULK(i, adr, 1, c, f, a)

Definition at line 257 of file pxa27x_udc.h.

#define PXA_EP_IN_INT	(	i,
		adr,
		c,
		f,
		a
	)	PXA_EP_INT(i, adr, 1, c, f, a)

Definition at line 261 of file pxa27x_udc.h.

#define PXA_EP_IN_ISO	(	i,
		adr,
		c,
		f,
		a
	)	PXA_EP_ISO(i, adr, 1, c, f, a)

Definition at line 259 of file pxa27x_udc.h.

#define PXA_EP_INT	(	_idx,
		addr,
		dir,
		config,
		iface,
		alt
	)

Value:

PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \

config, iface, alt)

Definition at line 254 of file pxa27x_udc.h.

#define PXA_EP_ISO	(	_idx,
		addr,
		dir,
		config,
		iface,
		alt
	)

Value:

PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \

config, iface, alt)

Definition at line 251 of file pxa27x_udc.h.

#define PXA_EP_OUT_BULK	(	i,
		adr,
		c,
		f,
		a
	)	PXA_EP_BULK(i, adr, 0, c, f, a)

Definition at line 258 of file pxa27x_udc.h.

#define PXA_EP_OUT_ISO	(	i,
		adr,
		c,
		f,
		a
	)	PXA_EP_ISO(i, adr, 0, c, f, a)

Definition at line 260 of file pxa27x_udc.h.

#define UDC_BCR_MASK (0x3ff)

Definition at line 152 of file pxa27x_udc.h.

#define udc_ep_readb	(	ep,
		reg
	)	__raw_readb((ep)->dev->regs + ofs_##reg(ep))

Definition at line 170 of file pxa27x_udc.h.

#define udc_ep_readl	(	ep,
		reg
	)	__raw_readl((ep)->dev->regs + ofs_##reg(ep))

Definition at line 166 of file pxa27x_udc.h.

#define udc_ep_writeb	(	ep,
		reg,
		value
	)	__raw_writeb((value), ep->dev->regs + ofs_##reg(ep))

Definition at line 172 of file pxa27x_udc.h.

#define udc_ep_writel	(	ep,
		reg,
		value
	)	__raw_writel((value), ep->dev->regs + ofs_##reg(ep))

Definition at line 168 of file pxa27x_udc.h.

#define UDC_FNR_MASK (0x7ff)

Definition at line 151 of file pxa27x_udc.h.

#define udc_readl	(	dev,
		reg
	)	__raw_readl((dev)->regs + (reg))

Definition at line 174 of file pxa27x_udc.h.

#define udc_writel	(	udc,
		reg,
		value
	)	__raw_writel((value), (udc)->regs + (reg))

Definition at line 176 of file pxa27x_udc.h.

#define UDCBCRn ( x ) (0x0200 + ((x)<<2)) /* UDC Byte Count Register */

Definition at line 36 of file pxa27x_udc.h.

#define UDCCISR0_EP_MASK ~0

Definition at line 180 of file pxa27x_udc.h.

#define UDCCISR1_EP_MASK 0xffff

Definition at line 181 of file pxa27x_udc.h.

#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */

Definition at line 133 of file pxa27x_udc.h.

#define UDCCONR_AISN_S 19

Definition at line 134 of file pxa27x_udc.h.

#define UDCCONR_CN (0x03 << 25) /* Configuration Number */

Definition at line 129 of file pxa27x_udc.h.

#define UDCCONR_CN_S 25

Definition at line 130 of file pxa27x_udc.h.

#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */

Definition at line 146 of file pxa27x_udc.h.

#define UDCCONR_ED (1 << 12) /* Endpoint Direction */

Definition at line 143 of file pxa27x_udc.h.

#define UDCCONR_EE (1 << 0) /* Endpoint Enable */

Definition at line 147 of file pxa27x_udc.h.

#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */

Definition at line 135 of file pxa27x_udc.h.

#define UDCCONR_EN_S 15

Definition at line 136 of file pxa27x_udc.h.

#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */

Definition at line 137 of file pxa27x_udc.h.

#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */

Definition at line 140 of file pxa27x_udc.h.

#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */

Definition at line 139 of file pxa27x_udc.h.

#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */

Definition at line 141 of file pxa27x_udc.h.

#define UDCCONR_ET_NU (0x00 << 13) /* Not used */

Definition at line 142 of file pxa27x_udc.h.

#define UDCCONR_ET_S 13

Definition at line 138 of file pxa27x_udc.h.

#define UDCCONR_IN (0x07 << 22) /* Interface Number */

Definition at line 131 of file pxa27x_udc.h.

#define UDCCONR_IN_S 22

Definition at line 132 of file pxa27x_udc.h.

#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */

Definition at line 144 of file pxa27x_udc.h.

#define UDCCONR_MPS_S 2

Definition at line 145 of file pxa27x_udc.h.

#define UDCCR 0x0000 /* UDC Control Register */

Definition at line 26 of file pxa27x_udc.h.

#define UDCCR_AAISN

Value:

(0x07 << 5) /* Active UDC Alternate Interface

Setting Number */

Definition at line 49 of file pxa27x_udc.h.

#define UDCCR_AAISN_S 5

Definition at line 50 of file pxa27x_udc.h.

#define UDCCR_AALTHNP

Value:

(1 << 30) /* A-device Alternate Host Negotiation

Protocol Port Support */

Definition at line 41 of file pxa27x_udc.h.

#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */

Definition at line 45 of file pxa27x_udc.h.

#define UDCCR_ACN_S 11

Definition at line 46 of file pxa27x_udc.h.

#define UDCCR_AHNP

Value:

(1 << 29) /* A-device Host Negotiation Protocol

Support */

Definition at line 42 of file pxa27x_udc.h.

#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */

Definition at line 47 of file pxa27x_udc.h.

#define UDCCR_AIN_S 8

Definition at line 48 of file pxa27x_udc.h.

#define UDCCR_BHNP

Value:

(1 << 28) /* B-device Host Negotiation Protocol

Enable */

Definition at line 43 of file pxa27x_udc.h.

#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */

Definition at line 44 of file pxa27x_udc.h.

#define UDCCR_EMCE

Value:

(1 << 3) /* Endpoint Memory Configuration

Error */

Definition at line 52 of file pxa27x_udc.h.

#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE)

Definition at line 149 of file pxa27x_udc.h.

#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */

Definition at line 40 of file pxa27x_udc.h.

#define UDCCR_SMAC

Value:

(1 << 4) /* Switch Endpoint Memory to Active

Configuration */

Definition at line 51 of file pxa27x_udc.h.

#define UDCCR_UDA (1 << 1) /* UDC Active */

Definition at line 54 of file pxa27x_udc.h.

#define UDCCR_UDE (1 << 0) /* UDC Enable */

Definition at line 55 of file pxa27x_udc.h.

#define UDCCR_UDR (1 << 2) /* UDC Resume */

Definition at line 53 of file pxa27x_udc.h.

#define UDCCRn ( x ) (0x0400 + ((x)<<2)) /* UDC Control Register */

Definition at line 38 of file pxa27x_udc.h.

#define UDCCSR0_ACM (1 << 9) /* Ack Control Mode */

Definition at line 106 of file pxa27x_udc.h.

#define UDCCSR0_AREN (1 << 8) /* Ack Response Enable */

Definition at line 107 of file pxa27x_udc.h.

#define UDCCSR0_CTRL_REQ_MASK (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)

Definition at line 182 of file pxa27x_udc.h.

#define UDCCSR0_DME (1 << 3) /* DMA Enable */

Definition at line 112 of file pxa27x_udc.h.

#define UDCCSR0_FST (1 << 5) /* Force Stall */

Definition at line 110 of file pxa27x_udc.h.

#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */

Definition at line 113 of file pxa27x_udc.h.

#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */

Definition at line 114 of file pxa27x_udc.h.

#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */

Definition at line 115 of file pxa27x_udc.h.

#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */

Definition at line 109 of file pxa27x_udc.h.

#define UDCCSR0_SA (1 << 7) /* Setup Active */

Definition at line 108 of file pxa27x_udc.h.

#define UDCCSR0_SST (1 << 4) /* Sent Stall */

Definition at line 111 of file pxa27x_udc.h.

#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */

Definition at line 120 of file pxa27x_udc.h.

#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */

Definition at line 121 of file pxa27x_udc.h.

#define UDCCSR_DME (1 << 3) /* DMA Enable */

Definition at line 124 of file pxa27x_udc.h.

#define UDCCSR_DPE (1 << 9) /* Data Packet Error */

Definition at line 117 of file pxa27x_udc.h.

#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */

Definition at line 118 of file pxa27x_udc.h.

#define UDCCSR_FS (1 << 0) /* FIFO needs service */

Definition at line 127 of file pxa27x_udc.h.

#define UDCCSR_FST (1 << 5) /* Force STALL */

Definition at line 122 of file pxa27x_udc.h.

#define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME)

Definition at line 179 of file pxa27x_udc.h.

#define UDCCSR_PC (1 << 1) /* Packet Complete */

Definition at line 126 of file pxa27x_udc.h.

#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */

Definition at line 119 of file pxa27x_udc.h.

#define UDCCSR_SST (1 << 4) /* Sent STALL */

Definition at line 123 of file pxa27x_udc.h.

#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */

Definition at line 125 of file pxa27x_udc.h.

#define UDCCSR_WR_MASK (UDCCSR_DME | UDCCSR_FST)

Definition at line 150 of file pxa27x_udc.h.

#define UDCCSRn ( x ) (0x0100 + ((x)<<2)) /* UDC Control/Status register */

Definition at line 35 of file pxa27x_udc.h.

#define UDCDRn ( x ) (0x0300 + ((x)<<2)) /* UDC Data Register */

Definition at line 37 of file pxa27x_udc.h.

#define UDCFNR 0x0014 /* UDC Frame Number Register */

Definition at line 31 of file pxa27x_udc.h.

#define UDCICR0 0x0004 /* UDC Interrupt Control Register0 */

Definition at line 27 of file pxa27x_udc.h.

#define UDCICR1 0x0008 /* UDC Interrupt Control Register1 */

Definition at line 28 of file pxa27x_udc.h.

#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */

Definition at line 58 of file pxa27x_udc.h.

#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */

Definition at line 62 of file pxa27x_udc.h.

#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */

Definition at line 60 of file pxa27x_udc.h.

#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */

Definition at line 59 of file pxa27x_udc.h.

#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */

Definition at line 61 of file pxa27x_udc.h.

#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */

Definition at line 63 of file pxa27x_udc.h.

#define UDCICR_INT	(	n,
		intr
	)	(((intr) & 0x03) << (((n) & 0x0F) * 2))

Definition at line 57 of file pxa27x_udc.h.

#define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)

Definition at line 65 of file pxa27x_udc.h.

#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */

Definition at line 64 of file pxa27x_udc.h.

#define UDCISR0 0x000C /* UDC Interrupt Status Register 0 */

Definition at line 29 of file pxa27x_udc.h.

#define UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */

Definition at line 30 of file pxa27x_udc.h.

#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */

Definition at line 68 of file pxa27x_udc.h.

#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */

Definition at line 72 of file pxa27x_udc.h.

#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */

Definition at line 70 of file pxa27x_udc.h.

#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */

Definition at line 69 of file pxa27x_udc.h.

#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */

Definition at line 71 of file pxa27x_udc.h.

#define UDCISR_INT	(	n,
		intr
	)	(((intr) & 0x03) << (((n) & 0x0F) * 2))

Definition at line 67 of file pxa27x_udc.h.

#define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)

Definition at line 73 of file pxa27x_udc.h.

#define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */

Definition at line 32 of file pxa27x_udc.h.

#define UDCOTGICR_IEIDF

Value:

(1 << 0) /* OTG ID Change Falling Edge

Interrupt Enable */

Definition at line 87 of file pxa27x_udc.h.

#define UDCOTGICR_IEIDR

Value:

(1 << 1) /* OTG ID Change Rising Edge

Interrupt Enable */

Definition at line 86 of file pxa27x_udc.h.

#define UDCOTGICR_IESDF

Value:

(1 << 2) /* OTG A-Device SRP Detect Falling

Edge Interrupt Enable */

Definition at line 85 of file pxa27x_udc.h.

#define UDCOTGICR_IESDR

Value:

(1 << 3) /* OTG A-Device SRP Detect Rising

Edge Interrupt Enable */

Definition at line 84 of file pxa27x_udc.h.

#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */

Definition at line 75 of file pxa27x_udc.h.

#define UDCOTGICR_IESVF

Value:

(1 << 4) /* OTG Session Valid Falling Edge

Interrupt Enable */

Definition at line 83 of file pxa27x_udc.h.

#define UDCOTGICR_IESVR

Value:

(1 << 5) /* OTG Session Valid Rising Edge

Interrupt Enable */

Definition at line 82 of file pxa27x_udc.h.

#define UDCOTGICR_IEVV40F

Value:

(1 << 8) /* OTG Vbus Valid 4.0V Falling Edge

Interrupt Enable */

Definition at line 79 of file pxa27x_udc.h.

#define UDCOTGICR_IEVV40R

Value:

(1 << 9) /* OTG Vbus Valid 4.0V Rising Edge

Interrupt Enable */

Definition at line 78 of file pxa27x_udc.h.

#define UDCOTGICR_IEVV44F

Value:

(1 << 6) /* OTG Vbus Valid 4.4V Falling Edge

Interrupt Enable */

Definition at line 81 of file pxa27x_udc.h.

#define UDCOTGICR_IEVV44R

Value:

(1 << 7) /* OTG Vbus Valid 4.4V Rising Edge

Interrupt Enable */

Definition at line 80 of file pxa27x_udc.h.

#define UDCOTGICR_IEXF

Value:

(1 << 16) /* Extra Transceiver Interrupt

Falling Edge Interrupt Enable */

Definition at line 77 of file pxa27x_udc.h.

#define UDCOTGICR_IEXR

Value:

(1 << 17) /* Extra Transceiver Interrupt

Rising Edge Interrupt Enable */

Definition at line 76 of file pxa27x_udc.h.

#define UP2OCR 0x0020 /* USB Port 2 Output Control register */

Definition at line 33 of file pxa27x_udc.h.

#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */

Definition at line 90 of file pxa27x_udc.h.

#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */

Definition at line 91 of file pxa27x_udc.h.

#define UP2OCR_DMPDE (1 << 3) /* D- Pull Down Enable */

Definition at line 94 of file pxa27x_udc.h.

#define UP2OCR_DMPUBE (1 << 7) /* D- Pull Up Bypass Enable */

Definition at line 98 of file pxa27x_udc.h.

#define UP2OCR_DMPUE (1 << 5) /* D- Pull Up Enable */

Definition at line 96 of file pxa27x_udc.h.

#define UP2OCR_DPPDE (1 << 2) /* D+ Pull Down Enable */

Definition at line 93 of file pxa27x_udc.h.

#define UP2OCR_DPPUBE (1 << 6) /* D+ Pull Up Bypass Enable */

Definition at line 97 of file pxa27x_udc.h.

#define UP2OCR_DPPUE (1 << 4) /* D+ Pull Up Enable */

Definition at line 95 of file pxa27x_udc.h.

#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */

Definition at line 99 of file pxa27x_udc.h.

#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */

Definition at line 100 of file pxa27x_udc.h.

#define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */

Definition at line 103 of file pxa27x_udc.h.

#define UP2OCR_HXS (1 << 16) /* Transceiver Output Select */

Definition at line 102 of file pxa27x_udc.h.

#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */

Definition at line 101 of file pxa27x_udc.h.

#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */

Definition at line 104 of file pxa27x_udc.h.

#define UP3OCR 0x0024 /* USB Port 3 Output Control register */

Definition at line 34 of file pxa27x_udc.h.

#define USB_EP_BULK	(	addr,
		bname,
		dir
	)	USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE)

Definition at line 226 of file pxa27x_udc.h.

#define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, 0, EP0_FIFO_SIZE)

Definition at line 237 of file pxa27x_udc.h.

#define USB_EP_DEF	(	addr,
		bname,
		dir,
		type,
		maxpkt
	)

Value:

{ .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, }, \
  .desc = { .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \
        .bmAttributes = type, \
        .wMaxPacketSize = maxpkt, }, \
  .dev = &memory \
}

Definition at line 219 of file pxa27x_udc.h.

#define USB_EP_IN_BULK ( n ) USB_EP_BULK(n, "ep" #n "in-bulk", 1)

Definition at line 232 of file pxa27x_udc.h.

#define USB_EP_IN_INT ( n ) USB_EP_INT(n, "ep" #n "in-int", 1)

Definition at line 236 of file pxa27x_udc.h.

#define USB_EP_IN_ISO ( n ) USB_EP_ISO(n, "ep" #n "in-iso", 1)

Definition at line 234 of file pxa27x_udc.h.

#define USB_EP_INT	(	addr,
		bname,
		dir
	)	USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE)

Definition at line 230 of file pxa27x_udc.h.

#define USB_EP_ISO	(	addr,
		bname,
		dir
	)	USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE)

Definition at line 228 of file pxa27x_udc.h.

#define USB_EP_OUT_BULK ( n ) USB_EP_BULK(n, "ep" #n "out-bulk", 0)

Definition at line 233 of file pxa27x_udc.h.

#define USB_EP_OUT_ISO ( n ) USB_EP_ISO(n, "ep" #n "out-iso", 0)

Definition at line 235 of file pxa27x_udc.h.

Enumeration Type Documentation

enum ep0_state

Enumerator:

EP0_IDLE
EP0_IN_DATA_PHASE
EP0_OUT_DATA_PHASE
EP0_CONFIG
EP0_STALL
STATE_DEV_DISABLED
STATE_DEV_OPENED
STATE_DEV_UNCONNECTED
STATE_DEV_CONNECTED
STATE_DEV_SETUP
STATE_DEV_UNBOUND
EP0_IDLE
EP0_IN_DATA_PHASE
EP0_OUT_DATA_PHASE
EP0_END_XFER
EP0_STALL
WAIT_FOR_SETUP
SETUP_STAGE
IN_DATA_STAGE
OUT_DATA_STAGE
IN_STATUS_STAGE
OUT_STATUS_STAGE
STALL
WAIT_ACK_SET_CONF_INTERF
EP0_IDLE
EP0_IN_DATA_PHASE
EP0_OUT_DATA_PHASE
EP0_END_XFER
EP0_STALL

Definition at line 364 of file pxa27x_udc.h.

Data Structures

Macros

: endpoint name (for trace/debug purpose)

Macro Definition Documentation

Enumeration Type Documentation