15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
19 #include <linux/tty.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
25 #include <linux/slab.h>
27 #include <linux/serial.h>
40 #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44 #include <linux/serial_core.h>
52 #define ZSDELAY() udelay(5)
53 #define ZSDELAY_LONG() udelay(20)
54 #define ZS_WSYNC(channel) do { } while (0)
56 #define NUM_IP22ZILOG 1
57 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
59 #define ZS_CLOCK 3672000
60 #define ZS_CLOCK_DIVISOR 16
75 #define IP22ZILOG_FLAG_IS_CONS 0x00000004
76 #define IP22ZILOG_FLAG_IS_KGDB 0x00000008
77 #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010
78 #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020
79 #define IP22ZILOG_FLAG_REGS_HELD 0x00000040
80 #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080
81 #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100
82 #define IP22ZILOG_FLAG_RESET_DONE 0x00000200
90 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
91 #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
92 #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
93 (UART_ZILOG(PORT)->curregs[REGNUM])
94 #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
95 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
96 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
97 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
98 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
99 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
100 #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
101 #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
102 #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
126 unsigned char reg,
unsigned char value)
138 for (i = 0; i < 32; i++) {
146 regval = read_zsreg(channel,
R1);
166 for (i = 0; i < 1000; i++) {
167 unsigned char stat = read_zsreg(channel,
R1);
177 ip22zilog_clear_fifo(channel);
180 write_zsreg(channel,
R1,
184 write_zsreg(channel,
R4, regs[
R4]);
187 write_zsreg(channel,
R10, regs[
R10]);
194 write_zsreg(channel,
R6, regs[
R6]);
195 write_zsreg(channel,
R7, regs[
R7]);
206 write_zsreg(channel,
R11, regs[
R11]);
209 write_zsreg(channel,
R12, regs[
R12]);
210 write_zsreg(channel,
R13, regs[
R13]);
213 write_zsreg(channel,
R14, regs[
R14]);
216 write_zsreg(channel,
R15, regs[
R15]);
223 write_zsreg(channel,
R3, regs[
R3]);
224 write_zsreg(channel,
R5, regs[
R5]);
227 write_zsreg(channel,
R1, regs[
R1]);
243 __load_zsregs(channel, up->
curregs);
248 #define Rx_BRK 0x0100
249 #define Rx_SYS 0x0200
255 unsigned char ch,
flag;
261 tty = up->
port.state->port.tty;
266 if (!(ch & Rx_CH_AV))
269 r1 = read_zsreg(channel,
R1);
287 up->
port.icount.rx++;
292 up->
port.icount.brk++;
298 up->
port.icount.parity++;
300 up->
port.icount.frame++;
302 up->
port.icount.overrun++;
303 r1 &= up->
port.read_status_mask;
306 else if (r1 & PAR_ERR)
308 else if (r1 & CRC_ERR)
335 if (uart_handle_break(&up->
port))
344 up->
port.icount.dsr++;
387 __load_zsregs(channel, up->
curregs);
396 if (up->
port.x_char) {
402 up->
port.icount.tx++;
409 xmit = &up->
port.state->xmit;
412 if (uart_tx_stopped(&up->
port))
421 up->
port.icount.tx++;
444 spin_lock(&up->
port.lock);
445 r3 = read_zsreg(channel,
R3);
455 tty = ip22zilog_receive_chars(up, channel);
457 ip22zilog_status_handle(up, channel);
459 ip22zilog_transmit_chars(up, channel);
461 spin_unlock(&up->
port.lock);
470 spin_lock(&up->
port.lock);
478 tty = ip22zilog_receive_chars(up, channel);
480 ip22zilog_status_handle(up, channel);
482 ip22zilog_transmit_chars(up, channel);
484 spin_unlock(&up->
port.lock);
511 static unsigned int ip22zilog_tx_empty(
struct uart_port *
port)
519 status = ip22zilog_read_channel_status(port);
521 spin_unlock_irqrestore(&port->
lock, flags);
532 static unsigned int ip22zilog_get_mctrl(
struct uart_port *port)
537 status = ip22zilog_read_channel_status(port);
551 static void ip22zilog_set_mctrl(
struct uart_port *port,
unsigned int mctrl)
557 set_bits = clear_bits = 0;
575 static void ip22zilog_stop_tx(
struct uart_port *port)
583 static void ip22zilog_start_tx(
struct uart_port *port)
625 static void ip22zilog_stop_rx(
struct uart_port *port)
637 ip22zilog_maybe_update_regs(up, channel);
641 static void ip22zilog_enable_ms(
struct uart_port *port)
645 unsigned char new_reg;
657 static void ip22zilog_break_ctl(
struct uart_port *port,
int break_state)
661 unsigned char set_bits, clear_bits, new_reg;
664 set_bits = clear_bits = 0;
681 spin_unlock_irqrestore(&port->
lock, flags);
694 for (i = 0; i < 1000; i++) {
695 unsigned char stat = read_zsreg(channel,
R1);
707 (
void) read_zsreg(channel,
R0);
719 __ip22zilog_reset(up);
721 __load_zsregs(channel, up->
curregs);
731 ip22zilog_maybe_update_regs(up, channel);
734 static int ip22zilog_startup(
struct uart_port *port)
743 __ip22zilog_startup(up);
744 spin_unlock_irqrestore(&port->
lock, flags);
773 static void ip22zilog_shutdown(
struct uart_port *port)
793 ip22zilog_maybe_update_regs(up, channel);
795 spin_unlock_irqrestore(&port->
lock, flags);
803 unsigned int iflag,
int brg)
819 switch (cflag &
CSIZE) {
860 up->
port.read_status_mask |= BRK_ABRT;
862 up->
port.ignore_status_mask = 0;
871 if ((cflag &
CREAD) == 0)
872 up->
port.ignore_status_mask = 0xff;
890 ip22zilog_convert_to_zs(up, termios->
c_cflag, termios->
c_iflag, brg);
900 spin_unlock_irqrestore(&up->
port.lock, flags);
903 static const char *ip22zilog_type(
struct uart_port *port)
911 static void ip22zilog_release_port(
struct uart_port *port)
915 static int ip22zilog_request_port(
struct uart_port *port)
921 static void ip22zilog_config_port(
struct uart_port *port,
int flags)
931 static struct uart_ops ip22zilog_pops = {
932 .tx_empty = ip22zilog_tx_empty,
933 .set_mctrl = ip22zilog_set_mctrl,
934 .get_mctrl = ip22zilog_get_mctrl,
935 .stop_tx = ip22zilog_stop_tx,
936 .start_tx = ip22zilog_start_tx,
937 .stop_rx = ip22zilog_stop_rx,
938 .enable_ms = ip22zilog_enable_ms,
939 .break_ctl = ip22zilog_break_ctl,
940 .startup = ip22zilog_startup,
941 .shutdown = ip22zilog_shutdown,
942 .set_termios = ip22zilog_set_termios,
943 .type = ip22zilog_type,
944 .release_port = ip22zilog_release_port,
945 .request_port = ip22zilog_request_port,
946 .config_port = ip22zilog_config_port,
947 .verify_port = ip22zilog_verify_port,
954 static int zilog_irq = -1;
956 static void *
__init alloc_one_table(
unsigned long size)
961 static void __init ip22zilog_alloc_tables(
void)
968 if (ip22zilog_port_table ==
NULL || ip22zilog_chip_regs ==
NULL) {
969 panic(
"IP22-Zilog: Cannot allocate IP22-Zilog tables.");
979 panic(
"IP22-Zilog: Illegal chip number %d in get_zs.", chip);
991 #define ZS_PUT_CHAR_MAX_DELAY 2000
993 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
994 static void ip22zilog_put_char(
struct uart_port *port,
int ch)
1004 if (val & Tx_BUF_EMP) {
1017 ip22zilog_console_write(
struct console *
con,
const char *
s,
unsigned int count)
1020 unsigned long flags;
1025 spin_unlock_irqrestore(&up->
port.lock, flags);
1031 unsigned long flags;
1032 int baud = 9600,
bits = 8;
1044 __ip22zilog_startup(up);
1046 spin_unlock_irqrestore(&up->
port.lock, flags);
1055 static struct console ip22zilog_console = {
1057 .write = ip22zilog_console_write,
1059 .setup = ip22zilog_console_setup,
1062 .data = &ip22zilog_reg,
1068 .driver_name =
"serial",
1073 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1074 .cons = &ip22zilog_console,
1078 static void __init ip22zilog_prepare(
void)
1090 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];
1091 up = &ip22zilog_port_table[0];
1092 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1093 up[channel].
next = &up[channel - 1];
1097 if (!ip22zilog_chip_regs[chip]) {
1098 ip22zilog_chip_regs[
chip] = rp = get_zs(chip);
1104 up[(chip * 2) + 0].port.
mapbase =
1106 up[(chip * 2) + 1].port.
mapbase =
1112 up[(chip * 2) + 0].
port.irq = zilog_irq;
1114 up[(chip * 2) + 0].
port.fifosize = 1;
1115 up[(chip * 2) + 0].port.
ops = &ip22zilog_pops;
1117 up[(chip * 2) + 0].port.
flags = 0;
1118 up[(chip * 2) + 0].
port.line = (chip * 2) + 0;
1119 up[(chip * 2) + 0].flags = 0;
1123 up[(chip * 2) + 1].
port.irq = zilog_irq;
1125 up[(chip * 2) + 1].
port.fifosize = 1;
1126 up[(chip * 2) + 1].port.
ops = &ip22zilog_pops;
1128 up[(chip * 2) + 1].port.
line = (chip * 2) + 1;
1152 static int __init ip22zilog_ports_init(
void)
1156 printk(
KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1158 ip22zilog_prepare();
1160 if (
request_irq(zilog_irq, ip22zilog_interrupt, 0,
1161 "IP22-Zilog", ip22zilog_irq_chain)) {
1162 panic(
"IP22-Zilog: Unable to register zs interrupt handler.\n");
1179 static int __init ip22zilog_init(
void)
1182 ip22zilog_alloc_tables();
1183 ip22zilog_ports_init();
1188 static void __exit ip22zilog_exit(
void)
1194 up = &ip22zilog_port_table[
i];
1200 up = &ip22zilog_port_table[0];
1202 if (up[(i * 2) + 0].port.
mapbase) {
1204 up[(i * 2) + 0].port.
mapbase = 0;
1206 if (up[(i * 2) + 1].
port.mapbase) {
1208 up[(i * 2) + 1].port.
mapbase = 0;