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ixgbe_82599.c
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1 /*******************************************************************************
2 
3  Intel 10 Gigabit PCI Express Linux driver
4  Copyright(c) 1999 - 2012 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  e1000-devel Mailing List <[email protected]>
24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 
26 *******************************************************************************/
27 
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35 
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
42 
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47  ixgbe_link_speed speed,
48  bool autoneg,
49  bool autoneg_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51  ixgbe_link_speed speed,
52  bool autoneg,
53  bool autoneg_wait_to_complete);
54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55  bool autoneg_wait_to_complete);
56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
57  ixgbe_link_speed speed,
58  bool autoneg,
59  bool autoneg_wait_to_complete);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61  ixgbe_link_speed speed,
62  bool autoneg,
63  bool autoneg_wait_to_complete);
64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
66 
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
68 {
69  struct ixgbe_mac_info *mac = &hw->mac;
70 
71  /* enable the laser control functions for SFP+ fiber */
72  if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
73  mac->ops.disable_tx_laser =
74  &ixgbe_disable_tx_laser_multispeed_fiber;
75  mac->ops.enable_tx_laser =
76  &ixgbe_enable_tx_laser_multispeed_fiber;
77  mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
78  } else {
79  mac->ops.disable_tx_laser = NULL;
80  mac->ops.enable_tx_laser = NULL;
81  mac->ops.flap_tx_laser = NULL;
82  }
83 
84  if (hw->phy.multispeed_fiber) {
85  /* Set up dual speed SFP+ support */
86  mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
87  } else {
88  if ((mac->ops.get_media_type(hw) ==
89  ixgbe_media_type_backplane) &&
90  (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
91  hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92  !ixgbe_verify_lesm_fw_enabled_82599(hw))
93  mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
94  else
95  mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
96  }
97 }
98 
99 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
100 {
101  s32 ret_val = 0;
102  u32 reg_anlp1 = 0;
103  u32 i = 0;
104  u16 list_offset, data_offset, data_value;
105 
106  if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
107  ixgbe_init_mac_link_ops_82599(hw);
108 
109  hw->phy.ops.reset = NULL;
110 
111  ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
112  &data_offset);
113  if (ret_val != 0)
114  goto setup_sfp_out;
115 
116  /* PHY config will finish before releasing the semaphore */
117  ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118  IXGBE_GSSR_MAC_CSR_SM);
119  if (ret_val != 0) {
120  ret_val = IXGBE_ERR_SWFW_SYNC;
121  goto setup_sfp_out;
122  }
123 
124  hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125  while (data_value != 0xffff) {
126  IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
127  IXGBE_WRITE_FLUSH(hw);
128  hw->eeprom.ops.read(hw, ++data_offset, &data_value);
129  }
130 
131  /* Release the semaphore */
132  hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
133  /*
134  * Delay obtaining semaphore again to allow FW access,
135  * semaphore_delay is in ms usleep_range needs us.
136  */
137  usleep_range(hw->eeprom.semaphore_delay * 1000,
138  hw->eeprom.semaphore_delay * 2000);
139 
140  /* Now restart DSP by setting Restart_AN and clearing LMS */
141  IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
142  IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
143  IXGBE_AUTOC_AN_RESTART));
144 
145  /* Wait for AN to leave state 0 */
146  for (i = 0; i < 10; i++) {
147  usleep_range(4000, 8000);
148  reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
149  if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
150  break;
151  }
152  if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
153  hw_dbg(hw, "sfp module setup not complete\n");
154  ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
155  goto setup_sfp_out;
156  }
157 
158  /* Restart DSP by setting Restart_AN and return to SFI mode */
159  IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
160  IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
161  IXGBE_AUTOC_AN_RESTART));
162  }
163 
164 setup_sfp_out:
165  return ret_val;
166 }
167 
168 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
169 {
170  struct ixgbe_mac_info *mac = &hw->mac;
171 
172  ixgbe_init_mac_link_ops_82599(hw);
173 
174  mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
175  mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
176  mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
177  mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
178  mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
179  mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
180 
181  return 0;
182 }
183 
193 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
194 {
195  struct ixgbe_mac_info *mac = &hw->mac;
196  struct ixgbe_phy_info *phy = &hw->phy;
197  s32 ret_val = 0;
198 
199  /* Identify the PHY or SFP module */
200  ret_val = phy->ops.identify(hw);
201 
202  /* Setup function pointers based on detected SFP module and speeds */
203  ixgbe_init_mac_link_ops_82599(hw);
204 
205  /* If copper media, overwrite with copper function pointers */
206  if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
207  mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
208  mac->ops.get_link_capabilities =
209  &ixgbe_get_copper_link_capabilities_generic;
210  }
211 
212  /* Set necessary function pointers based on phy type */
213  switch (hw->phy.type) {
214  case ixgbe_phy_tn:
215  phy->ops.check_link = &ixgbe_check_phy_link_tnx;
216  phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
217  phy->ops.get_firmware_version =
218  &ixgbe_get_phy_firmware_version_tnx;
219  break;
220  default:
221  break;
222  }
223 
224  return ret_val;
225 }
226 
235 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
236  ixgbe_link_speed *speed,
237  bool *negotiation)
238 {
239  s32 status = 0;
240  u32 autoc = 0;
241 
242  /* Determine 1G link capabilities off of SFP+ type */
243  if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
244  hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
245  hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
246  hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
247  *speed = IXGBE_LINK_SPEED_1GB_FULL;
248  *negotiation = true;
249  goto out;
250  }
251 
252  /*
253  * Determine link capabilities based on the stored value of AUTOC,
254  * which represents EEPROM defaults. If AUTOC value has not been
255  * stored, use the current register value.
256  */
257  if (hw->mac.orig_link_settings_stored)
258  autoc = hw->mac.orig_autoc;
259  else
260  autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
261 
262  switch (autoc & IXGBE_AUTOC_LMS_MASK) {
263  case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
264  *speed = IXGBE_LINK_SPEED_1GB_FULL;
265  *negotiation = false;
266  break;
267 
268  case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
269  *speed = IXGBE_LINK_SPEED_10GB_FULL;
270  *negotiation = false;
271  break;
272 
273  case IXGBE_AUTOC_LMS_1G_AN:
274  *speed = IXGBE_LINK_SPEED_1GB_FULL;
275  *negotiation = true;
276  break;
277 
278  case IXGBE_AUTOC_LMS_10G_SERIAL:
279  *speed = IXGBE_LINK_SPEED_10GB_FULL;
280  *negotiation = false;
281  break;
282 
283  case IXGBE_AUTOC_LMS_KX4_KX_KR:
284  case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
285  *speed = IXGBE_LINK_SPEED_UNKNOWN;
286  if (autoc & IXGBE_AUTOC_KR_SUPP)
287  *speed |= IXGBE_LINK_SPEED_10GB_FULL;
288  if (autoc & IXGBE_AUTOC_KX4_SUPP)
289  *speed |= IXGBE_LINK_SPEED_10GB_FULL;
290  if (autoc & IXGBE_AUTOC_KX_SUPP)
291  *speed |= IXGBE_LINK_SPEED_1GB_FULL;
292  *negotiation = true;
293  break;
294 
295  case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
296  *speed = IXGBE_LINK_SPEED_100_FULL;
297  if (autoc & IXGBE_AUTOC_KR_SUPP)
298  *speed |= IXGBE_LINK_SPEED_10GB_FULL;
299  if (autoc & IXGBE_AUTOC_KX4_SUPP)
300  *speed |= IXGBE_LINK_SPEED_10GB_FULL;
301  if (autoc & IXGBE_AUTOC_KX_SUPP)
302  *speed |= IXGBE_LINK_SPEED_1GB_FULL;
303  *negotiation = true;
304  break;
305 
306  case IXGBE_AUTOC_LMS_SGMII_1G_100M:
307  *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
308  *negotiation = false;
309  break;
310 
311  default:
312  status = IXGBE_ERR_LINK_SETUP;
313  goto out;
314  break;
315  }
316 
317  if (hw->phy.multispeed_fiber) {
318  *speed |= IXGBE_LINK_SPEED_10GB_FULL |
319  IXGBE_LINK_SPEED_1GB_FULL;
320  *negotiation = true;
321  }
322 
323 out:
324  return status;
325 }
326 
333 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
334 {
335  enum ixgbe_media_type media_type;
336 
337  /* Detect if there is a copper PHY attached. */
338  switch (hw->phy.type) {
339  case ixgbe_phy_cu_unknown:
340  case ixgbe_phy_tn:
341  media_type = ixgbe_media_type_copper;
342  goto out;
343  default:
344  break;
345  }
346 
347  switch (hw->device_id) {
348  case IXGBE_DEV_ID_82599_KX4:
349  case IXGBE_DEV_ID_82599_KX4_MEZZ:
350  case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
351  case IXGBE_DEV_ID_82599_KR:
352  case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
353  case IXGBE_DEV_ID_82599_XAUI_LOM:
354  /* Default device ID is mezzanine card KX/KX4 */
355  media_type = ixgbe_media_type_backplane;
356  break;
357  case IXGBE_DEV_ID_82599_SFP:
358  case IXGBE_DEV_ID_82599_SFP_FCOE:
359  case IXGBE_DEV_ID_82599_SFP_EM:
360  case IXGBE_DEV_ID_82599_SFP_SF2:
361  case IXGBE_DEV_ID_82599_SFP_SF_QP:
362  case IXGBE_DEV_ID_82599EN_SFP:
363  media_type = ixgbe_media_type_fiber;
364  break;
365  case IXGBE_DEV_ID_82599_CX4:
366  media_type = ixgbe_media_type_cx4;
367  break;
368  case IXGBE_DEV_ID_82599_T3_LOM:
369  media_type = ixgbe_media_type_copper;
370  break;
371  case IXGBE_DEV_ID_82599_LS:
372  media_type = ixgbe_media_type_fiber_lco;
373  break;
374  default:
375  media_type = ixgbe_media_type_unknown;
376  break;
377  }
378 out:
379  return media_type;
380 }
381 
390 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
391  bool autoneg_wait_to_complete)
392 {
393  u32 autoc_reg;
394  u32 links_reg;
395  u32 i;
396  s32 status = 0;
397 
398  /* Restart link */
399  autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
400  autoc_reg |= IXGBE_AUTOC_AN_RESTART;
401  IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
402 
403  /* Only poll for autoneg to complete if specified to do so */
404  if (autoneg_wait_to_complete) {
405  if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
406  IXGBE_AUTOC_LMS_KX4_KX_KR ||
407  (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
408  IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
409  (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
410  IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
411  links_reg = 0; /* Just in case Autoneg time = 0 */
412  for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
413  links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
414  if (links_reg & IXGBE_LINKS_KX_AN_COMP)
415  break;
416  msleep(100);
417  }
418  if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
419  status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
420  hw_dbg(hw, "Autoneg did not complete.\n");
421  }
422  }
423  }
424 
425  /* Add delay to filter out noises during initial link setup */
426  msleep(50);
427 
428  return status;
429 }
430 
439 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
440 {
441  u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
442 
443  /* Disable tx laser; allow 100us to go dark per spec */
444  esdp_reg |= IXGBE_ESDP_SDP3;
445  IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
446  IXGBE_WRITE_FLUSH(hw);
447  udelay(100);
448 }
449 
458 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
459 {
460  u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
461 
462  /* Enable tx laser; allow 100ms to light up */
463  esdp_reg &= ~IXGBE_ESDP_SDP3;
464  IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
465  IXGBE_WRITE_FLUSH(hw);
466  msleep(100);
467 }
468 
481 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
482 {
483  if (hw->mac.autotry_restart) {
484  ixgbe_disable_tx_laser_multispeed_fiber(hw);
485  ixgbe_enable_tx_laser_multispeed_fiber(hw);
486  hw->mac.autotry_restart = false;
487  }
488 }
489 
499 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
500  ixgbe_link_speed speed,
501  bool autoneg,
502  bool autoneg_wait_to_complete)
503 {
504  s32 status = 0;
505  ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
506  ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
507  u32 speedcnt = 0;
508  u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
509  u32 i = 0;
510  bool link_up = false;
511  bool negotiation;
512 
513  /* Mask off requested but non-supported speeds */
514  status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
515  &negotiation);
516  if (status != 0)
517  return status;
518 
519  speed &= link_speed;
520 
521  /*
522  * Try each speed one by one, highest priority first. We do this in
523  * software because 10gb fiber doesn't support speed autonegotiation.
524  */
525  if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
526  speedcnt++;
527  highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
528 
529  /* If we already have link at this speed, just jump out */
530  status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
531  false);
532  if (status != 0)
533  return status;
534 
535  if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
536  goto out;
537 
538  /* Set the module link speed */
539  esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
540  IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
541  IXGBE_WRITE_FLUSH(hw);
542 
543  /* Allow module to change analog characteristics (1G->10G) */
544  msleep(40);
545 
546  status = ixgbe_setup_mac_link_82599(hw,
547  IXGBE_LINK_SPEED_10GB_FULL,
548  autoneg,
549  autoneg_wait_to_complete);
550  if (status != 0)
551  return status;
552 
553  /* Flap the tx laser if it has not already been done */
554  hw->mac.ops.flap_tx_laser(hw);
555 
556  /*
557  * Wait for the controller to acquire link. Per IEEE 802.3ap,
558  * Section 73.10.2, we may have to wait up to 500ms if KR is
559  * attempted. 82599 uses the same timing for 10g SFI.
560  */
561  for (i = 0; i < 5; i++) {
562  /* Wait for the link partner to also set speed */
563  msleep(100);
564 
565  /* If we have link, just jump out */
566  status = hw->mac.ops.check_link(hw, &link_speed,
567  &link_up, false);
568  if (status != 0)
569  return status;
570 
571  if (link_up)
572  goto out;
573  }
574  }
575 
576  if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
577  speedcnt++;
578  if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
579  highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
580 
581  /* If we already have link at this speed, just jump out */
582  status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
583  false);
584  if (status != 0)
585  return status;
586 
587  if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
588  goto out;
589 
590  /* Set the module link speed */
591  esdp_reg &= ~IXGBE_ESDP_SDP5;
592  esdp_reg |= IXGBE_ESDP_SDP5_DIR;
593  IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
594  IXGBE_WRITE_FLUSH(hw);
595 
596  /* Allow module to change analog characteristics (10G->1G) */
597  msleep(40);
598 
599  status = ixgbe_setup_mac_link_82599(hw,
600  IXGBE_LINK_SPEED_1GB_FULL,
601  autoneg,
602  autoneg_wait_to_complete);
603  if (status != 0)
604  return status;
605 
606  /* Flap the tx laser if it has not already been done */
607  hw->mac.ops.flap_tx_laser(hw);
608 
609  /* Wait for the link partner to also set speed */
610  msleep(100);
611 
612  /* If we have link, just jump out */
613  status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
614  false);
615  if (status != 0)
616  return status;
617 
618  if (link_up)
619  goto out;
620  }
621 
622  /*
623  * We didn't get link. Configure back to the highest speed we tried,
624  * (if there was more than one). We call ourselves back with just the
625  * single highest speed that the user requested.
626  */
627  if (speedcnt > 1)
628  status = ixgbe_setup_mac_link_multispeed_fiber(hw,
629  highest_link_speed,
630  autoneg,
631  autoneg_wait_to_complete);
632 
633 out:
634  /* Set autoneg_advertised value based on input link speed */
635  hw->phy.autoneg_advertised = 0;
636 
637  if (speed & IXGBE_LINK_SPEED_10GB_FULL)
638  hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
639 
640  if (speed & IXGBE_LINK_SPEED_1GB_FULL)
641  hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
642 
643  return status;
644 }
645 
655 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
656  ixgbe_link_speed speed, bool autoneg,
657  bool autoneg_wait_to_complete)
658 {
659  s32 status = 0;
660  ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
661  s32 i, j;
662  bool link_up = false;
663  u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
664 
665  /* Set autoneg_advertised value based on input link speed */
666  hw->phy.autoneg_advertised = 0;
667 
668  if (speed & IXGBE_LINK_SPEED_10GB_FULL)
669  hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
670 
671  if (speed & IXGBE_LINK_SPEED_1GB_FULL)
672  hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
673 
674  if (speed & IXGBE_LINK_SPEED_100_FULL)
675  hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
676 
677  /*
678  * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
679  * autoneg advertisement if link is unable to be established at the
680  * highest negotiated rate. This can sometimes happen due to integrity
681  * issues with the physical media connection.
682  */
683 
684  /* First, try to get link with full advertisement */
685  hw->phy.smart_speed_active = false;
686  for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
687  status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
688  autoneg_wait_to_complete);
689  if (status != 0)
690  goto out;
691 
692  /*
693  * Wait for the controller to acquire link. Per IEEE 802.3ap,
694  * Section 73.10.2, we may have to wait up to 500ms if KR is
695  * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
696  * Table 9 in the AN MAS.
697  */
698  for (i = 0; i < 5; i++) {
699  mdelay(100);
700 
701  /* If we have link, just jump out */
702  status = hw->mac.ops.check_link(hw, &link_speed,
703  &link_up, false);
704  if (status != 0)
705  goto out;
706 
707  if (link_up)
708  goto out;
709  }
710  }
711 
712  /*
713  * We didn't get link. If we advertised KR plus one of KX4/KX
714  * (or BX4/BX), then disable KR and try again.
715  */
716  if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
717  ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
718  goto out;
719 
720  /* Turn SmartSpeed on to disable KR support */
721  hw->phy.smart_speed_active = true;
722  status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
723  autoneg_wait_to_complete);
724  if (status != 0)
725  goto out;
726 
727  /*
728  * Wait for the controller to acquire link. 600ms will allow for
729  * the AN link_fail_inhibit_timer as well for multiple cycles of
730  * parallel detect, both 10g and 1g. This allows for the maximum
731  * connect attempts as defined in the AN MAS table 73-7.
732  */
733  for (i = 0; i < 6; i++) {
734  mdelay(100);
735 
736  /* If we have link, just jump out */
737  status = hw->mac.ops.check_link(hw, &link_speed,
738  &link_up, false);
739  if (status != 0)
740  goto out;
741 
742  if (link_up)
743  goto out;
744  }
745 
746  /* We didn't get link. Turn SmartSpeed back off. */
747  hw->phy.smart_speed_active = false;
748  status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
749  autoneg_wait_to_complete);
750 
751 out:
752  if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
753  hw_dbg(hw, "Smartspeed has downgraded the link speed from "
754  "the maximum advertised\n");
755  return status;
756 }
757 
767 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
768  ixgbe_link_speed speed, bool autoneg,
769  bool autoneg_wait_to_complete)
770 {
771  s32 status = 0;
772  u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
773  u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
774  u32 start_autoc = autoc;
775  u32 orig_autoc = 0;
776  u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
777  u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
778  u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
779  u32 links_reg;
780  u32 i;
781  ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
782 
783  /* Check to see if speed passed in is supported. */
784  status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
785  &autoneg);
786  if (status != 0)
787  goto out;
788 
789  speed &= link_capabilities;
790 
791  if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
792  status = IXGBE_ERR_LINK_SETUP;
793  goto out;
794  }
795 
796  /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
797  if (hw->mac.orig_link_settings_stored)
798  orig_autoc = hw->mac.orig_autoc;
799  else
800  orig_autoc = autoc;
801 
802  if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
803  link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
804  link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
805  /* Set KX4/KX/KR support according to speed requested */
806  autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
807  if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
808  if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
809  autoc |= IXGBE_AUTOC_KX4_SUPP;
810  if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
811  (hw->phy.smart_speed_active == false))
812  autoc |= IXGBE_AUTOC_KR_SUPP;
813  }
814  if (speed & IXGBE_LINK_SPEED_1GB_FULL)
815  autoc |= IXGBE_AUTOC_KX_SUPP;
816  } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
817  (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
818  link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
819  /* Switch from 1G SFI to 10G SFI if requested */
820  if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
821  (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
822  autoc &= ~IXGBE_AUTOC_LMS_MASK;
823  autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
824  }
825  } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
826  (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
827  /* Switch from 10G SFI to 1G SFI if requested */
828  if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
829  (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
830  autoc &= ~IXGBE_AUTOC_LMS_MASK;
831  if (autoneg)
832  autoc |= IXGBE_AUTOC_LMS_1G_AN;
833  else
834  autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
835  }
836  }
837 
838  if (autoc != start_autoc) {
839  /* Restart link */
840  autoc |= IXGBE_AUTOC_AN_RESTART;
841  IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
842 
843  /* Only poll for autoneg to complete if specified to do so */
844  if (autoneg_wait_to_complete) {
845  if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
846  link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
847  link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
848  links_reg = 0; /*Just in case Autoneg time=0*/
849  for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
850  links_reg =
851  IXGBE_READ_REG(hw, IXGBE_LINKS);
852  if (links_reg & IXGBE_LINKS_KX_AN_COMP)
853  break;
854  msleep(100);
855  }
856  if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
857  status =
858  IXGBE_ERR_AUTONEG_NOT_COMPLETE;
859  hw_dbg(hw, "Autoneg did not "
860  "complete.\n");
861  }
862  }
863  }
864 
865  /* Add delay to filter out noises during initial link setup */
866  msleep(50);
867  }
868 
869 out:
870  return status;
871 }
872 
882 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
883  ixgbe_link_speed speed,
884  bool autoneg,
885  bool autoneg_wait_to_complete)
886 {
887  s32 status;
888 
889  /* Setup the PHY according to input speed */
890  status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
891  autoneg_wait_to_complete);
892  /* Set up MAC */
893  ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
894 
895  return status;
896 }
897 
906 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
907 {
908  ixgbe_link_speed link_speed;
909  s32 status;
910  u32 ctrl, i, autoc, autoc2;
911  bool link_up = false;
912 
913  /* Call adapter stop to disable tx/rx and clear interrupts */
914  status = hw->mac.ops.stop_adapter(hw);
915  if (status != 0)
916  goto reset_hw_out;
917 
918  /* flush pending Tx transactions */
919  ixgbe_clear_tx_pending(hw);
920 
921  /* PHY ops must be identified and initialized prior to reset */
922 
923  /* Identify PHY and related function pointers */
924  status = hw->phy.ops.init(hw);
925 
926  if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
927  goto reset_hw_out;
928 
929  /* Setup SFP module if there is one present. */
930  if (hw->phy.sfp_setup_needed) {
931  status = hw->mac.ops.setup_sfp(hw);
932  hw->phy.sfp_setup_needed = false;
933  }
934 
935  if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
936  goto reset_hw_out;
937 
938  /* Reset PHY */
939  if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
940  hw->phy.ops.reset(hw);
941 
942 mac_reset_top:
943  /*
944  * Issue global reset to the MAC. Needs to be SW reset if link is up.
945  * If link reset is used when link is up, it might reset the PHY when
946  * mng is using it. If link is down or the flag to force full link
947  * reset is set, then perform link reset.
948  */
949  ctrl = IXGBE_CTRL_LNK_RST;
950  if (!hw->force_full_reset) {
951  hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
952  if (link_up)
953  ctrl = IXGBE_CTRL_RST;
954  }
955 
956  ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
957  IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
958  IXGBE_WRITE_FLUSH(hw);
959 
960  /* Poll for reset bit to self-clear indicating reset is complete */
961  for (i = 0; i < 10; i++) {
962  udelay(1);
963  ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
964  if (!(ctrl & IXGBE_CTRL_RST_MASK))
965  break;
966  }
967 
968  if (ctrl & IXGBE_CTRL_RST_MASK) {
969  status = IXGBE_ERR_RESET_FAILED;
970  hw_dbg(hw, "Reset polling failed to complete.\n");
971  }
972 
973  msleep(50);
974 
975  /*
976  * Double resets are required for recovery from certain error
977  * conditions. Between resets, it is necessary to stall to allow time
978  * for any pending HW events to complete.
979  */
980  if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
981  hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
982  goto mac_reset_top;
983  }
984 
985  /*
986  * Store the original AUTOC/AUTOC2 values if they have not been
987  * stored off yet. Otherwise restore the stored original
988  * values since the reset operation sets back to defaults.
989  */
990  autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
991  autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
992  if (hw->mac.orig_link_settings_stored == false) {
993  hw->mac.orig_autoc = autoc;
994  hw->mac.orig_autoc2 = autoc2;
995  hw->mac.orig_link_settings_stored = true;
996  } else {
997  if (autoc != hw->mac.orig_autoc)
998  IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
999  IXGBE_AUTOC_AN_RESTART));
1000 
1001  if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1002  (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1003  autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1004  autoc2 |= (hw->mac.orig_autoc2 &
1005  IXGBE_AUTOC2_UPPER_MASK);
1006  IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1007  }
1008  }
1009 
1010  /* Store the permanent mac address */
1011  hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1012 
1013  /*
1014  * Store MAC address from RAR0, clear receive address registers, and
1015  * clear the multicast table. Also reset num_rar_entries to 128,
1016  * since we modify this value when programming the SAN MAC address.
1017  */
1018  hw->mac.num_rar_entries = 128;
1019  hw->mac.ops.init_rx_addrs(hw);
1020 
1021  /* Store the permanent SAN mac address */
1022  hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1023 
1024  /* Add the SAN MAC address to the RAR only if it's a valid address */
1025  if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1026  hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1027  hw->mac.san_addr, 0, IXGBE_RAH_AV);
1028 
1029  /* Save the SAN MAC RAR index */
1030  hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1031 
1032  /* Reserve the last RAR for the SAN MAC address */
1033  hw->mac.num_rar_entries--;
1034  }
1035 
1036  /* Store the alternative WWNN/WWPN prefix */
1037  hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1038  &hw->mac.wwpn_prefix);
1039 
1040 reset_hw_out:
1041  return status;
1042 }
1043 
1048 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1049 {
1050  int i;
1051  u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1052  fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1053 
1054  /*
1055  * Before starting reinitialization process,
1056  * FDIRCMD.CMD must be zero.
1057  */
1058  for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1059  if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1060  IXGBE_FDIRCMD_CMD_MASK))
1061  break;
1062  udelay(10);
1063  }
1064  if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1065  hw_dbg(hw, "Flow Director previous command isn't complete, "
1066  "aborting table re-initialization.\n");
1067  return IXGBE_ERR_FDIR_REINIT_FAILED;
1068  }
1069 
1070  IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1071  IXGBE_WRITE_FLUSH(hw);
1072  /*
1073  * 82599 adapters flow director init flow cannot be restarted,
1074  * Workaround 82599 silicon errata by performing the following steps
1075  * before re-writing the FDIRCTRL control register with the same value.
1076  * - write 1 to bit 8 of FDIRCMD register &
1077  * - write 0 to bit 8 of FDIRCMD register
1078  */
1079  IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1080  (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1081  IXGBE_FDIRCMD_CLEARHT));
1082  IXGBE_WRITE_FLUSH(hw);
1083  IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1084  (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1085  ~IXGBE_FDIRCMD_CLEARHT));
1086  IXGBE_WRITE_FLUSH(hw);
1087  /*
1088  * Clear FDIR Hash register to clear any leftover hashes
1089  * waiting to be programmed.
1090  */
1091  IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1092  IXGBE_WRITE_FLUSH(hw);
1093 
1094  IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1095  IXGBE_WRITE_FLUSH(hw);
1096 
1097  /* Poll init-done after we write FDIRCTRL register */
1098  for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1099  if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1100  IXGBE_FDIRCTRL_INIT_DONE)
1101  break;
1102  usleep_range(1000, 2000);
1103  }
1104  if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1105  hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1106  return IXGBE_ERR_FDIR_REINIT_FAILED;
1107  }
1108 
1109  /* Clear FDIR statistics registers (read to clear) */
1110  IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1111  IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1112  IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1113  IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1114  IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1115 
1116  return 0;
1117 }
1118 
1124 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1125 {
1126  int i;
1127 
1128  /* Prime the keys for hashing */
1129  IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1130  IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1131 
1132  /*
1133  * Poll init-done after we write the register. Estimated times:
1134  * 10G: PBALLOC = 11b, timing is 60us
1135  * 1G: PBALLOC = 11b, timing is 600us
1136  * 100M: PBALLOC = 11b, timing is 6ms
1137  *
1138  * Multiple these timings by 4 if under full Rx load
1139  *
1140  * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1141  * 1 msec per poll time. If we're at line rate and drop to 100M, then
1142  * this might not finish in our poll time, but we can live with that
1143  * for now.
1144  */
1145  IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1146  IXGBE_WRITE_FLUSH(hw);
1147  for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1148  if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1149  IXGBE_FDIRCTRL_INIT_DONE)
1150  break;
1151  usleep_range(1000, 2000);
1152  }
1153 
1154  if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1155  hw_dbg(hw, "Flow Director poll time exceeded!\n");
1156 }
1157 
1164 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1165 {
1166  /*
1167  * Continue setup of fdirctrl register bits:
1168  * Move the flexible bytes to use the ethertype - shift 6 words
1169  * Set the maximum length per hash bucket to 0xA filters
1170  * Send interrupt when 64 filters are left
1171  */
1172  fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1173  (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1174  (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1175 
1176  /* write hashes and fdirctrl register, poll for completion */
1177  ixgbe_fdir_enable_82599(hw, fdirctrl);
1178 
1179  return 0;
1180 }
1181 
1188 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1189 {
1190  /*
1191  * Continue setup of fdirctrl register bits:
1192  * Turn perfect match filtering on
1193  * Report hash in RSS field of Rx wb descriptor
1194  * Initialize the drop queue
1195  * Move the flexible bytes to use the ethertype - shift 6 words
1196  * Set the maximum length per hash bucket to 0xA filters
1197  * Send interrupt when 64 (0x4 * 16) filters are left
1198  */
1199  fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1200  IXGBE_FDIRCTRL_REPORT_STATUS |
1201  (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1202  (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1203  (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1204  (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1205 
1206  /* write hashes and fdirctrl register, poll for completion */
1207  ixgbe_fdir_enable_82599(hw, fdirctrl);
1208 
1209  return 0;
1210 }
1211 
1212 /*
1213  * These defines allow us to quickly generate all of the necessary instructions
1214  * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1215  * for values 0 through 15
1216  */
1217 #define IXGBE_ATR_COMMON_HASH_KEY \
1218  (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1219 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1220 do { \
1221  u32 n = (_n); \
1222  if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1223  common_hash ^= lo_hash_dword >> n; \
1224  else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1225  bucket_hash ^= lo_hash_dword >> n; \
1226  else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1227  sig_hash ^= lo_hash_dword << (16 - n); \
1228  if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1229  common_hash ^= hi_hash_dword >> n; \
1230  else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1231  bucket_hash ^= hi_hash_dword >> n; \
1232  else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1233  sig_hash ^= hi_hash_dword << (16 - n); \
1234 } while (0);
1235 
1246 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1247  union ixgbe_atr_hash_dword common)
1248 {
1249  u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1250  u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1251 
1252  /* record the flow_vm_vlan bits as they are a key part to the hash */
1253  flow_vm_vlan = ntohl(input.dword);
1254 
1255  /* generate common hash dword */
1256  hi_hash_dword = ntohl(common.dword);
1257 
1258  /* low dword is word swapped version of common */
1259  lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1260 
1261  /* apply flow ID/VM pool/VLAN ID bits to hash words */
1262  hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1263 
1264  /* Process bits 0 and 16 */
1265  IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1266 
1267  /*
1268  * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1269  * delay this because bit 0 of the stream should not be processed
1270  * so we do not add the vlan until after bit 0 was processed
1271  */
1272  lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1273 
1274  /* Process remaining 30 bit of the key */
1275  IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1276  IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1277  IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1278  IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1279  IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1280  IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1281  IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1282  IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1283  IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1284  IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1285  IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1286  IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1287  IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1288  IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1289  IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1290 
1291  /* combine common_hash result with signature and bucket hashes */
1292  bucket_hash ^= common_hash;
1293  bucket_hash &= IXGBE_ATR_HASH_MASK;
1294 
1295  sig_hash ^= common_hash << 16;
1296  sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1297 
1298  /* return completed signature hash */
1299  return sig_hash ^ bucket_hash;
1300 }
1301 
1309 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1310  union ixgbe_atr_hash_dword input,
1311  union ixgbe_atr_hash_dword common,
1312  u8 queue)
1313 {
1314  u64 fdirhashcmd;
1315  u32 fdircmd;
1316 
1317  /*
1318  * Get the flow_type in order to program FDIRCMD properly
1319  * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1320  */
1321  switch (input.formatted.flow_type) {
1322  case IXGBE_ATR_FLOW_TYPE_TCPV4:
1323  case IXGBE_ATR_FLOW_TYPE_UDPV4:
1324  case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1325  case IXGBE_ATR_FLOW_TYPE_TCPV6:
1326  case IXGBE_ATR_FLOW_TYPE_UDPV6:
1327  case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1328  break;
1329  default:
1330  hw_dbg(hw, " Error on flow type input\n");
1331  return IXGBE_ERR_CONFIG;
1332  }
1333 
1334  /* configure FDIRCMD register */
1335  fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1336  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1337  fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1338  fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1339 
1340  /*
1341  * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1342  * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1343  */
1344  fdirhashcmd = (u64)fdircmd << 32;
1345  fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1346  IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1347 
1348  hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1349 
1350  return 0;
1351 }
1352 
1353 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1354 do { \
1355  u32 n = (_n); \
1356  if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1357  bucket_hash ^= lo_hash_dword >> n; \
1358  if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1359  bucket_hash ^= hi_hash_dword >> n; \
1360 } while (0);
1361 
1373 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1374  union ixgbe_atr_input *input_mask)
1375 {
1376 
1377  u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1378  u32 bucket_hash = 0;
1379 
1380  /* Apply masks to input data */
1381  input->dword_stream[0] &= input_mask->dword_stream[0];
1382  input->dword_stream[1] &= input_mask->dword_stream[1];
1383  input->dword_stream[2] &= input_mask->dword_stream[2];
1384  input->dword_stream[3] &= input_mask->dword_stream[3];
1385  input->dword_stream[4] &= input_mask->dword_stream[4];
1386  input->dword_stream[5] &= input_mask->dword_stream[5];
1387  input->dword_stream[6] &= input_mask->dword_stream[6];
1388  input->dword_stream[7] &= input_mask->dword_stream[7];
1389  input->dword_stream[8] &= input_mask->dword_stream[8];
1390  input->dword_stream[9] &= input_mask->dword_stream[9];
1391  input->dword_stream[10] &= input_mask->dword_stream[10];
1392 
1393  /* record the flow_vm_vlan bits as they are a key part to the hash */
1394  flow_vm_vlan = ntohl(input->dword_stream[0]);
1395 
1396  /* generate common hash dword */
1397  hi_hash_dword = ntohl(input->dword_stream[1] ^
1398  input->dword_stream[2] ^
1399  input->dword_stream[3] ^
1400  input->dword_stream[4] ^
1401  input->dword_stream[5] ^
1402  input->dword_stream[6] ^
1403  input->dword_stream[7] ^
1404  input->dword_stream[8] ^
1405  input->dword_stream[9] ^
1406  input->dword_stream[10]);
1407 
1408  /* low dword is word swapped version of common */
1409  lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1410 
1411  /* apply flow ID/VM pool/VLAN ID bits to hash words */
1412  hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1413 
1414  /* Process bits 0 and 16 */
1415  IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1416 
1417  /*
1418  * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1419  * delay this because bit 0 of the stream should not be processed
1420  * so we do not add the vlan until after bit 0 was processed
1421  */
1422  lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1423 
1424  /* Process remaining 30 bit of the key */
1425  IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1426  IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1427  IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1428  IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1429  IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1430  IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1431  IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1432  IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1433  IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1434  IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1435  IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1436  IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1437  IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1438  IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1439  IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1440 
1441  /*
1442  * Limit hash to 13 bits since max bucket count is 8K.
1443  * Store result at the end of the input stream.
1444  */
1445  input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1446 }
1447 
1457 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1458 {
1459  u32 mask = ntohs(input_mask->formatted.dst_port);
1460  mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1461  mask |= ntohs(input_mask->formatted.src_port);
1462  mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1463  mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1464  mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1465  return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1466 }
1467 
1468 /*
1469  * These two macros are meant to address the fact that we have registers
1470  * that are either all or in part big-endian. As a result on big-endian
1471  * systems we will end up byte swapping the value to little-endian before
1472  * it is byte swapped again and written to the hardware in the original
1473  * big-endian format.
1474  */
1475 #define IXGBE_STORE_AS_BE32(_value) \
1476  (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1477  (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1478 
1479 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1480  IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1481 
1482 #define IXGBE_STORE_AS_BE16(_value) \
1483  ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1484 
1485 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1486  union ixgbe_atr_input *input_mask)
1487 {
1488  /* mask IPv6 since it is currently not supported */
1489  u32 fdirm = IXGBE_FDIRM_DIPv6;
1490  u32 fdirtcpm;
1491 
1492  /*
1493  * Program the relevant mask registers. If src/dst_port or src/dst_addr
1494  * are zero, then assume a full mask for that field. Also assume that
1495  * a VLAN of 0 is unspecified, so mask that out as well. L4type
1496  * cannot be masked out in this implementation.
1497  *
1498  * This also assumes IPv4 only. IPv6 masking isn't supported at this
1499  * point in time.
1500  */
1501 
1502  /* verify bucket hash is cleared on hash generation */
1503  if (input_mask->formatted.bkt_hash)
1504  hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1505 
1506  /* Program FDIRM and verify partial masks */
1507  switch (input_mask->formatted.vm_pool & 0x7F) {
1508  case 0x0:
1509  fdirm |= IXGBE_FDIRM_POOL;
1510  case 0x7F:
1511  break;
1512  default:
1513  hw_dbg(hw, " Error on vm pool mask\n");
1514  return IXGBE_ERR_CONFIG;
1515  }
1516 
1517  switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1518  case 0x0:
1519  fdirm |= IXGBE_FDIRM_L4P;
1520  if (input_mask->formatted.dst_port ||
1521  input_mask->formatted.src_port) {
1522  hw_dbg(hw, " Error on src/dst port mask\n");
1523  return IXGBE_ERR_CONFIG;
1524  }
1525  case IXGBE_ATR_L4TYPE_MASK:
1526  break;
1527  default:
1528  hw_dbg(hw, " Error on flow type mask\n");
1529  return IXGBE_ERR_CONFIG;
1530  }
1531 
1532  switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1533  case 0x0000:
1534  /* mask VLAN ID, fall through to mask VLAN priority */
1535  fdirm |= IXGBE_FDIRM_VLANID;
1536  case 0x0FFF:
1537  /* mask VLAN priority */
1538  fdirm |= IXGBE_FDIRM_VLANP;
1539  break;
1540  case 0xE000:
1541  /* mask VLAN ID only, fall through */
1542  fdirm |= IXGBE_FDIRM_VLANID;
1543  case 0xEFFF:
1544  /* no VLAN fields masked */
1545  break;
1546  default:
1547  hw_dbg(hw, " Error on VLAN mask\n");
1548  return IXGBE_ERR_CONFIG;
1549  }
1550 
1551  switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1552  case 0x0000:
1553  /* Mask Flex Bytes, fall through */
1554  fdirm |= IXGBE_FDIRM_FLEX;
1555  case 0xFFFF:
1556  break;
1557  default:
1558  hw_dbg(hw, " Error on flexible byte mask\n");
1559  return IXGBE_ERR_CONFIG;
1560  }
1561 
1562  /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1563  IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1564 
1565  /* store the TCP/UDP port masks, bit reversed from port layout */
1566  fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1567 
1568  /* write both the same so that UDP and TCP use the same mask */
1569  IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1570  IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1571 
1572  /* store source and destination IP masks (big-enian) */
1573  IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1574  ~input_mask->formatted.src_ip[0]);
1575  IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1576  ~input_mask->formatted.dst_ip[0]);
1577 
1578  return 0;
1579 }
1580 
1581 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1582  union ixgbe_atr_input *input,
1583  u16 soft_id, u8 queue)
1584 {
1585  u32 fdirport, fdirvlan, fdirhash, fdircmd;
1586 
1587  /* currently IPv6 is not supported, must be programmed with 0 */
1588  IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1589  input->formatted.src_ip[0]);
1590  IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1591  input->formatted.src_ip[1]);
1592  IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1593  input->formatted.src_ip[2]);
1594 
1595  /* record the source address (big-endian) */
1596  IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1597 
1598  /* record the first 32 bits of the destination address (big-endian) */
1599  IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1600 
1601  /* record source and destination port (little-endian)*/
1602  fdirport = ntohs(input->formatted.dst_port);
1603  fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1604  fdirport |= ntohs(input->formatted.src_port);
1605  IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1606 
1607  /* record vlan (little-endian) and flex_bytes(big-endian) */
1608  fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1609  fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1610  fdirvlan |= ntohs(input->formatted.vlan_id);
1611  IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1612 
1613  /* configure FDIRHASH register */
1614  fdirhash = input->formatted.bkt_hash;
1615  fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1616  IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1617 
1618  /*
1619  * flush all previous writes to make certain registers are
1620  * programmed prior to issuing the command
1621  */
1622  IXGBE_WRITE_FLUSH(hw);
1623 
1624  /* configure FDIRCMD register */
1625  fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1626  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1627  if (queue == IXGBE_FDIR_DROP_QUEUE)
1628  fdircmd |= IXGBE_FDIRCMD_DROP;
1629  fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1630  fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1631  fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1632 
1633  IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1634 
1635  return 0;
1636 }
1637 
1638 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1639  union ixgbe_atr_input *input,
1640  u16 soft_id)
1641 {
1642  u32 fdirhash;
1643  u32 fdircmd = 0;
1644  u32 retry_count;
1645  s32 err = 0;
1646 
1647  /* configure FDIRHASH register */
1648  fdirhash = input->formatted.bkt_hash;
1649  fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1650  IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1651 
1652  /* flush hash to HW */
1653  IXGBE_WRITE_FLUSH(hw);
1654 
1655  /* Query if filter is present */
1656  IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1657 
1658  for (retry_count = 10; retry_count; retry_count--) {
1659  /* allow 10us for query to process */
1660  udelay(10);
1661  /* verify query completed successfully */
1662  fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1663  if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1664  break;
1665  }
1666 
1667  if (!retry_count)
1668  err = IXGBE_ERR_FDIR_REINIT_FAILED;
1669 
1670  /* if filter exists in hardware then remove it */
1671  if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1672  IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1673  IXGBE_WRITE_FLUSH(hw);
1674  IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1675  IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1676  }
1677 
1678  return err;
1679 }
1680 
1689 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1690 {
1691  u32 core_ctl;
1692 
1693  IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1694  (reg << 8));
1695  IXGBE_WRITE_FLUSH(hw);
1696  udelay(10);
1697  core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1698  *val = (u8)core_ctl;
1699 
1700  return 0;
1701 }
1702 
1711 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1712 {
1713  u32 core_ctl;
1714 
1715  core_ctl = (reg << 8) | val;
1716  IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1717  IXGBE_WRITE_FLUSH(hw);
1718  udelay(10);
1719 
1720  return 0;
1721 }
1722 
1731 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1732 {
1733  s32 ret_val = 0;
1734 
1735  ret_val = ixgbe_start_hw_generic(hw);
1736  if (ret_val != 0)
1737  goto out;
1738 
1739  ret_val = ixgbe_start_hw_gen2(hw);
1740  if (ret_val != 0)
1741  goto out;
1742 
1743  /* We need to run link autotry after the driver loads */
1744  hw->mac.autotry_restart = true;
1745  hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1746 
1747  if (ret_val == 0)
1748  ret_val = ixgbe_verify_fw_version_82599(hw);
1749 out:
1750  return ret_val;
1751 }
1752 
1761 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1762 {
1763  s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1764 
1765  /* Detect PHY if not unknown - returns success if already detected. */
1766  status = ixgbe_identify_phy_generic(hw);
1767  if (status != 0) {
1768  /* 82599 10GBASE-T requires an external PHY */
1769  if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1770  goto out;
1771  else
1772  status = ixgbe_identify_sfp_module_generic(hw);
1773  }
1774 
1775  /* Set PHY type none if no PHY detected */
1776  if (hw->phy.type == ixgbe_phy_unknown) {
1777  hw->phy.type = ixgbe_phy_none;
1778  status = 0;
1779  }
1780 
1781  /* Return error if SFP module has been detected but is not supported */
1782  if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1783  status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1784 
1785 out:
1786  return status;
1787 }
1788 
1795 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1796 {
1797  u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1798  u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1799  u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1800  u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1801  u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1802  u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1803  u16 ext_ability = 0;
1804  u8 comp_codes_10g = 0;
1805  u8 comp_codes_1g = 0;
1806 
1807  hw->phy.ops.identify(hw);
1808 
1809  switch (hw->phy.type) {
1810  case ixgbe_phy_tn:
1811  case ixgbe_phy_cu_unknown:
1812  hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1813  &ext_ability);
1814  if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1815  physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1816  if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1817  physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1818  if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1819  physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1820  goto out;
1821  default:
1822  break;
1823  }
1824 
1825  switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1826  case IXGBE_AUTOC_LMS_1G_AN:
1827  case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1828  if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1829  physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1830  IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1831  goto out;
1832  } else
1833  /* SFI mode so read SFP module */
1834  goto sfp_check;
1835  break;
1836  case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1837  if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1838  physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1839  else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1840  physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1841  else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1842  physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1843  goto out;
1844  break;
1845  case IXGBE_AUTOC_LMS_10G_SERIAL:
1846  if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1847  physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1848  goto out;
1849  } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1850  goto sfp_check;
1851  break;
1852  case IXGBE_AUTOC_LMS_KX4_KX_KR:
1853  case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1854  if (autoc & IXGBE_AUTOC_KX_SUPP)
1855  physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1856  if (autoc & IXGBE_AUTOC_KX4_SUPP)
1857  physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1858  if (autoc & IXGBE_AUTOC_KR_SUPP)
1859  physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1860  goto out;
1861  break;
1862  default:
1863  goto out;
1864  break;
1865  }
1866 
1867 sfp_check:
1868  /* SFP check must be done last since DA modules are sometimes used to
1869  * test KR mode - we need to id KR mode correctly before SFP module.
1870  * Call identify_sfp because the pluggable module may have changed */
1871  hw->phy.ops.identify_sfp(hw);
1872  if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1873  goto out;
1874 
1875  switch (hw->phy.type) {
1876  case ixgbe_phy_sfp_passive_tyco:
1877  case ixgbe_phy_sfp_passive_unknown:
1878  physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1879  break;
1880  case ixgbe_phy_sfp_ftl_active:
1881  case ixgbe_phy_sfp_active_unknown:
1882  physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1883  break;
1884  case ixgbe_phy_sfp_avago:
1885  case ixgbe_phy_sfp_ftl:
1886  case ixgbe_phy_sfp_intel:
1887  case ixgbe_phy_sfp_unknown:
1888  hw->phy.ops.read_i2c_eeprom(hw,
1889  IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1890  hw->phy.ops.read_i2c_eeprom(hw,
1891  IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1892  if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1893  physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1894  else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1895  physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1896  else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1897  physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1898  break;
1899  default:
1900  break;
1901  }
1902 
1903 out:
1904  return physical_layer;
1905 }
1906 
1914 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1915 {
1916  /*
1917  * Workaround for 82599 silicon errata when enabling the Rx datapath.
1918  * If traffic is incoming before we enable the Rx unit, it could hang
1919  * the Rx DMA unit. Therefore, make sure the security engine is
1920  * completely disabled prior to enabling the Rx unit.
1921  */
1922  hw->mac.ops.disable_rx_buff(hw);
1923 
1924  IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1925 
1926  hw->mac.ops.enable_rx_buff(hw);
1927 
1928  return 0;
1929 }
1930 
1941 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1942 {
1943  s32 status = IXGBE_ERR_EEPROM_VERSION;
1944  u16 fw_offset, fw_ptp_cfg_offset;
1945  u16 fw_version = 0;
1946 
1947  /* firmware check is only necessary for SFI devices */
1948  if (hw->phy.media_type != ixgbe_media_type_fiber) {
1949  status = 0;
1950  goto fw_version_out;
1951  }
1952 
1953  /* get the offset to the Firmware Module block */
1954  hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
1955 
1956  if ((fw_offset == 0) || (fw_offset == 0xFFFF))
1957  goto fw_version_out;
1958 
1959  /* get the offset to the Pass Through Patch Configuration block */
1960  hw->eeprom.ops.read(hw, (fw_offset +
1961  IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
1962  &fw_ptp_cfg_offset);
1963 
1964  if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
1965  goto fw_version_out;
1966 
1967  /* get the firmware version */
1968  hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
1969  IXGBE_FW_PATCH_VERSION_4),
1970  &fw_version);
1971 
1972  if (fw_version > 0x5)
1973  status = 0;
1974 
1975 fw_version_out:
1976  return status;
1977 }
1978 
1986 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
1987 {
1988  bool lesm_enabled = false;
1989  u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
1990  s32 status;
1991 
1992  /* get the offset to the Firmware Module block */
1993  status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
1994 
1995  if ((status != 0) ||
1996  (fw_offset == 0) || (fw_offset == 0xFFFF))
1997  goto out;
1998 
1999  /* get the offset to the LESM Parameters block */
2000  status = hw->eeprom.ops.read(hw, (fw_offset +
2001  IXGBE_FW_LESM_PARAMETERS_PTR),
2002  &fw_lesm_param_offset);
2003 
2004  if ((status != 0) ||
2005  (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2006  goto out;
2007 
2008  /* get the lesm state word */
2009  status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2010  IXGBE_FW_LESM_STATE_1),
2011  &fw_lesm_state);
2012 
2013  if ((status == 0) &&
2014  (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2015  lesm_enabled = true;
2016 
2017 out:
2018  return lesm_enabled;
2019 }
2020 
2032 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2033  u16 words, u16 *data)
2034 {
2035  struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2036  s32 ret_val = IXGBE_ERR_CONFIG;
2037 
2038  /*
2039  * If EEPROM is detected and can be addressed using 14 bits,
2040  * use EERD otherwise use bit bang
2041  */
2042  if ((eeprom->type == ixgbe_eeprom_spi) &&
2043  (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2044  ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2045  data);
2046  else
2047  ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2048  words,
2049  data);
2050 
2051  return ret_val;
2052 }
2053 
2064 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2065  u16 offset, u16 *data)
2066 {
2067  struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2068  s32 ret_val = IXGBE_ERR_CONFIG;
2069 
2070  /*
2071  * If EEPROM is detected and can be addressed using 14 bits,
2072  * use EERD otherwise use bit bang
2073  */
2074  if ((eeprom->type == ixgbe_eeprom_spi) &&
2075  (offset <= IXGBE_EERD_MAX_ADDR))
2076  ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2077  else
2078  ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2079 
2080  return ret_val;
2081 }
2082 
2083 static struct ixgbe_mac_operations mac_ops_82599 = {
2084  .init_hw = &ixgbe_init_hw_generic,
2085  .reset_hw = &ixgbe_reset_hw_82599,
2086  .start_hw = &ixgbe_start_hw_82599,
2087  .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2088  .get_media_type = &ixgbe_get_media_type_82599,
2089  .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2090  .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2091  .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2092  .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
2093  .get_mac_addr = &ixgbe_get_mac_addr_generic,
2094  .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2095  .get_device_caps = &ixgbe_get_device_caps_generic,
2096  .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2097  .stop_adapter = &ixgbe_stop_adapter_generic,
2098  .get_bus_info = &ixgbe_get_bus_info_generic,
2099  .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2100  .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2101  .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2102  .setup_link = &ixgbe_setup_mac_link_82599,
2103  .set_rxpba = &ixgbe_set_rxpba_generic,
2104  .check_link = &ixgbe_check_mac_link_generic,
2105  .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2106  .led_on = &ixgbe_led_on_generic,
2107  .led_off = &ixgbe_led_off_generic,
2108  .blink_led_start = &ixgbe_blink_led_start_generic,
2109  .blink_led_stop = &ixgbe_blink_led_stop_generic,
2110  .set_rar = &ixgbe_set_rar_generic,
2111  .clear_rar = &ixgbe_clear_rar_generic,
2112  .set_vmdq = &ixgbe_set_vmdq_generic,
2113  .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
2114  .clear_vmdq = &ixgbe_clear_vmdq_generic,
2115  .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2116  .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2117  .enable_mc = &ixgbe_enable_mc_generic,
2118  .disable_mc = &ixgbe_disable_mc_generic,
2119  .clear_vfta = &ixgbe_clear_vfta_generic,
2120  .set_vfta = &ixgbe_set_vfta_generic,
2121  .fc_enable = &ixgbe_fc_enable_generic,
2122  .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2123  .init_uta_tables = &ixgbe_init_uta_tables_generic,
2124  .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2125  .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2126  .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2127  .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2128  .release_swfw_sync = &ixgbe_release_swfw_sync,
2129  .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2130  .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
2131 
2132 };
2133 
2134 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2135  .init_params = &ixgbe_init_eeprom_params_generic,
2136  .read = &ixgbe_read_eeprom_82599,
2137  .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2138  .write = &ixgbe_write_eeprom_generic,
2139  .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2140  .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2141  .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2142  .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2143 };
2144 
2145 static struct ixgbe_phy_operations phy_ops_82599 = {
2146  .identify = &ixgbe_identify_phy_82599,
2147  .identify_sfp = &ixgbe_identify_sfp_module_generic,
2148  .init = &ixgbe_init_phy_ops_82599,
2149  .reset = &ixgbe_reset_phy_generic,
2150  .read_reg = &ixgbe_read_phy_reg_generic,
2151  .write_reg = &ixgbe_write_phy_reg_generic,
2152  .setup_link = &ixgbe_setup_phy_link_generic,
2153  .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2154  .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2155  .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2156  .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2157  .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2158  .check_overtemp = &ixgbe_tn_check_overtemp,
2159 };
2160 
2161 struct ixgbe_info ixgbe_82599_info = {
2162  .mac = ixgbe_mac_82599EB,
2163  .get_invariants = &ixgbe_get_invariants_82599,
2164  .mac_ops = &mac_ops_82599,
2165  .eeprom_ops = &eeprom_ops_82599,
2166  .phy_ops = &phy_ops_82599,
2167  .mbx_ops = &mbx_ops_generic,
2168 };
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