#include <linux/types.h>
#include <linux/mdio.h>
#include <linux/netdevice.h>
#include "ixgbe_mbx.h"

Data Structures
struct	ixgbe_thermal_diode_data

struct	ixgbe_thermal_sensor_data

struct	ixgbe_hic_hdr

struct	ixgbe_hic_drv_info

union	ixgbe_adv_tx_desc

union	ixgbe_adv_rx_desc

struct	ixgbe_adv_tx_context_desc

union	ixgbe_atr_input

union	ixgbe_atr_hash_dword

struct	ixgbe_addr_filter_info

struct	ixgbe_bus_info

struct	ixgbe_fc_info

struct	ixgbe_hw_stats

struct	ixgbe_eeprom_operations

struct	ixgbe_mac_operations

struct	ixgbe_phy_operations

struct	ixgbe_eeprom_info

struct	ixgbe_mac_info

struct	ixgbe_phy_info

struct	ixgbe_mbx_operations

struct	ixgbe_mbx_stats

struct	ixgbe_mbx_info

struct	ixgbe_hw

struct	ixgbe_info

Macros
#define	IXGBE_DEV_ID_82598 0x10B6

#define	IXGBE_DEV_ID_82598_BX 0x1508

#define	IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6

#define	IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7

#define	IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB

#define	IXGBE_DEV_ID_82598AT 0x10C8

#define	IXGBE_DEV_ID_82598AT2 0x150B

#define	IXGBE_DEV_ID_82598EB_CX4 0x10DD

#define	IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC

#define	IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1

#define	IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1

#define	IXGBE_DEV_ID_82598EB_XF_LR 0x10F4

#define	IXGBE_DEV_ID_82599_KX4 0x10F7

#define	IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514

#define	IXGBE_DEV_ID_82599_KR 0x1517

#define	IXGBE_DEV_ID_82599_T3_LOM 0x151C

#define	IXGBE_DEV_ID_82599_CX4 0x10F9

#define	IXGBE_DEV_ID_82599_SFP 0x10FB

#define	IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a

#define	IXGBE_DEV_ID_82599_SFP_FCOE 0x1529

#define	IXGBE_SUBDEV_ID_82599_SFP 0x11A9

#define	IXGBE_SUBDEV_ID_82599_RNDC 0x1F72

#define	IXGBE_SUBDEV_ID_82599_560FLR 0x17D0

#define	IXGBE_DEV_ID_82599_SFP_EM 0x1507

#define	IXGBE_DEV_ID_82599_SFP_SF2 0x154D

#define	IXGBE_DEV_ID_82599EN_SFP 0x1557

#define	IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC

#define	IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8

#define	IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C

#define	IXGBE_DEV_ID_82599_LS 0x154F

#define	IXGBE_DEV_ID_X540T 0x1528

#define	IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A

#define	IXGBE_DEV_ID_X540T1 0x1560

#define	IXGBE_DEV_ID_82599_VF 0x10ED

#define	IXGBE_DEV_ID_X540_VF 0x1515

#define	IXGBE_CTRL 0x00000

#define	IXGBE_STATUS 0x00008

#define	IXGBE_CTRL_EXT 0x00018

#define	IXGBE_ESDP 0x00020

#define	IXGBE_EODSDP 0x00028

#define	IXGBE_I2CCTL 0x00028

#define	IXGBE_LEDCTL 0x00200

#define	IXGBE_FRTIMER 0x00048

#define	IXGBE_TCPTIMER 0x0004C

#define	IXGBE_CORESPARE 0x00600

#define	IXGBE_EXVET 0x05078

#define	IXGBE_EEC 0x10010

#define	IXGBE_EERD 0x10014

#define	IXGBE_EEWR 0x10018

#define	IXGBE_FLA 0x1001C

#define	IXGBE_EEMNGCTL 0x10110

#define	IXGBE_EEMNGDATA 0x10114

#define	IXGBE_FLMNGCTL 0x10118

#define	IXGBE_FLMNGDATA 0x1011C

#define	IXGBE_FLMNGCNT 0x10120

#define	IXGBE_FLOP 0x1013C

#define	IXGBE_GRC 0x10200

#define	IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */

#define	IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */

#define	IXGBE_VPDDIAG0 0x10204

#define	IXGBE_VPDDIAG1 0x10208

#define	IXGBE_I2C_CLK_IN 0x00000001

#define	IXGBE_I2C_CLK_OUT 0x00000002

#define	IXGBE_I2C_DATA_IN 0x00000004

#define	IXGBE_I2C_DATA_OUT 0x00000008

#define	IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500

#define	IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8

#define	IXGBE_EMC_INTERNAL_DATA 0x00

#define	IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20

#define	IXGBE_EMC_DIODE1_DATA 0x01

#define	IXGBE_EMC_DIODE1_THERM_LIMIT 0x19

#define	IXGBE_EMC_DIODE2_DATA 0x23

#define	IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A

#define	IXGBE_MAX_SENSORS 3

#define	IXGBE_EICR 0x00800

#define	IXGBE_EICS 0x00808

#define	IXGBE_EIMS 0x00880

#define	IXGBE_EIMC 0x00888

#define	IXGBE_EIAC 0x00810

#define	IXGBE_EIAM 0x00890

#define	IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)

#define	IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)

#define	IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)

#define	IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)

#define	IXGBE_MAX_INT_RATE 488281

#define	IXGBE_MIN_INT_RATE 956

#define	IXGBE_MAX_EITR 0x00000FF8

#define	IXGBE_MIN_EITR 8

#define	IXGBE_EITR(_i)

#define	IXGBE_EITR_ITR_INT_MASK 0x00000FF8

#define	IXGBE_EITR_LLI_MOD 0x00008000

#define	IXGBE_EITR_CNT_WDIS 0x80000000

#define	IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */

#define	IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */

#define	IXGBE_EITRSEL 0x00894

#define	IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */

#define	IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */

#define	IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))

#define	IXGBE_GPIE 0x00898

#define	IXGBE_FCADBUL 0x03210

#define	IXGBE_FCADBUH 0x03214

#define	IXGBE_FCAMACL 0x04328

#define	IXGBE_FCAMACH 0x0432C

#define	IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_PFCTOP 0x03008

#define	IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */

#define	IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */

#define	IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */

#define	IXGBE_FCRTV 0x032A0

#define	IXGBE_FCCFG 0x03D00

#define	IXGBE_TFCS 0x0CE00

#define	IXGBE_RDBAL(_i)

#define	IXGBE_RDBAH(_i)

#define	IXGBE_RDLEN(_i)

#define	IXGBE_RDH(_i)

#define	IXGBE_RDT(_i)

#define	IXGBE_RXDCTL(_i)

#define	IXGBE_RSCCTL(_i)

#define	IXGBE_RSCDBU 0x03028

#define	IXGBE_RDDCC 0x02F20

#define	IXGBE_RXMEMWRAP 0x03190

#define	IXGBE_STARCTRL 0x03024

#define	IXGBE_SRRCTL(_i)

#define	IXGBE_DCA_RXCTRL(_i)

#define	IXGBE_RDRXCTL 0x02F00

#define	IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))

#define	IXGBE_RXCTRL 0x03000

#define	IXGBE_DROPEN 0x03D04

#define	IXGBE_RXPBSIZE_SHIFT 10

#define	IXGBE_RXCSUM 0x05000

#define	IXGBE_RFCTL 0x05008

#define	IXGBE_DRECCCTL 0x02F08

#define	IXGBE_DRECCCTL_DISABLE 0

#define	IXGBE_MTA(_i) (0x05200 + ((_i) * 4))

#define	IXGBE_RAL(_i)

#define	IXGBE_RAH(_i)

#define	IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))

#define	IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))

#define	IXGBE_PSRTYPE(_i)

#define	IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))

#define	IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))

#define	IXGBE_FCTRL 0x05080

#define	IXGBE_VLNCTRL 0x05088

#define	IXGBE_MCSTCTRL 0x05090

#define	IXGBE_MRQC 0x05818

#define	IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */

#define	IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */

#define	IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */

#define	IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */

#define	IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */

#define	IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */

#define	IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */

#define	IXGBE_RQTC 0x0EC70

#define	IXGBE_MTQC 0x08120

#define	IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */

#define	IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */

#define	IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */

#define	IXGBE_VT_CTL 0x051B0

#define	IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */

#define	IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */

#define	IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */

#define	IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */

#define	IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))

#define	IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))

#define	IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))

#define	IXGBE_QDE 0x2F04

#define	IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */

#define	IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */

#define	IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))

#define	IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))

#define	IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))

#define	IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))

#define	IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /128 of these (0-127)/

#define	IXGBE_RXFECCERR0 0x051B8

#define	IXGBE_LLITHRESH 0x0EC90

#define	IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_IMIRVP 0x05AC0

#define	IXGBE_VMD_CTL 0x0581C

#define	IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */

#define	IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */

#define	IXGBE_FDIRCTRL 0x0EE00

#define	IXGBE_FDIRHKEY 0x0EE68

#define	IXGBE_FDIRSKEY 0x0EE6C

#define	IXGBE_FDIRDIP4M 0x0EE3C

#define	IXGBE_FDIRSIP4M 0x0EE40

#define	IXGBE_FDIRTCPM 0x0EE44

#define	IXGBE_FDIRUDPM 0x0EE48

#define	IXGBE_FDIRIP6M 0x0EE74

#define	IXGBE_FDIRM 0x0EE70

#define	IXGBE_FDIRFREE 0x0EE38

#define	IXGBE_FDIRLEN 0x0EE4C

#define	IXGBE_FDIRUSTAT 0x0EE50

#define	IXGBE_FDIRFSTAT 0x0EE54

#define	IXGBE_FDIRMATCH 0x0EE58

#define	IXGBE_FDIRMISS 0x0EE5C

#define	IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */

#define	IXGBE_FDIRIPSA 0x0EE18

#define	IXGBE_FDIRIPDA 0x0EE1C

#define	IXGBE_FDIRPORT 0x0EE20

#define	IXGBE_FDIRVLAN 0x0EE24

#define	IXGBE_FDIRHASH 0x0EE28

#define	IXGBE_FDIRCMD 0x0EE2C

#define	IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/

#define	IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))

#define	IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))

#define	IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))

#define	IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))

#define	IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))

#define	IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))

#define	IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))

#define	IXGBE_DTXCTL 0x07E00

#define	IXGBE_DMATXCTL 0x04A80

#define	IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */

#define	IXGBE_PFDTXGSWC 0x08220

#define	IXGBE_DTXMXSZRQ 0x08100

#define	IXGBE_DTXTCPFLGL 0x04A88

#define	IXGBE_DTXTCPFLGH 0x04A8C

#define	IXGBE_LBDRPEN 0x0CA00

#define	IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */

#define	IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */

#define	IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */

#define	IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */

#define	IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */

#define	IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */

#define	IXGBE_SPOOF_MACAS_MASK 0xFF

#define	IXGBE_SPOOF_VLANAS_MASK 0xFF00

#define	IXGBE_SPOOF_VLANAS_SHIFT 8

#define	IXGBE_PFVFSPOOF_REG_COUNT 8

#define	IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */

#define	IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))

#define	IXGBE_TIPG 0x0CB00

#define	IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */

#define	IXGBE_MNGTXMAP 0x0CD10

#define	IXGBE_TIPG_FIBER_DEFAULT 3

#define	IXGBE_TXPBSIZE_SHIFT 10

#define	IXGBE_WUC 0x05800

#define	IXGBE_WUFC 0x05808

#define	IXGBE_WUS 0x05810

#define	IXGBE_IPAV 0x05838

#define	IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */

#define	IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */

#define	IXGBE_WUPL 0x05900

#define	IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */

#define	IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */

#define	IXGBE_FHFT_EXT(_n)

#define	IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4

#define	IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2

#define	IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128

#define	IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */

#define	IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */

#define	IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */

#define	IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */

#define	IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */

#define	IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */

#define	IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */

#define	IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */

#define	IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */

#define	IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */

#define	IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */

#define	IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */

#define	IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */

#define	IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */

#define	IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */

#define	IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */

#define	IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */

#define	IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */

#define	IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */

#define	IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */

#define	IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */

#define	IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */

#define	IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */

#define	IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */

#define	IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */

#define	IXGBE_WUS_LNKC IXGBE_WUFC_LNKC

#define	IXGBE_WUS_MAG IXGBE_WUFC_MAG

#define	IXGBE_WUS_EX IXGBE_WUFC_EX

#define	IXGBE_WUS_MC IXGBE_WUFC_MC

#define	IXGBE_WUS_BC IXGBE_WUFC_BC

#define	IXGBE_WUS_ARP IXGBE_WUFC_ARP

#define	IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4

#define	IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6

#define	IXGBE_WUS_MNG IXGBE_WUFC_MNG

#define	IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0

#define	IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1

#define	IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2

#define	IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3

#define	IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4

#define	IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5

#define	IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS

#define	IXGBE_WUPL_LENGTH_MASK 0xFFFF

#define	MAX_TRAFFIC_CLASS 8

#define	X540_TRAFFIC_CLASS 4

#define	IXGBE_RMCS 0x03D00

#define	IXGBE_DPMCS 0x07F40

#define	IXGBE_PDPMCS 0x0CD00

#define	IXGBE_RUPPBMR 0x050A0

#define	IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */

#define	IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */

#define	IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_SECTXCTRL 0x08800

#define	IXGBE_SECTXSTAT 0x08804

#define	IXGBE_SECTXBUFFAF 0x08808

#define	IXGBE_SECTXMINIFG 0x08810

#define	IXGBE_SECRXCTRL 0x08D00

#define	IXGBE_SECRXSTAT 0x08D04

#define	IXGBE_SECTXCTRL_SECTX_DIS 0x00000001

#define	IXGBE_SECTXCTRL_TX_DIS 0x00000002

#define	IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004

#define	IXGBE_SECTXSTAT_SECTX_RDY 0x00000001

#define	IXGBE_SECTXSTAT_ECC_TXERR 0x00000002

#define	IXGBE_SECRXCTRL_SECRX_DIS 0x00000001

#define	IXGBE_SECRXCTRL_RX_DIS 0x00000002

#define	IXGBE_SECRXSTAT_SECRX_RDY 0x00000001

#define	IXGBE_SECRXSTAT_ECC_RXERR 0x00000002

#define	IXGBE_LSECTXCAP 0x08A00

#define	IXGBE_LSECRXCAP 0x08F00

#define	IXGBE_LSECTXCTRL 0x08A04

#define	IXGBE_LSECTXSCL 0x08A08 /* SCI Low */

#define	IXGBE_LSECTXSCH 0x08A0C /* SCI High */

#define	IXGBE_LSECTXSA 0x08A10

#define	IXGBE_LSECTXPN0 0x08A14

#define	IXGBE_LSECTXPN1 0x08A18

#define	IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */

#define	IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */

#define	IXGBE_LSECRXCTRL 0x08F04

#define	IXGBE_LSECRXSCL 0x08F08

#define	IXGBE_LSECRXSCH 0x08F0C

#define	IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */

#define	IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */

#define	IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))

#define	IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */

#define	IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */

#define	IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */

#define	IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */

#define	IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */

#define	IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */

#define	IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */

#define	IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */

#define	IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */

#define	IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */

#define	IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */

#define	IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */

#define	IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */

#define	IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */

#define	IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */

#define	IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */

#define	IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */

#define	IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */

#define	IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */

#define	IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000

#define	IXGBE_LSECTXCAP_SUM_SHIFT 16

#define	IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000

#define	IXGBE_LSECRXCAP_SUM_SHIFT 16

#define	IXGBE_LSECTXCTRL_EN_MASK 0x00000003

#define	IXGBE_LSECTXCTRL_DISABLE 0x0

#define	IXGBE_LSECTXCTRL_AUTH 0x1

#define	IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2

#define	IXGBE_LSECTXCTRL_AISCI 0x00000020

#define	IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00

#define	IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8

#define	IXGBE_LSECRXCTRL_EN_MASK 0x0000000C

#define	IXGBE_LSECRXCTRL_EN_SHIFT 2

#define	IXGBE_LSECRXCTRL_DISABLE 0x0

#define	IXGBE_LSECRXCTRL_CHECK 0x1

#define	IXGBE_LSECRXCTRL_STRICT 0x2

#define	IXGBE_LSECRXCTRL_DROP 0x3

#define	IXGBE_LSECRXCTRL_PLSH 0x00000040

#define	IXGBE_LSECRXCTRL_RP 0x00000080

#define	IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33

#define	IXGBE_IPSTXIDX 0x08900

#define	IXGBE_IPSTXSALT 0x08904

#define	IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */

#define	IXGBE_IPSRXIDX 0x08E00

#define	IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */

#define	IXGBE_IPSRXSPI 0x08E14

#define	IXGBE_IPSRXIPIDX 0x08E18

#define	IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */

#define	IXGBE_IPSRXSALT 0x08E2C

#define	IXGBE_IPSRXMOD 0x08E30

#define	IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4

#define	IXGBE_RTRPCS 0x02430

#define	IXGBE_RTTDCS 0x04900

#define	IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */

#define	IXGBE_RTTPCS 0x0CD00

#define	IXGBE_RTRUP2TC 0x03020

#define	IXGBE_RTTUP2TC 0x0C800

#define	IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */

#define	IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_RTTDQSEL 0x04904

#define	IXGBE_RTTDT1C 0x04908

#define	IXGBE_RTTDT1S 0x0490C

#define	IXGBE_RTTDTECC 0x04990

#define	IXGBE_RTTDTECC_NO_BCN 0x00000100

#define	IXGBE_RTTBCNRC 0x04984

#define	IXGBE_RTTBCNRC_RS_ENA 0x80000000

#define	IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF

#define	IXGBE_RTTBCNRC_RF_INT_SHIFT 14

#define	IXGBE_RTTBCNRC_RF_INT_MASK (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)

#define	IXGBE_RTTBCNRM 0x04980

#define	IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */

#define	IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */

#define	IXGBE_FCBUFF 0x02418 /* FC Buffer Control */

#define	IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */

#define	IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */

#define	IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))

#define	IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */

#define	IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */

#define	IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */

#define	IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */

#define	IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */

#define	IXGBE_FCBUFF_BUFFSIZE_SHIFT 3

#define	IXGBE_FCBUFF_BUFFCNT_SHIFT 8

#define	IXGBE_FCBUFF_OFFSET_SHIFT 16

#define	IXGBE_FCDMARW_WE (1 << 14) /* Write enable */

#define	IXGBE_FCDMARW_RE (1 << 15) /* Read enable */

#define	IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */

#define	IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */

#define	IXGBE_FCDMARW_LASTSIZE_SHIFT 16

#define	IXGBE_TEOFF 0x04A94 /* Tx FC EOF */

#define	IXGBE_TSOFF 0x04A98 /* Tx FC SOF */

#define	IXGBE_REOFF 0x05158 /* Rx FC EOF */

#define	IXGBE_RSOFF 0x051F8 /* Rx FC SOF */

#define	IXGBE_FCFLT 0x05108 /* FC FLT Context */

#define	IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */

#define	IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */

#define	IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */

#define	IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */

#define	IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */

#define	IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */

#define	IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */

#define	IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */

#define	IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */

#define	IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */

#define	IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */

#define	IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */

#define	IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */

#define	IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */

#define	IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */

#define	IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */

#define	IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */

#define	IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */

#define	IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */

#define	IXGBE_FCRXCTRL_FCOEVER_SHIFT 8

#define	IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */

#define	IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */

#define	IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */

#define	IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */

#define	IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */

#define	IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */

#define	IXGBE_CRCERRS 0x04000

#define	IXGBE_ILLERRC 0x04004

#define	IXGBE_ERRBC 0x04008

#define	IXGBE_MSPDC 0x04010

#define	IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/

#define	IXGBE_MLFC 0x04034

#define	IXGBE_MRFC 0x04038

#define	IXGBE_RLEC 0x04040

#define	IXGBE_LXONTXC 0x03F60

#define	IXGBE_LXONRXC 0x0CF60

#define	IXGBE_LXOFFTXC 0x03F68

#define	IXGBE_LXOFFRXC 0x0CF68

#define	IXGBE_LXONRXCNT 0x041A4

#define	IXGBE_LXOFFRXCNT 0x041A8

#define	IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */

#define	IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */

#define	IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */

#define	IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/

#define	IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/

#define	IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/

#define	IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/

#define	IXGBE_PRC64 0x0405C

#define	IXGBE_PRC127 0x04060

#define	IXGBE_PRC255 0x04064

#define	IXGBE_PRC511 0x04068

#define	IXGBE_PRC1023 0x0406C

#define	IXGBE_PRC1522 0x04070

#define	IXGBE_GPRC 0x04074

#define	IXGBE_BPRC 0x04078

#define	IXGBE_MPRC 0x0407C

#define	IXGBE_GPTC 0x04080

#define	IXGBE_GORCL 0x04088

#define	IXGBE_GORCH 0x0408C

#define	IXGBE_GOTCL 0x04090

#define	IXGBE_GOTCH 0x04094

#define	IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/

#define	IXGBE_RUC 0x040A4

#define	IXGBE_RFC 0x040A8

#define	IXGBE_ROC 0x040AC

#define	IXGBE_RJC 0x040B0

#define	IXGBE_MNGPRC 0x040B4

#define	IXGBE_MNGPDC 0x040B8

#define	IXGBE_MNGPTC 0x0CF90

#define	IXGBE_TORL 0x040C0

#define	IXGBE_TORH 0x040C4

#define	IXGBE_TPR 0x040D0

#define	IXGBE_TPT 0x040D4

#define	IXGBE_PTC64 0x040D8

#define	IXGBE_PTC127 0x040DC

#define	IXGBE_PTC255 0x040E0

#define	IXGBE_PTC511 0x040E4

#define	IXGBE_PTC1023 0x040E8

#define	IXGBE_PTC1522 0x040EC

#define	IXGBE_MPTC 0x040F0

#define	IXGBE_BPTC 0x040F4

#define	IXGBE_XEC 0x04120

#define	IXGBE_SSVPC 0x08780

#define	IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))

#define	IXGBE_TQSMR(_i)

#define	IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))

#define	IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */

#define	IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */

#define	IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */

#define	IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */

#define	IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */

#define	IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */

#define	IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */

#define	IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */

#define	IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */

#define	IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */

#define	IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */

#define	IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */

#define	IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */

#define	IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */

#define	IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */

#define	IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */

#define	IXGBE_O2BGPTC 0x041C4

#define	IXGBE_O2BSPC 0x087B0

#define	IXGBE_B2OSPC 0x041C0

#define	IXGBE_B2OGPRC 0x02F90

#define	IXGBE_PCRC8ECL 0x0E810

#define	IXGBE_PCRC8ECH 0x0E811

#define	IXGBE_PCRC8ECH_MASK 0x1F

#define	IXGBE_LDPCECL 0x0E820

#define	IXGBE_LDPCECH 0x0E821

#define	IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_MANC 0x05820

#define	IXGBE_MFVAL 0x05824

#define	IXGBE_MANC2H 0x05860

#define	IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_MIPAF 0x058B0

#define	IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */

#define	IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */

#define	IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */

#define	IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */

#define	IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */

#define	IXGBE_LSWFW 0x15014

#define	IXGBE_HICR 0x15F00

#define	IXGBE_FWSTS 0x15F0C

#define	IXGBE_HSMC0R 0x15F04

#define	IXGBE_HSMC1R 0x15F08

#define	IXGBE_SWSR 0x15F10

#define	IXGBE_HFDR 0x15FE8

#define	IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */

#define	IXGBE_HICR_EN 0x01 /* Enable bit - RO */

#define	IXGBE_HICR_C 0x02

#define	IXGBE_HICR_SV 0x04 /* Status Validity */

#define	IXGBE_HICR_FW_RESET_ENABLE 0x40

#define	IXGBE_HICR_FW_RESET 0x80

#define	IXGBE_GCR 0x11000

#define	IXGBE_GTV 0x11004

#define	IXGBE_FUNCTAG 0x11008

#define	IXGBE_GLT 0x1100C

#define	IXGBE_GSCL_1 0x11010

#define	IXGBE_GSCL_2 0x11014

#define	IXGBE_GSCL_3 0x11018

#define	IXGBE_GSCL_4 0x1101C

#define	IXGBE_GSCN_0 0x11020

#define	IXGBE_GSCN_1 0x11024

#define	IXGBE_GSCN_2 0x11028

#define	IXGBE_GSCN_3 0x1102C

#define	IXGBE_FACTPS 0x10150

#define	IXGBE_PCIEANACTL 0x11040

#define	IXGBE_SWSM 0x10140

#define	IXGBE_FWSM 0x10148

#define	IXGBE_GSSR 0x10160

#define	IXGBE_MREVID 0x11064

#define	IXGBE_DCA_ID 0x11070

#define	IXGBE_DCA_CTRL 0x11074

#define	IXGBE_SWFW_SYNC IXGBE_GSSR

#define	IXGBE_GCR_EXT 0x11050

#define	IXGBE_GSCL_5_82599 0x11030

#define	IXGBE_GSCL_6_82599 0x11034

#define	IXGBE_GSCL_7_82599 0x11038

#define	IXGBE_GSCL_8_82599 0x1103C

#define	IXGBE_PHYADR_82599 0x11040

#define	IXGBE_PHYDAT_82599 0x11044

#define	IXGBE_PHYCTL_82599 0x11048

#define	IXGBE_PBACLR_82599 0x11068

#define	IXGBE_CIAA_82599 0x11088

#define	IXGBE_CIAD_82599 0x1108C

#define	IXGBE_PICAUSE 0x110B0

#define	IXGBE_PIENA 0x110B8

#define	IXGBE_CDQ_MBR_82599 0x110B4

#define	IXGBE_PCIESPARE 0x110BC

#define	IXGBE_MISC_REG_82599 0x110F0

#define	IXGBE_ECC_CTRL_0_82599 0x11100

#define	IXGBE_ECC_CTRL_1_82599 0x11104

#define	IXGBE_ECC_STATUS_82599 0x110E0

#define	IXGBE_BAR_CTRL_82599 0x110F4

#define	IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000

#define	IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000

#define	IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000

#define	IXGBE_GCR_CAP_VER2 0x00040000

#define	IXGBE_GCR_EXT_MSIX_EN 0x80000000

#define	IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000

#define	IXGBE_GCR_EXT_VT_MODE_16 0x00000001

#define	IXGBE_GCR_EXT_VT_MODE_32 0x00000002

#define	IXGBE_GCR_EXT_VT_MODE_64 0x00000003

#define	IXGBE_GCR_EXT_SRIOV

#define	IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */

#define	IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */

#define	IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */

#define	IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */

#define	IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */

#define	IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */

#define	IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */

#define	IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */

#define	IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */

#define	IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */

#define	IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */

#define	IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */

#define	IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */

#define	IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */

#define	IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */

#define	IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */

#define	IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */

#define	IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */

#define	IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */

#define	IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */

#define	IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */

#define	IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */

#define	IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */

#define	IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */

#define	IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */

#define	IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */

#define	IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */

#define	IXGBE_RDSTATCTL 0x02C20

#define	IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */

#define	IXGBE_RDHMPN 0x02F08

#define	IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))

#define	IXGBE_RDPROBE 0x02F20

#define	IXGBE_RDMAM 0x02F30

#define	IXGBE_RDMAD 0x02F34

#define	IXGBE_TDSTATCTL 0x07C20

#define	IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */

#define	IXGBE_TDHMPN 0x07F08

#define	IXGBE_TDHMPN2 0x082FC

#define	IXGBE_TXDESCIC 0x082CC

#define	IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))

#define	IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))

#define	IXGBE_TDPROBE 0x07F20

#define	IXGBE_TXBUFCTRL 0x0C600

#define	IXGBE_TXBUFDATA0 0x0C610

#define	IXGBE_TXBUFDATA1 0x0C614

#define	IXGBE_TXBUFDATA2 0x0C618

#define	IXGBE_TXBUFDATA3 0x0C61C

#define	IXGBE_RXBUFCTRL 0x03600

#define	IXGBE_RXBUFDATA0 0x03610

#define	IXGBE_RXBUFDATA1 0x03614

#define	IXGBE_RXBUFDATA2 0x03618

#define	IXGBE_RXBUFDATA3 0x0361C

#define	IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */

#define	IXGBE_RFVAL 0x050A4

#define	IXGBE_MDFTC1 0x042B8

#define	IXGBE_MDFTC2 0x042C0

#define	IXGBE_MDFTFIFO1 0x042C4

#define	IXGBE_MDFTFIFO2 0x042C8

#define	IXGBE_MDFTS 0x042CC

#define	IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/

#define	IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/

#define	IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/

#define	IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/

#define	IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/

#define	IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/

#define	IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/

#define	IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/

#define	IXGBE_PCIEECCCTL 0x1106C

#define	IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/

#define	IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/

#define	IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/

#define	IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/

#define	IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/

#define	IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/

#define	IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/

#define	IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/

#define	IXGBE_PCIEECCCTL0 0x11100

#define	IXGBE_PCIEECCCTL1 0x11104

#define	IXGBE_RXDBUECC 0x03F70

#define	IXGBE_TXDBUECC 0x0CF70

#define	IXGBE_RXDBUEST 0x03F74

#define	IXGBE_TXDBUEST 0x0CF74

#define	IXGBE_PBTXECC 0x0C300

#define	IXGBE_PBRXECC 0x03300

#define	IXGBE_GHECCR 0x110B0

#define	IXGBE_PCS1GCFIG 0x04200

#define	IXGBE_PCS1GLCTL 0x04208

#define	IXGBE_PCS1GLSTA 0x0420C

#define	IXGBE_PCS1GDBG0 0x04210

#define	IXGBE_PCS1GDBG1 0x04214

#define	IXGBE_PCS1GANA 0x04218

#define	IXGBE_PCS1GANLP 0x0421C

#define	IXGBE_PCS1GANNP 0x04220

#define	IXGBE_PCS1GANLPNP 0x04224

#define	IXGBE_HLREG0 0x04240

#define	IXGBE_HLREG1 0x04244

#define	IXGBE_PAP 0x04248

#define	IXGBE_MACA 0x0424C

#define	IXGBE_APAE 0x04250

#define	IXGBE_ARD 0x04254

#define	IXGBE_AIS 0x04258

#define	IXGBE_MSCA 0x0425C

#define	IXGBE_MSRWD 0x04260

#define	IXGBE_MLADD 0x04264

#define	IXGBE_MHADD 0x04268

#define	IXGBE_MAXFRS 0x04268

#define	IXGBE_TREG 0x0426C

#define	IXGBE_PCSS1 0x04288

#define	IXGBE_PCSS2 0x0428C

#define	IXGBE_XPCSS 0x04290

#define	IXGBE_MFLCN 0x04294

#define	IXGBE_SERDESC 0x04298

#define	IXGBE_MACS 0x0429C

#define	IXGBE_AUTOC 0x042A0

#define	IXGBE_LINKS 0x042A4

#define	IXGBE_LINKS2 0x04324

#define	IXGBE_AUTOC2 0x042A8

#define	IXGBE_AUTOC3 0x042AC

#define	IXGBE_ANLP1 0x042B0

#define	IXGBE_ANLP2 0x042B4

#define	IXGBE_MACC 0x04330

#define	IXGBE_ATLASCTL 0x04800

#define	IXGBE_MMNGC 0x042D0

#define	IXGBE_ANLPNP1 0x042D4

#define	IXGBE_ANLPNP2 0x042D8

#define	IXGBE_KRPCSFC 0x042E0

#define	IXGBE_KRPCSS 0x042E4

#define	IXGBE_FECS1 0x042E8

#define	IXGBE_FECS2 0x042EC

#define	IXGBE_SMADARCTL 0x14F10

#define	IXGBE_MPVC 0x04318

#define	IXGBE_SGMIIC 0x04314

#define	IXGBE_RXNFGPC 0x041B0

#define	IXGBE_RXNFGBCL 0x041B4

#define	IXGBE_RXNFGBCH 0x041B8

#define	IXGBE_RXDGPC 0x02F50

#define	IXGBE_RXDGBCL 0x02F54

#define	IXGBE_RXDGBCH 0x02F58

#define	IXGBE_RXDDGPC 0x02F5C

#define	IXGBE_RXDDGBCL 0x02F60

#define	IXGBE_RXDDGBCH 0x02F64

#define	IXGBE_RXLPBKGPC 0x02F68

#define	IXGBE_RXLPBKGBCL 0x02F6C

#define	IXGBE_RXLPBKGBCH 0x02F70

#define	IXGBE_RXDLPBKGPC 0x02F74

#define	IXGBE_RXDLPBKGBCL 0x02F78

#define	IXGBE_RXDLPBKGBCH 0x02F7C

#define	IXGBE_TXDGPC 0x087A0

#define	IXGBE_TXDGBCL 0x087A4

#define	IXGBE_TXDGBCH 0x087A8

#define	IXGBE_RXDSTATCTRL 0x02F40

#define	IXGBE_VALIDATE_LINK_READY_TIMEOUT 50

#define	IXGBE_CORECTL 0x014F00

#define	IXGBE_BARCTRL 0x110F4

#define	IXGBE_BARCTRL_FLSIZE 0x0700

#define	IXGBE_BARCTRL_FLSIZE_SHIFT 8

#define	IXGBE_BARCTRL_CSRSIZE 0x2000

#define	IXGBE_RSCCTL_RSCEN 0x01

#define	IXGBE_RSCCTL_MAXDESC_1 0x00

#define	IXGBE_RSCCTL_MAXDESC_4 0x04

#define	IXGBE_RSCCTL_MAXDESC_8 0x08

#define	IXGBE_RSCCTL_MAXDESC_16 0x0C

#define	IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F

#define	IXGBE_RSCDBU_RSCACKDIS 0x00000080

#define	IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */

#define	IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */

#define	IXGBE_RDRXCTL_MVMEN 0x00000020

#define	IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */

#define	IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */

#define	IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */

#define	IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */

#define	IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */

#define	IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */

#define	IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)

#define	IXGBE_RQTC_TC0_MASK (0x7 << 0)

#define	IXGBE_RQTC_TC1_MASK (0x7 << 4)

#define	IXGBE_RQTC_TC2_MASK (0x7 << 8)

#define	IXGBE_RQTC_TC3_MASK (0x7 << 12)

#define	IXGBE_RQTC_TC4_MASK (0x7 << 16)

#define	IXGBE_RQTC_TC5_MASK (0x7 << 20)

#define	IXGBE_RQTC_TC6_MASK (0x7 << 24)

#define	IXGBE_RQTC_TC7_MASK (0x7 << 28)

#define	IXGBE_PSRTYPE_RQPL_MASK 0x7

#define	IXGBE_PSRTYPE_RQPL_SHIFT 29

#define	IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */

#define	IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */

#define	IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */

#define	IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST \| IXGBE_CTRL_RST)

#define	IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */

#define	IXGBE_MHADD_MFS_MASK 0xFFFF0000

#define	IXGBE_MHADD_MFS_SHIFT 16

#define	IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */

#define	IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */

#define	IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */

#define	IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */

#define	IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */

#define	IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */

#define	IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */

#define	IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */

#define	IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */

#define	IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */

#define	IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */

#define	IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */

#define	IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */

#define	IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */

#define	IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */

#define	IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */

#define	IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */

#define	IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */

#define	IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */

#define	IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */

#define	IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */

#define	IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */

#define	IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */

#define	IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */

#define	IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */

#define	IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */

#define	IXGBE_MSCA_NP_ADDR_SHIFT 0

#define	IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */

#define	IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */

#define	IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */

#define	IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/

#define	IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */

#define	IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */

#define	IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */

#define	IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */

#define	IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */

#define	IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/

#define	IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */

#define	IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */

#define	IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */

#define	IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */

#define	IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */

#define	IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */

#define	IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF

#define	IXGBE_MSRWD_WRITE_DATA_SHIFT 0

#define	IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000

#define	IXGBE_MSRWD_READ_DATA_SHIFT 16

#define	IXGBE_ATLAS_PDN_LPBK 0x24

#define	IXGBE_ATLAS_PDN_10G 0xB

#define	IXGBE_ATLAS_PDN_1G 0xC

#define	IXGBE_ATLAS_PDN_AN 0xD

#define	IXGBE_ATLASCTL_WRITE_CMD 0x00010000

#define	IXGBE_ATLAS_PDN_TX_REG_EN 0x10

#define	IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0

#define	IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0

#define	IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0

#define	IXGBE_CORECTL_WRITE_CMD 0x00010000

#define	IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */

#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */

#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */

#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */

#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */

#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018

#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010

#define	IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */

#define	IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */

#define	IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */

#define	IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */

#define	IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */

#define	IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/

#define	IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/

#define	IXGBE_MII_AUTONEG_REG 0x0

#define	IXGBE_PHY_REVISION_MASK 0xFFFFFFF0

#define	IXGBE_MAX_PHY_ADDR 32

#define	TN1010_PHY_ID 0x00A19410

#define	TNX_FW_REV 0xB

#define	X540_PHY_ID 0x01540200

#define	QT2022_PHY_ID 0x0043A400

#define	ATH_PHY_ID 0x03429050

#define	AQ_FW_REV 0x20

#define	IXGBE_M88E1145_E_PHY_ID 0x01410CD0

#define	IXGBE_PHY_INIT_OFFSET_NL 0x002B

#define	IXGBE_PHY_INIT_END_NL 0xFFFF

#define	IXGBE_CONTROL_MASK_NL 0xF000

#define	IXGBE_DATA_MASK_NL 0x0FFF

#define	IXGBE_CONTROL_SHIFT_NL 12

#define	IXGBE_DELAY_NL 0

#define	IXGBE_DATA_NL 1

#define	IXGBE_CONTROL_NL 0x000F

#define	IXGBE_CONTROL_EOL_NL 0x0FFF

#define	IXGBE_CONTROL_SOL_NL 0x0000

#define	IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */

#define	IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */

#define	IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */

#define	IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */

#define	IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */

#define	IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */

#define	IXGBE_GPIE_EIAME 0x40000000

#define	IXGBE_GPIE_PBA_SUPPORT 0x80000000

#define	IXGBE_GPIE_RSC_DELAY_SHIFT 11

#define	IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */

#define	IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */

#define	IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */

#define	IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */

#define	IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */

#define	IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */

#define	IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */

#define	IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */

#define	IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */

#define	IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */

#define	IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer*/

#define	IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/

#define	IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */

#define	IXGBE_MAX_PB 8

#define	PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL

#define	PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED

#define	IXGBE_TFCS_TXOFF 0x00000001

#define	IXGBE_TFCS_TXOFF0 0x00000100

#define	IXGBE_TFCS_TXOFF1 0x00000200

#define	IXGBE_TFCS_TXOFF2 0x00000400

#define	IXGBE_TFCS_TXOFF3 0x00000800

#define	IXGBE_TFCS_TXOFF4 0x00001000

#define	IXGBE_TFCS_TXOFF5 0x00002000

#define	IXGBE_TFCS_TXOFF6 0x00004000

#define	IXGBE_TFCS_TXOFF7 0x00008000

#define	IXGBE_TCPTIMER_KS 0x00000100

#define	IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200

#define	IXGBE_TCPTIMER_COUNT_FINISH 0x00000400

#define	IXGBE_TCPTIMER_LOOP 0x00000800

#define	IXGBE_TCPTIMER_DURATION_MASK 0x000000FF

#define	IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */

#define	IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */

#define	IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */

#define	IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */

#define	IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */

#define	IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */

#define	IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */

#define	IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */

#define	IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */

#define	IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */

#define	IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */

#define	IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */

#define	IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */

#define	IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */

#define	IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */

#define	IXGBE_VMD_CTL_VMDQ_EN 0x00000001

#define	IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002

#define	IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */

#define	IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */

#define	IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */

#define	IXGBE_VT_CTL_POOL_SHIFT 7

#define	IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)

#define	IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */

#define	IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */

#define	IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */

#define	IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */

#define	IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */

#define	IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF

#define	IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */

#define	IXGBE_RDHMPN_RDICADDR 0x007FF800

#define	IXGBE_RDHMPN_RDICRDREQ 0x00800000

#define	IXGBE_RDHMPN_RDICADDR_SHIFT 11

#define	IXGBE_TDHMPN_TDICADDR 0x003FF800

#define	IXGBE_TDHMPN_TDICRDREQ 0x00800000

#define	IXGBE_TDHMPN_TDICADDR_SHIFT 11

#define	IXGBE_RDMAM_MEM_SEL_SHIFT 13

#define	IXGBE_RDMAM_DWORD_SHIFT 9

#define	IXGBE_RDMAM_DESC_COMP_FIFO 1

#define	IXGBE_RDMAM_DFC_CMD_FIFO 2

#define	IXGBE_RDMAM_TCN_STATUS_RAM 4

#define	IXGBE_RDMAM_WB_COLL_FIFO 5

#define	IXGBE_RDMAM_QSC_CNT_RAM 6

#define	IXGBE_RDMAM_QSC_QUEUE_CNT 8

#define	IXGBE_RDMAM_QSC_QUEUE_RAM 0xA

#define	IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135

#define	IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4

#define	IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48

#define	IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7

#define	IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256

#define	IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9

#define	IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8

#define	IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4

#define	IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64

#define	IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4

#define	IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32

#define	IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4

#define	IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128

#define	IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8

#define	IXGBE_TXDESCIC_READY 0x80000000

#define	IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */

#define	IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */

#define	IXGBE_FCRTL_XONE 0x80000000 /* XON enable */

#define	IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */

#define	IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */

#define	IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */

#define	IXGBE_RMCS_RAC 0x00000004

#define	IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */

#define	IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */

#define	IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */

#define	IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */

#define	IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */

#define	IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */

#define	IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */

#define	IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */

#define	IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */

#define	IXGBE_EICR_PCI 0x00040000 /* PCI Exception */

#define	IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */

#define	IXGBE_EICR_LSC 0x00100000 /* Link Status Change */

#define	IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */

#define	IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */

#define	IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */

#define	IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */

#define	IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */

#define	IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */

#define	IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */

#define	IXGBE_EICR_ECC 0x10000000 /* ECC Error */

#define	IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */

#define	IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */

#define	IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */

#define	IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */

#define	IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */

#define	IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */

#define	IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */

#define	IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */

#define	IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */

#define	IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */

#define	IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */

#define	IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */

#define	IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */

#define	IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */

#define	IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */

#define	IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */

#define	IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */

#define	IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */

#define	IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */

#define	IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */

#define	IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */

#define	IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */

#define	IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */

#define	IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */

#define	IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */

#define	IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */

#define	IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */

#define	IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermel Sensor Event */

#define	IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */

#define	IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */

#define	IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */

#define	IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */

#define	IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */

#define	IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */

#define	IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */

#define	IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */

#define	IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */

#define	IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */

#define	IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */

#define	IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */

#define	IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */

#define	IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */

#define	IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */

#define	IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */

#define	IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */

#define	IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */

#define	IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */

#define	IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */

#define	IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */

#define	IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */

#define	IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */

#define	IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */

#define	IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */

#define	IXGBE_EIMS_ENABLE_MASK

#define	IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */

#define	IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */

#define	IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */

#define	IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */

#define	IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */

#define	IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */

#define	IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */

#define	IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */

#define	IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */

#define	IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */

#define	IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */

#define	IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */

#define	IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */

#define	IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */

#define	IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */

#define	IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */

#define	IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */

#define	IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */

#define	IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */

#define	IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */

#define	IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */

#define	IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */

#define	IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */

#define	IXGBE_MAX_FTQF_FILTERS 128

#define	IXGBE_FTQF_PROTOCOL_MASK 0x00000003

#define	IXGBE_FTQF_PROTOCOL_TCP 0x00000000

#define	IXGBE_FTQF_PROTOCOL_UDP 0x00000001

#define	IXGBE_FTQF_PROTOCOL_SCTP 2

#define	IXGBE_FTQF_PRIORITY_MASK 0x00000007

#define	IXGBE_FTQF_PRIORITY_SHIFT 2

#define	IXGBE_FTQF_POOL_MASK 0x0000003F

#define	IXGBE_FTQF_POOL_SHIFT 8

#define	IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F

#define	IXGBE_FTQF_5TUPLE_MASK_SHIFT 25

#define	IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E

#define	IXGBE_FTQF_DEST_ADDR_MASK 0x1D

#define	IXGBE_FTQF_SOURCE_PORT_MASK 0x1B

#define	IXGBE_FTQF_DEST_PORT_MASK 0x17

#define	IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F

#define	IXGBE_FTQF_POOL_MASK_EN 0x40000000

#define	IXGBE_FTQF_QUEUE_ENABLE 0x80000000

#define	IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF

#define	IXGBE_IVAR_REG_NUM 25

#define	IXGBE_IVAR_REG_NUM_82599 64

#define	IXGBE_IVAR_TXRX_ENTRY 96

#define	IXGBE_IVAR_RX_ENTRY 64

#define	IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))

#define	IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))

#define	IXGBE_IVAR_TX_ENTRY 32

#define	IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */

#define	IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */

#define	IXGBE_MSIX_VECTOR(_i) (0 + (_i))

#define	IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */

#define	IXGBE_MAX_ETQF_FILTERS 8

#define	IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */

#define	IXGBE_ETQF_BCN 0x10000000 /* bit 28 */

#define	IXGBE_ETQF_1588 0x40000000 /* bit 30 */

#define	IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */

#define	IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */

#define	IXGBE_ETQF_POOL_SHIFT 20

#define	IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */

#define	IXGBE_ETQS_RX_QUEUE_SHIFT 16

#define	IXGBE_ETQS_LLI 0x20000000 /* bit 29 */

#define	IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */

#define	IXGBE_ETQF_FILTER_EAPOL 0

#define	IXGBE_ETQF_FILTER_FCOE 2

#define	IXGBE_ETQF_FILTER_1588 3

#define	IXGBE_ETQF_FILTER_FIP 4

#define	IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */

#define	IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */

#define	IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */

#define	IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */

#define	IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */

#define	IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */

#define	IXGBE_VLVF_ENTRIES 64

#define	IXGBE_VLVF_VLANID_MASK 0x00000FFF

#define	IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */

#define	IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */

#define	IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */

#define	IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */

#define	IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/

#define	IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */

#define	IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */

#define	IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */

#define	IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */

#define	IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */

#define	IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */

#define	IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */

#define	IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */

#define	IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */

#define	IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */

#define	IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */

#define	IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */

#define	IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */

#define	IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 Native Function */

#define	IXGBE_LED_IVRT_BASE 0x00000040

#define	IXGBE_LED_BLINK_BASE 0x00000080

#define	IXGBE_LED_MODE_MASK_BASE 0x0000000F

#define	IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))

#define	IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))

#define	IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)

#define	IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)

#define	IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)

#define	IXGBE_LED_LINK_UP 0x0

#define	IXGBE_LED_LINK_10G 0x1

#define	IXGBE_LED_MAC 0x2

#define	IXGBE_LED_FILTER 0x3

#define	IXGBE_LED_LINK_ACTIVE 0x4

#define	IXGBE_LED_LINK_1G 0x5

#define	IXGBE_LED_ON 0xE

#define	IXGBE_LED_OFF 0xF

#define	IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000

#define	IXGBE_AUTOC_KX4_SUPP 0x80000000

#define	IXGBE_AUTOC_KX_SUPP 0x40000000

#define	IXGBE_AUTOC_PAUSE 0x30000000

#define	IXGBE_AUTOC_ASM_PAUSE 0x20000000

#define	IXGBE_AUTOC_SYM_PAUSE 0x10000000

#define	IXGBE_AUTOC_RF 0x08000000

#define	IXGBE_AUTOC_PD_TMR 0x06000000

#define	IXGBE_AUTOC_AN_RX_LOOSE 0x01000000

#define	IXGBE_AUTOC_AN_RX_DRIFT 0x00800000

#define	IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000

#define	IXGBE_AUTOC_FECA 0x00040000

#define	IXGBE_AUTOC_FECR 0x00020000

#define	IXGBE_AUTOC_KR_SUPP 0x00010000

#define	IXGBE_AUTOC_AN_RESTART 0x00001000

#define	IXGBE_AUTOC_FLU 0x00000001

#define	IXGBE_AUTOC_LMS_SHIFT 13

#define	IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)

#define	IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200

#define	IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9

#define	IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180

#define	IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7

#define	IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000

#define	IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000

#define	IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16

#define	IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)

#define	IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)

#define	IXGBE_MACC_FLU 0x00000001

#define	IXGBE_MACC_FSV_10G 0x00030000

#define	IXGBE_MACC_FS 0x00040000

#define	IXGBE_MAC_RX2TX_LPBK 0x00000002

#define	IXGBE_LINKS_KX_AN_COMP 0x80000000

#define	IXGBE_LINKS_UP 0x40000000

#define	IXGBE_LINKS_SPEED 0x20000000

#define	IXGBE_LINKS_MODE 0x18000000

#define	IXGBE_LINKS_RX_MODE 0x06000000

#define	IXGBE_LINKS_TX_MODE 0x01800000

#define	IXGBE_LINKS_XGXS_EN 0x00400000

#define	IXGBE_LINKS_SGMII_EN 0x02000000

#define	IXGBE_LINKS_PCS_1G_EN 0x00200000

#define	IXGBE_LINKS_1G_AN_EN 0x00100000

#define	IXGBE_LINKS_KX_AN_IDLE 0x00080000

#define	IXGBE_LINKS_1G_SYNC 0x00040000

#define	IXGBE_LINKS_10G_ALIGN 0x00020000

#define	IXGBE_LINKS_10G_LANE_SYNC 0x00017000

#define	IXGBE_LINKS_TL_FAULT 0x00001000

#define	IXGBE_LINKS_SIGNAL 0x00000F00

#define	IXGBE_LINKS_SPEED_82599 0x30000000

#define	IXGBE_LINKS_SPEED_10G_82599 0x30000000

#define	IXGBE_LINKS_SPEED_1G_82599 0x20000000

#define	IXGBE_LINKS_SPEED_100_82599 0x10000000

#define	IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */

#define	IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */

#define	IXGBE_LINKS2_AN_SUPPORTED 0x00000040

#define	IXGBE_PCS1GLSTA_LINK_OK 1

#define	IXGBE_PCS1GLSTA_SYNK_OK 0x10

#define	IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000

#define	IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000

#define	IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000

#define	IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000

#define	IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000

#define	IXGBE_PCS1GANA_SYM_PAUSE 0x80

#define	IXGBE_PCS1GANA_ASM_PAUSE 0x100

#define	IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */

#define	IXGBE_PCS1GLCTL_FLV_LINK_UP 1

#define	IXGBE_PCS1GLCTL_FORCE_LINK 0x20

#define	IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40

#define	IXGBE_PCS1GLCTL_AN_ENABLE 0x10000

#define	IXGBE_PCS1GLCTL_AN_RESTART 0x20000

#define	IXGBE_ANLP1_PAUSE 0x0C00

#define	IXGBE_ANLP1_SYM_PAUSE 0x0400

#define	IXGBE_ANLP1_ASM_PAUSE 0x0800

#define	IXGBE_ANLP1_AN_STATE_MASK 0x000f0000

#define	IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */

#define	IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */

#define	IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */

#define	IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */

#define	IXGBE_GSSR_EEP_SM 0x0001

#define	IXGBE_GSSR_PHY0_SM 0x0002

#define	IXGBE_GSSR_PHY1_SM 0x0004

#define	IXGBE_GSSR_MAC_CSR_SM 0x0008

#define	IXGBE_GSSR_FLASH_SM 0x0010

#define	IXGBE_GSSR_SW_MNG_SM 0x0400

#define	IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */

#define	IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */

#define	IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */

#define	IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */

#define	IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */

#define	IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */

#define	IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */

#define	IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */

#define	IXGBE_EEC_FWE_SHIFT 4

#define	IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */

#define	IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */

#define	IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */

#define	IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */

#define	IXGBE_EEC_FLUP 0x00800000 /* Flash update command */

#define	IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */

#define	IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */

#define	IXGBE_EEC_ADDR_SIZE 0x00000400

#define	IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */

#define	IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */

#define	IXGBE_EEC_SIZE_SHIFT 11

#define	IXGBE_EEPROM_WORD_SIZE_SHIFT 6

#define	IXGBE_EEPROM_OPCODE_BITS 8

#define	IXGBE_PBANUM_LENGTH 11

#define	IXGBE_PBANUM_PTR_GUARD 0xFAFA

#define	IXGBE_EEPROM_CHECKSUM 0x3F

#define	IXGBE_EEPROM_SUM 0xBABA

#define	IXGBE_PCIE_ANALOG_PTR 0x03

#define	IXGBE_ATLAS0_CONFIG_PTR 0x04

#define	IXGBE_PHY_PTR 0x04

#define	IXGBE_ATLAS1_CONFIG_PTR 0x05

#define	IXGBE_OPTION_ROM_PTR 0x05

#define	IXGBE_PCIE_GENERAL_PTR 0x06

#define	IXGBE_PCIE_CONFIG0_PTR 0x07

#define	IXGBE_PCIE_CONFIG1_PTR 0x08

#define	IXGBE_CORE0_PTR 0x09

#define	IXGBE_CORE1_PTR 0x0A

#define	IXGBE_MAC0_PTR 0x0B

#define	IXGBE_MAC1_PTR 0x0C

#define	IXGBE_CSR0_CONFIG_PTR 0x0D

#define	IXGBE_CSR1_CONFIG_PTR 0x0E

#define	IXGBE_FW_PTR 0x0F

#define	IXGBE_PBANUM0_PTR 0x15

#define	IXGBE_PBANUM1_PTR 0x16

#define	IXGBE_FREE_SPACE_PTR 0X3E

#define	IXGBE_ETS_CFG 0x26

#define	IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0

#define	IXGBE_ETS_LTHRES_DELTA_SHIFT 6

#define	IXGBE_ETS_TYPE_MASK 0x0038

#define	IXGBE_ETS_TYPE_SHIFT 3

#define	IXGBE_ETS_TYPE_EMC 0x000

#define	IXGBE_ETS_TYPE_EMC_SHIFTED 0x000

#define	IXGBE_ETS_NUM_SENSORS_MASK 0x0007

#define	IXGBE_ETS_DATA_LOC_MASK 0x3C00

#define	IXGBE_ETS_DATA_LOC_SHIFT 10

#define	IXGBE_ETS_DATA_INDEX_MASK 0x0300

#define	IXGBE_ETS_DATA_INDEX_SHIFT 8

#define	IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF

#define	IXGBE_SAN_MAC_ADDR_PTR 0x28

#define	IXGBE_DEVICE_CAPS 0x2C

#define	IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11

#define	IXGBE_PCIE_MSIX_82599_CAPS 0x72

#define	IXGBE_MAX_MSIX_VECTORS_82599 0x40

#define	IXGBE_PCIE_MSIX_82598_CAPS 0x62

#define	IXGBE_MAX_MSIX_VECTORS_82598 0x13

#define	IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF

#define	IXGBE_ISCSI_BOOT_CAPS 0x0033

#define	IXGBE_ISCSI_SETUP_PORT_0 0x0030

#define	IXGBE_ISCSI_SETUP_PORT_1 0x0034

#define	IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */

#define	IXGBE_EEPROM_STATUS_RDY_SPI 0x01

#define	IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */

#define	IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */

#define	IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */

#define	IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */

#define	IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04

#define	IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */

#define	IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */

#define	IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */

#define	IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */

#define	IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */

#define	IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */

#define	IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */

#define	IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */

#define	IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */

#define	IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */

#define	IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */

#define	IXGBE_EEPROM_PAGE_SIZE_MAX 128

#define	IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */

#define	IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */

#define	IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */

#define	IXGBE_EERD_EEWR_ATTEMPTS 100000

#define	IXGBE_FLUDONE_ATTEMPTS 20000

#define	IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */

#define	IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */

#define	IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */

#define	IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */

#define	IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0

#define	IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3

#define	IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1

#define	IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2

#define	IXGBE_FW_LESM_PARAMETERS_PTR 0x2

#define	IXGBE_FW_LESM_STATE_1 0x1

#define	IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */

#define	IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4

#define	IXGBE_FW_PATCH_VERSION_4 0x7

#define	IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */

#define	IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */

#define	IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */

#define	IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */

#define	IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */

#define	IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */

#define	IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */

#define	IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */

#define	IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */

#define	IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */

#define	IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */

#define	IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */

#define	IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */

#define	IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */

#define	IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */

#define	IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */

#define	IXGBE_PCI_DEVICE_STATUS 0xAA

#define	IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020

#define	IXGBE_PCI_LINK_STATUS 0xB2

#define	IXGBE_PCI_DEVICE_CONTROL2 0xC8

#define	IXGBE_PCI_LINK_WIDTH 0x3F0

#define	IXGBE_PCI_LINK_WIDTH_1 0x10

#define	IXGBE_PCI_LINK_WIDTH_2 0x20

#define	IXGBE_PCI_LINK_WIDTH_4 0x40

#define	IXGBE_PCI_LINK_WIDTH_8 0x80

#define	IXGBE_PCI_LINK_SPEED 0xF

#define	IXGBE_PCI_LINK_SPEED_2500 0x1

#define	IXGBE_PCI_LINK_SPEED_5000 0x2

#define	IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E

#define	IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80

#define	IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005

#define	IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800

#define	IXGBE_IS_MULTICAST(Address) (bool)(((u8 *)(Address))[0] & ((u8)0x01))

#define	IXGBE_IS_BROADCAST(Address)

#define	IXGBE_RAH_VIND_MASK 0x003C0000

#define	IXGBE_RAH_VIND_SHIFT 18

#define	IXGBE_RAH_AV 0x80000000

#define	IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF

#define	IXGBE_RFCTL_ISCSI_DIS 0x00000001

#define	IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E

#define	IXGBE_RFCTL_ISCSI_DWC_SHIFT 1

#define	IXGBE_RFCTL_NFSW_DIS 0x00000040

#define	IXGBE_RFCTL_NFSR_DIS 0x00000080

#define	IXGBE_RFCTL_NFS_VER_MASK 0x00000300

#define	IXGBE_RFCTL_NFS_VER_SHIFT 8

#define	IXGBE_RFCTL_NFS_VER_2 0

#define	IXGBE_RFCTL_NFS_VER_3 1

#define	IXGBE_RFCTL_NFS_VER_4 2

#define	IXGBE_RFCTL_IPV6_DIS 0x00000400

#define	IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800

#define	IXGBE_RFCTL_IPFRSP_DIS 0x00004000

#define	IXGBE_RFCTL_IPV6_EX_DIS 0x00010000

#define	IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000

#define	IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */

#define	IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */

#define	IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */

#define	IXGBE_TX_PAD_ENABLE 0x00000400

#define	IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */

#define	IXGBE_MAX_FRAME_SZ 0x40040000

#define	IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */

#define	IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */

#define	IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */

#define	IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */

#define	IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */

#define	IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */

#define	IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */

#define	IXGBE_RXDCTL_RLPML_EN 0x00008000

#define	IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */

#define	IXGBE_TSAUXC_EN_CLK 0x00000004

#define	IXGBE_TSAUXC_SYNCLK 0x00000008

#define	IXGBE_TSAUXC_SDP0_INT 0x00000040

#define	IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */

#define	IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */

#define	IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */

#define	IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */

#define	IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00

#define	IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02

#define	IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04

#define	IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A

#define	IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */

#define	IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF

#define	IXGBE_RXMTRL_V1_SYNC_MSG 0x00

#define	IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01

#define	IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02

#define	IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03

#define	IXGBE_RXMTRL_V1_MGMT_MSG 0x04

#define	IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00

#define	IXGBE_RXMTRL_V2_SYNC_MSG 0x0000

#define	IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100

#define	IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200

#define	IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300

#define	IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800

#define	IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900

#define	IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00

#define	IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00

#define	IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00

#define	IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00

#define	IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */

#define	IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/

#define	IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */

#define	IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */

#define	IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */

#define	IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */

#define	IXGBE_FCTRL_RPFCE 0x00004000

#define	IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */

#define	IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */

#define	IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */

#define	IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */

#define	IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */

#define	IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Receive FC Mask */

#define	IXGBE_MFLCN_RPFCE_SHIFT 4

#define	IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */

#define	IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */

#define	IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */

#define	IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */

#define	IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */

#define	IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */

#define	IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */

#define	IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */

#define	IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */

#define	IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */

#define	IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */

#define	IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000

#define	IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000

#define	IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000

#define	IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000

#define	IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000

#define	IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000

#define	IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000

#define	IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000

#define	IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000

#define	IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000

#define	IXGBE_MRQC_L3L4TXSWEN 0x00008000

#define	IXGBE_QDE_ENABLE 0x00000001

#define	IXGBE_QDE_IDX_MASK 0x00007F00

#define	IXGBE_QDE_IDX_SHIFT 8

#define	IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */

#define	IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */

#define	IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */

#define	IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */

#define	IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */

#define	IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */

#define	IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */

#define	IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */

#define	IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */

#define	IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000

#define	IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000

#define	IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000

#define	IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000

#define	IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000

#define	IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */

#define	IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */

#define	IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */

#define	IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */

#define	IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */

#define	IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */

#define	IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */

#define	IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */

#define	IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */

#define	IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */

#define	IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */

#define	IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */

#define	IXGBE_RXDADV_NEXTP_SHIFT 0x00000004

#define	IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */

#define	IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */

#define	IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */

#define	IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */

#define	IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */

#define	IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */

#define	IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */

#define	IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */

#define	IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */

#define	IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */

#define	IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */

#define	IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */

#define	IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */

#define	IXGBE_RXD_ERR_CE 0x01 /* CRC Error */

#define	IXGBE_RXD_ERR_LE 0x02 /* Length Error */

#define	IXGBE_RXD_ERR_PE 0x08 /* Packet Error */

#define	IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */

#define	IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */

#define	IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */

#define	IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */

#define	IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */

#define	IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */

#define	IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */

#define	IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */

#define	IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */

#define	IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */

#define	IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */

#define	IXGBE_RXDADV_ERR_HBO 0x00800000 /Header Buffer Overflow /

#define	IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */

#define	IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */

#define	IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */

#define	IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */

#define	IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */

#define	IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */

#define	IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */

#define	IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */

#define	IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */

#define	IXGBE_RXD_PRI_SHIFT 13

#define	IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */

#define	IXGBE_RXD_CFI_SHIFT 12

#define	IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */

#define	IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */

#define	IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */

#define	IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */

#define	IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */

#define	IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */

#define	IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */

#define	IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */

#define	IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */

#define	IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */

#define	IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */

#define	IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE 1588 Time Stamp */

#define	IXGBE_PSRTYPE_TCPHDR 0x00000010

#define	IXGBE_PSRTYPE_UDPHDR 0x00000020

#define	IXGBE_PSRTYPE_IPV4HDR 0x00000100

#define	IXGBE_PSRTYPE_IPV6HDR 0x00000200

#define	IXGBE_PSRTYPE_L2HDR 0x00001000

#define	IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */

#define	IXGBE_SRRCTL_RDMTS_SHIFT 22

#define	IXGBE_SRRCTL_RDMTS_MASK 0x01C00000

#define	IXGBE_SRRCTL_DROP_EN 0x10000000

#define	IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F

#define	IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00

#define	IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000

#define	IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000

#define	IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000

#define	IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000

#define	IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000

#define	IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000

#define	IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000

#define	IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF

#define	IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F

#define	IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0

#define	IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0

#define	IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0

#define	IXGBE_RXDADV_RSCCNT_MASK 0x001E0000

#define	IXGBE_RXDADV_RSCCNT_SHIFT 17

#define	IXGBE_RXDADV_HDRBUFLEN_SHIFT 5

#define	IXGBE_RXDADV_SPLITHEADER_EN 0x00001000

#define	IXGBE_RXDADV_SPH 0x8000

#define	IXGBE_RXDADV_RSSTYPE_NONE 0x00000000

#define	IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001

#define	IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002

#define	IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003

#define	IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004

#define	IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005

#define	IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006

#define	IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007

#define	IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008

#define	IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009

#define	IXGBE_RXDADV_PKTTYPE_NONE 0x00000000

#define	IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */

#define	IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */

#define	IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */

#define	IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */

#define	IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */

#define	IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */

#define	IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */

#define	IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */

#define	IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */

#define	IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */

#define	IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */

#define	IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */

#define	IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */

#define	IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */

#define	IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000

#define	IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000

#define	IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000

#define	IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000

#define	IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000

#define	IXGBE_RXD_ERR_FRAME_ERR_MASK

#define	IXGBE_RXDADV_ERR_FRAME_ERR_MASK

#define	IXGBE_MCSTCTRL_MFE 0x4

#define	IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8

#define	IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8

#define	IXGBE_REQ_TX_BUFFER_GRANULARITY 1024

#define	IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */

#define	IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */

#define	IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */

#define	IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT

#define	IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)

#define	IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4))

#define	IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600))

#define	IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4))

#define	IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16

#define	IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001

#define	IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002

#define	IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003

#define	IXGBE_FDIRCTRL_INIT_DONE 0x00000008

#define	IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010

#define	IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020

#define	IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080

#define	IXGBE_FDIRCTRL_DROP_Q_SHIFT 8

#define	IXGBE_FDIRCTRL_FLEX_SHIFT 16

#define	IXGBE_FDIRCTRL_SEARCHLIM 0x00800000

#define	IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24

#define	IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000

#define	IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28

#define	IXGBE_FDIRTCPM_DPORTM_SHIFT 16

#define	IXGBE_FDIRUDPM_DPORTM_SHIFT 16

#define	IXGBE_FDIRIP6M_DIPM_SHIFT 16

#define	IXGBE_FDIRM_VLANID 0x00000001

#define	IXGBE_FDIRM_VLANP 0x00000002

#define	IXGBE_FDIRM_POOL 0x00000004

#define	IXGBE_FDIRM_L4P 0x00000008

#define	IXGBE_FDIRM_FLEX 0x00000010

#define	IXGBE_FDIRM_DIPv6 0x00000020

#define	IXGBE_FDIRFREE_FREE_MASK 0xFFFF

#define	IXGBE_FDIRFREE_FREE_SHIFT 0

#define	IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000

#define	IXGBE_FDIRFREE_COLL_SHIFT 16

#define	IXGBE_FDIRLEN_MAXLEN_MASK 0x3F

#define	IXGBE_FDIRLEN_MAXLEN_SHIFT 0

#define	IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000

#define	IXGBE_FDIRLEN_MAXHASH_SHIFT 16

#define	IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF

#define	IXGBE_FDIRUSTAT_ADD_SHIFT 0

#define	IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000

#define	IXGBE_FDIRUSTAT_REMOVE_SHIFT 16

#define	IXGBE_FDIRFSTAT_FADD_MASK 0x00FF

#define	IXGBE_FDIRFSTAT_FADD_SHIFT 0

#define	IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00

#define	IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8

#define	IXGBE_FDIRPORT_DESTINATION_SHIFT 16

#define	IXGBE_FDIRVLAN_FLEX_SHIFT 16

#define	IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15

#define	IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16

#define	IXGBE_FDIRCMD_CMD_MASK 0x00000003

#define	IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001

#define	IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002

#define	IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003

#define	IXGBE_FDIRCMD_FILTER_VALID 0x00000004

#define	IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008

#define	IXGBE_FDIRCMD_IPv6DMATCH 0x00000010

#define	IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020

#define	IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040

#define	IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060

#define	IXGBE_FDIRCMD_IPV6 0x00000080

#define	IXGBE_FDIRCMD_CLEARHT 0x00000100

#define	IXGBE_FDIRCMD_DROP 0x00000200

#define	IXGBE_FDIRCMD_INT 0x00000400

#define	IXGBE_FDIRCMD_LAST 0x00000800

#define	IXGBE_FDIRCMD_COLLISION 0x00001000

#define	IXGBE_FDIRCMD_QUEUE_EN 0x00008000

#define	IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5

#define	IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16

#define	IXGBE_FDIRCMD_VT_POOL_SHIFT 24

#define	IXGBE_FDIR_INIT_DONE_POLL 10

#define	IXGBE_FDIRCMD_CMD_POLL 10

#define	IXGBE_FDIR_DROP_QUEUE 127

#define	IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */

#define	IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */

#define	IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */

#define	FW_CEM_HDR_LEN 0x4

#define	FW_CEM_CMD_DRIVER_INFO 0xDD

#define	FW_CEM_CMD_DRIVER_INFO_LEN 0x5

#define	FW_CEM_CMD_RESERVED 0x0

#define	FW_CEM_UNUSED_VER 0x0

#define	FW_CEM_MAX_RETRIES 3

#define	FW_CEM_RESP_STATUS_SUCCESS 0x1

#define	IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */

#define	IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */

#define	IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE 1588 Time Stamp */

#define	IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */

#define	IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */

#define	IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */

#define	IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */

#define	IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */

#define	IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */

#define	IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */

#define	IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */

#define	IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */

#define	IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */

#define	IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */

#define	IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */

#define	IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */

#define	IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */

#define	IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */

#define	IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */

#define	IXGBE_ADVTXD_CC 0x00000080 /* Check Context */

#define	IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */

#define	IXGBE_ADVTXD_POPTS_IXSM

#define	IXGBE_ADVTXD_POPTS_TXSM

#define	IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */

#define	IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */

#define	IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */

#define	IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */

#define	IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */

#define	IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */

#define	IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */

#define	IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */

#define	IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */

#define	IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */

#define	IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */

#define	IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */

#define	IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */

#define	IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /Req requires Markers and CRC/

#define	IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */

#define	IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */

#define	IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */

#define	IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */

#define	IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */

#define	IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */

#define	IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */

#define	IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */

#define	IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */

#define	IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */

#define	IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */

#define	IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */

#define	IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */

#define	IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */

#define	IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */

#define	IXGBE_LINK_SPEED_UNKNOWN 0

#define	IXGBE_LINK_SPEED_100_FULL 0x0008

#define	IXGBE_LINK_SPEED_1GB_FULL 0x0020

#define	IXGBE_LINK_SPEED_10GB_FULL 0x0080

#define	IXGBE_LINK_SPEED_82598_AUTONEG

#define	IXGBE_LINK_SPEED_82599_AUTONEG

#define	IXGBE_PHYSICAL_LAYER_UNKNOWN 0

#define	IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001

#define	IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002

#define	IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004

#define	IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008

#define	IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010

#define	IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020

#define	IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040

#define	IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080

#define	IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100

#define	IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200

#define	IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400

#define	IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800

#define	IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000

#define	IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000

#define	IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))

#define	IXGBE_B2BT(BT) (BT * 8)

#define	IXGBE_PFC_D 672

#define	IXGBE_CABLE_DC 5556 /* Delay Copper */

#define	IXGBE_CABLE_DO 5000 /* Delay Optical */

#define	IXGBE_PHY_DC 25600 /* Delay 10G BASET */

#define	IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */

#define	IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */

#define	IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)

#define	IXGBE_PHY_D 12800

#define	IXGBE_MAC_D 4096

#define	IXGBE_XAUI_D (2 * 1024)

#define	IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)

#define	IXGBE_HD 6144

#define	IXGBE_PCI_DELAY 10000

#define	IXGBE_DV_X540(_max_frame_link, _max_frame_tc)

#define	IXGBE_DV(_max_frame_link, _max_frame_tc)

#define	IXGBE_LOW_DV_X540(_max_frame_tc)

#define	IXGBE_LOW_DV(_max_frame_tc) (2 * IXGBE_LOW_DV_X540(_max_frame_tc))

#define	IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2

#define	IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614

#define	IXGBE_ATR_HASH_MASK 0x7fff

#define	IXGBE_ATR_L4TYPE_MASK 0x3

#define	IXGBE_ATR_L4TYPE_UDP 0x1

#define	IXGBE_ATR_L4TYPE_TCP 0x2

#define	IXGBE_ATR_L4TYPE_SCTP 0x3

#define	IXGBE_ATR_L4TYPE_IPV6_MASK 0x4

#define	IXGBE_SMARTSPEED_MAX_RETRIES 3

#define	IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01

#define	IXGBE_MAX_MTA 128

#define	IXGBE_ERR_EEPROM -1

#define	IXGBE_ERR_EEPROM_CHECKSUM -2

#define	IXGBE_ERR_PHY -3

#define	IXGBE_ERR_CONFIG -4

#define	IXGBE_ERR_PARAM -5

#define	IXGBE_ERR_MAC_TYPE -6

#define	IXGBE_ERR_UNKNOWN_PHY -7

#define	IXGBE_ERR_LINK_SETUP -8

#define	IXGBE_ERR_ADAPTER_STOPPED -9

#define	IXGBE_ERR_INVALID_MAC_ADDR -10

#define	IXGBE_ERR_DEVICE_NOT_SUPPORTED -11

#define	IXGBE_ERR_MASTER_REQUESTS_PENDING -12

#define	IXGBE_ERR_INVALID_LINK_SETTINGS -13

#define	IXGBE_ERR_AUTONEG_NOT_COMPLETE -14

#define	IXGBE_ERR_RESET_FAILED -15

#define	IXGBE_ERR_SWFW_SYNC -16

#define	IXGBE_ERR_PHY_ADDR_INVALID -17

#define	IXGBE_ERR_I2C -18

#define	IXGBE_ERR_SFP_NOT_SUPPORTED -19

#define	IXGBE_ERR_SFP_NOT_PRESENT -20

#define	IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21

#define	IXGBE_ERR_NO_SAN_ADDR_PTR -22

#define	IXGBE_ERR_FDIR_REINIT_FAILED -23

#define	IXGBE_ERR_EEPROM_VERSION -24

#define	IXGBE_ERR_NO_SPACE -25

#define	IXGBE_ERR_OVERTEMP -26

#define	IXGBE_ERR_FC_NOT_NEGOTIATED -27

#define	IXGBE_ERR_FC_NOT_SUPPORTED -28

#define	IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30

#define	IXGBE_ERR_PBA_SECTION -31

#define	IXGBE_ERR_INVALID_ARGUMENT -32

#define	IXGBE_ERR_HOST_INTERFACE_COMMAND -33

#define	IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF

Typedefs
typedef u32	ixgbe_autoneg_advertised

typedef u32	ixgbe_link_speed

typedef u32	ixgbe_physical_layer

typedef u8 (	ixgbe_mc_addr_itr )(struct ixgbe_hw hw, u8 mc_addr_ptr, u32 vmdq)

Enumerations
enum	{ PBA_STRATEGY_EQUAL = 0, PBA_STRATEGY_EQUAL = 0, PBA_STRATEGY_WEIGHTED = 1, PBA_STRATEGY_WEIGHTED = 1 }

enum	ixgbe_fdir_pballoc_type { IXGBE_FDIR_PBALLOC_NONE = 0, IXGBE_FDIR_PBALLOC_64K = 1, IXGBE_FDIR_PBALLOC_128K = 2, IXGBE_FDIR_PBALLOC_256K = 3 }

enum	ixgbe_atr_flow_type { IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7 }

enum	ixgbe_eeprom_type { ixgbe_eeprom_uninitialized = 0, ixgbe_eeprom_spi, ixgbe_flash, ixgbe_eeprom_none }

enum	ixgbe_mac_type { ixgbe_mac_unknown = 0, ixgbe_mac_82598EB, ixgbe_mac_82599EB, ixgbe_mac_X540, ixgbe_num_macs, ixgbe_mac_unknown = 0, ixgbe_mac_82599_vf, ixgbe_mac_X540_vf, ixgbe_num_macs }

enum	ixgbe_phy_type { ixgbe_phy_unknown = 0, ixgbe_phy_none, ixgbe_phy_tn, ixgbe_phy_aq, ixgbe_phy_cu_unknown, ixgbe_phy_qt, ixgbe_phy_xaui, ixgbe_phy_nl, ixgbe_phy_sfp_passive_tyco, ixgbe_phy_sfp_passive_unknown, ixgbe_phy_sfp_active_unknown, ixgbe_phy_sfp_avago, ixgbe_phy_sfp_ftl, ixgbe_phy_sfp_ftl_active, ixgbe_phy_sfp_unknown, ixgbe_phy_sfp_intel, ixgbe_phy_sfp_unsupported, ixgbe_phy_generic }

enum	ixgbe_sfp_type { ixgbe_sfp_type_da_cu = 0, ixgbe_sfp_type_sr = 1, ixgbe_sfp_type_lr = 2, ixgbe_sfp_type_da_cu_core0 = 3, ixgbe_sfp_type_da_cu_core1 = 4, ixgbe_sfp_type_srlr_core0 = 5, ixgbe_sfp_type_srlr_core1 = 6, ixgbe_sfp_type_da_act_lmt_core0 = 7, ixgbe_sfp_type_da_act_lmt_core1 = 8, ixgbe_sfp_type_1g_cu_core0 = 9, ixgbe_sfp_type_1g_cu_core1 = 10, ixgbe_sfp_type_1g_sx_core0 = 11, ixgbe_sfp_type_1g_sx_core1 = 12, ixgbe_sfp_type_not_present = 0xFFFE, ixgbe_sfp_type_unknown = 0xFFFF }

enum	ixgbe_media_type { ixgbe_media_type_unknown = 0, ixgbe_media_type_fiber, ixgbe_media_type_fiber_lco, ixgbe_media_type_copper, ixgbe_media_type_backplane, ixgbe_media_type_cx4, ixgbe_media_type_virtual }

enum	ixgbe_fc_mode { ixgbe_fc_none = 0, ixgbe_fc_rx_pause, ixgbe_fc_tx_pause, ixgbe_fc_full, ixgbe_fc_default }

enum	ixgbe_smart_speed { ixgbe_smart_speed_auto = 0, ixgbe_smart_speed_on, ixgbe_smart_speed_off }

enum	ixgbe_bus_type { ixgbe_bus_type_unknown = 0, ixgbe_bus_type_pci, ixgbe_bus_type_pcix, ixgbe_bus_type_pci_express, ixgbe_bus_type_reserved }

enum	ixgbe_bus_speed { ixgbe_bus_speed_unknown = 0, ixgbe_bus_speed_33 = 33, ixgbe_bus_speed_66 = 66, ixgbe_bus_speed_100 = 100, ixgbe_bus_speed_120 = 120, ixgbe_bus_speed_133 = 133, ixgbe_bus_speed_2500 = 2500, ixgbe_bus_speed_5000 = 5000, ixgbe_bus_speed_reserved }

enum	ixgbe_bus_width { ixgbe_bus_width_unknown = 0, ixgbe_bus_width_pcie_x1 = 1, ixgbe_bus_width_pcie_x2 = 2, ixgbe_bus_width_pcie_x4 = 4, ixgbe_bus_width_pcie_x8 = 8, ixgbe_bus_width_32 = 32, ixgbe_bus_width_64 = 64, ixgbe_bus_width_reserved }

Macro Definition Documentation

#define AQ_FW_REV 0x20

Definition at line 1131 of file ixgbe_type.h.

#define ATH_PHY_ID 0x03429050

Definition at line 1130 of file ixgbe_type.h.

#define FW_CEM_CMD_DRIVER_INFO 0xDD

Definition at line 2245 of file ixgbe_type.h.

#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5

Definition at line 2246 of file ixgbe_type.h.

#define FW_CEM_CMD_RESERVED 0x0

Definition at line 2247 of file ixgbe_type.h.

#define FW_CEM_HDR_LEN 0x4

Definition at line 2244 of file ixgbe_type.h.

#define FW_CEM_MAX_RETRIES 3

Definition at line 2249 of file ixgbe_type.h.

#define FW_CEM_RESP_STATUS_SUCCESS 0x1

Definition at line 2250 of file ixgbe_type.h.

#define FW_CEM_UNUSED_VER 0x0

Definition at line 2248 of file ixgbe_type.h.

#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */

Definition at line 2347 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */

Definition at line 2339 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */

Definition at line 2340 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */

Definition at line 2336 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */

Definition at line 2337 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */

Definition at line 2338 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */

Definition at line 2342 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */

Definition at line 2341 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */

Definition at line 2328 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */

Definition at line 2334 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */

Definition at line 2335 of file ixgbe_type.h.

#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */

Definition at line 2333 of file ixgbe_type.h.

#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */

Definition at line 2379 of file ixgbe_type.h.

#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */

Definition at line 2371 of file ixgbe_type.h.

#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */

Definition at line 2376 of file ixgbe_type.h.

#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */

Definition at line 2378 of file ixgbe_type.h.

#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */

Definition at line 2377 of file ixgbe_type.h.

#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */

Definition at line 2374 of file ixgbe_type.h.

#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */

Definition at line 2375 of file ixgbe_type.h.

#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */

Definition at line 2373 of file ixgbe_type.h.

#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */

Definition at line 2372 of file ixgbe_type.h.

#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */

Definition at line 2346 of file ixgbe_type.h.

#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */

Definition at line 2332 of file ixgbe_type.h.

#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */

Definition at line 2331 of file ixgbe_type.h.

#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */

Definition at line 2380 of file ixgbe_type.h.

#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */

Definition at line 2329 of file ixgbe_type.h.

#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE 1588 Time Stamp */

Definition at line 2330 of file ixgbe_type.h.

#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */

Definition at line 2359 of file ixgbe_type.h.

#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */

Definition at line 2381 of file ixgbe_type.h.

#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */

Definition at line 2358 of file ixgbe_type.h.

#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */

Definition at line 2367 of file ixgbe_type.h.

#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */

Definition at line 2353 of file ixgbe_type.h.

#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */

Definition at line 2356 of file ixgbe_type.h.

#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */

Definition at line 2355 of file ixgbe_type.h.

#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */

Definition at line 2354 of file ixgbe_type.h.

#define IXGBE_ADVTXD_POPTS_IXSM

Value:

(IXGBE_TXD_POPTS_IXSM << \

IXGBE_ADVTXD_POPTS_SHIFT)

Definition at line 2349 of file ixgbe_type.h.

#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */

Definition at line 2357 of file ixgbe_type.h.

#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */

Definition at line 2348 of file ixgbe_type.h.

#define IXGBE_ADVTXD_POPTS_TXSM

Value:

(IXGBE_TXD_POPTS_TXSM << \

IXGBE_ADVTXD_POPTS_SHIFT)

Definition at line 2351 of file ixgbe_type.h.

#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */

Definition at line 2343 of file ixgbe_type.h.

#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */

Definition at line 2345 of file ixgbe_type.h.

#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */

Definition at line 2344 of file ixgbe_type.h.

#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */

Definition at line 2369 of file ixgbe_type.h.

#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */

Definition at line 2368 of file ixgbe_type.h.

#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */

Definition at line 2361 of file ixgbe_type.h.

#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */

Definition at line 2362 of file ixgbe_type.h.

#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */

Definition at line 2365 of file ixgbe_type.h.

#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */

Definition at line 2364 of file ixgbe_type.h.

#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */

Definition at line 2363 of file ixgbe_type.h.

#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/

Definition at line 2366 of file ixgbe_type.h.

#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */

Definition at line 2360 of file ixgbe_type.h.

#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */

Definition at line 2370 of file ixgbe_type.h.

#define IXGBE_AIS 0x04258

Definition at line 910 of file ixgbe_type.h.

#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */

Definition at line 1802 of file ixgbe_type.h.

#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */

Definition at line 1809 of file ixgbe_type.h.

#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */

Definition at line 1803 of file ixgbe_type.h.

#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */

Definition at line 1808 of file ixgbe_type.h.

#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */

Definition at line 1804 of file ixgbe_type.h.

#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */

Definition at line 1805 of file ixgbe_type.h.

#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */

Definition at line 1806 of file ixgbe_type.h.

#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */

Definition at line 1807 of file ixgbe_type.h.

#define IXGBE_ANLP1 0x042B0

Definition at line 928 of file ixgbe_type.h.

#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000

Definition at line 1640 of file ixgbe_type.h.

#define IXGBE_ANLP1_ASM_PAUSE 0x0800

Definition at line 1639 of file ixgbe_type.h.

#define IXGBE_ANLP1_PAUSE 0x0C00

Definition at line 1637 of file ixgbe_type.h.

#define IXGBE_ANLP1_SYM_PAUSE 0x0400

Definition at line 1638 of file ixgbe_type.h.

#define IXGBE_ANLP2 0x042B4

Definition at line 929 of file ixgbe_type.h.

#define IXGBE_ANLPNP1 0x042D4

Definition at line 933 of file ixgbe_type.h.

#define IXGBE_ANLPNP2 0x042D8

Definition at line 934 of file ixgbe_type.h.

#define IXGBE_APAE 0x04250

Definition at line 908 of file ixgbe_type.h.

#define IXGBE_ARD 0x04254

Definition at line 909 of file ixgbe_type.h.

#define IXGBE_ATLAS0_CONFIG_PTR 0x04

Definition at line 1692 of file ixgbe_type.h.

#define IXGBE_ATLAS1_CONFIG_PTR 0x05

Definition at line 1694 of file ixgbe_type.h.

#define IXGBE_ATLAS_PDN_10G 0xB

Definition at line 1086 of file ixgbe_type.h.

#define IXGBE_ATLAS_PDN_1G 0xC

Definition at line 1087 of file ixgbe_type.h.

#define IXGBE_ATLAS_PDN_AN 0xD

Definition at line 1088 of file ixgbe_type.h.

#define IXGBE_ATLAS_PDN_LPBK 0x24

Definition at line 1085 of file ixgbe_type.h.

#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0

Definition at line 1093 of file ixgbe_type.h.

#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0

Definition at line 1094 of file ixgbe_type.h.

#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0

Definition at line 1095 of file ixgbe_type.h.

#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10

Definition at line 1092 of file ixgbe_type.h.

#define IXGBE_ATLASCTL 0x04800

Definition at line 931 of file ixgbe_type.h.

#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000

Definition at line 1091 of file ixgbe_type.h.

#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2

Definition at line 2479 of file ixgbe_type.h.

#define IXGBE_ATR_HASH_MASK 0x7fff

Definition at line 2483 of file ixgbe_type.h.

#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4

Definition at line 2488 of file ixgbe_type.h.

#define IXGBE_ATR_L4TYPE_MASK 0x3

Definition at line 2484 of file ixgbe_type.h.

#define IXGBE_ATR_L4TYPE_SCTP 0x3

Definition at line 2487 of file ixgbe_type.h.

#define IXGBE_ATR_L4TYPE_TCP 0x2

Definition at line 2486 of file ixgbe_type.h.

#define IXGBE_ATR_L4TYPE_UDP 0x1

Definition at line 2485 of file ixgbe_type.h.

#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614

Definition at line 2480 of file ixgbe_type.h.

#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */

Definition at line 1612 of file ixgbe_type.h.

#define IXGBE_AUTOC 0x042A0

Definition at line 923 of file ixgbe_type.h.

#define IXGBE_AUTOC2 0x042A8

Definition at line 926 of file ixgbe_type.h.

#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)

Definition at line 1580 of file ixgbe_type.h.

#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000

Definition at line 1578 of file ixgbe_type.h.

#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16

Definition at line 1579 of file ixgbe_type.h.

#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)

Definition at line 1582 of file ixgbe_type.h.

#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)

Definition at line 1581 of file ixgbe_type.h.

#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000

Definition at line 1577 of file ixgbe_type.h.

#define IXGBE_AUTOC3 0x042AC

Definition at line 927 of file ixgbe_type.h.

#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)

Definition at line 1571 of file ixgbe_type.h.

#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)

Definition at line 1570 of file ixgbe_type.h.

#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180

Definition at line 1567 of file ixgbe_type.h.

#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7

Definition at line 1568 of file ixgbe_type.h.

#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)

Definition at line 1569 of file ixgbe_type.h.

#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)

Definition at line 1572 of file ixgbe_type.h.

#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)

Definition at line 1573 of file ixgbe_type.h.

#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)

Definition at line 1575 of file ixgbe_type.h.

#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200

Definition at line 1565 of file ixgbe_type.h.

#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9

Definition at line 1566 of file ixgbe_type.h.

#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)

Definition at line 1574 of file ixgbe_type.h.

#define IXGBE_AUTOC_AN_RESTART 0x00001000

Definition at line 1549 of file ixgbe_type.h.

#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000

Definition at line 1545 of file ixgbe_type.h.

#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000

Definition at line 1544 of file ixgbe_type.h.

#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000

Definition at line 1543 of file ixgbe_type.h.

#define IXGBE_AUTOC_ASM_PAUSE 0x20000000

Definition at line 1539 of file ixgbe_type.h.

#define IXGBE_AUTOC_FECA 0x00040000

Definition at line 1546 of file ixgbe_type.h.

#define IXGBE_AUTOC_FECR 0x00020000

Definition at line 1547 of file ixgbe_type.h.

#define IXGBE_AUTOC_FLU 0x00000001

Definition at line 1550 of file ixgbe_type.h.

#define IXGBE_AUTOC_KR_SUPP 0x00010000

Definition at line 1548 of file ixgbe_type.h.

#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000

Definition at line 1535 of file ixgbe_type.h.

#define IXGBE_AUTOC_KX4_SUPP 0x80000000

Definition at line 1536 of file ixgbe_type.h.

#define IXGBE_AUTOC_KX_SUPP 0x40000000

Definition at line 1537 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1559 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1552 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1560 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1558 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)

Definition at line 1563 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1561 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1562 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1553 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1555 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1556 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1557 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)

Definition at line 1554 of file ixgbe_type.h.

#define IXGBE_AUTOC_LMS_SHIFT 13

Definition at line 1551 of file ixgbe_type.h.

#define IXGBE_AUTOC_PAUSE 0x30000000

Definition at line 1538 of file ixgbe_type.h.

#define IXGBE_AUTOC_PD_TMR 0x06000000

Definition at line 1542 of file ixgbe_type.h.

#define IXGBE_AUTOC_RF 0x08000000

Definition at line 1541 of file ixgbe_type.h.

#define IXGBE_AUTOC_SYM_PAUSE 0x10000000

Definition at line 1540 of file ixgbe_type.h.

#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */

Definition at line 830 of file ixgbe_type.h.

#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */

Definition at line 832 of file ixgbe_type.h.

#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */

Definition at line 829 of file ixgbe_type.h.

#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */

Definition at line 831 of file ixgbe_type.h.

#define IXGBE_B2BT ( BT ) (BT * 8)

Definition at line 2422 of file ixgbe_type.h.

#define IXGBE_B2OGPRC 0x02F90

Definition at line 708 of file ixgbe_type.h.

#define IXGBE_B2OSPC 0x041C0

Definition at line 707 of file ixgbe_type.h.

#define IXGBE_BAR_CTRL_82599 0x110F4

Definition at line 789 of file ixgbe_type.h.

#define IXGBE_BARCTRL 0x110F4

Definition at line 971 of file ixgbe_type.h.

#define IXGBE_BARCTRL_CSRSIZE 0x2000

Definition at line 974 of file ixgbe_type.h.

#define IXGBE_BARCTRL_FLSIZE 0x0700

Definition at line 972 of file ixgbe_type.h.

#define IXGBE_BARCTRL_FLSIZE_SHIFT 8

Definition at line 973 of file ixgbe_type.h.

#define IXGBE_BPRC 0x04078

Definition at line 654 of file ixgbe_type.h.

#define IXGBE_BPTC 0x040F4

Definition at line 680 of file ixgbe_type.h.

#define IXGBE_BT2KB ( BT ) ((BT + (8 * 1024 - 1)) / (8 * 1024))

Definition at line 2421 of file ixgbe_type.h.

#define IXGBE_CABLE_DC 5556 /* Delay Copper */

Definition at line 2428 of file ixgbe_type.h.

#define IXGBE_CABLE_DO 5000 /* Delay Optical */

Definition at line 2429 of file ixgbe_type.h.

#define IXGBE_CDQ_MBR_82599 0x110B4

Definition at line 783 of file ixgbe_type.h.

#define IXGBE_CIAA_82599 0x11088

Definition at line 779 of file ixgbe_type.h.

#define IXGBE_CIAD_82599 0x1108C

Definition at line 780 of file ixgbe_type.h.

#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF

Definition at line 1848 of file ixgbe_type.h.

#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */

Definition at line 826 of file ixgbe_type.h.

#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */

Definition at line 825 of file ixgbe_type.h.

#define IXGBE_CONTROL_EOL_NL 0x0FFF

Definition at line 1145 of file ixgbe_type.h.

#define IXGBE_CONTROL_MASK_NL 0xF000

Definition at line 1139 of file ixgbe_type.h.

#define IXGBE_CONTROL_NL 0x000F

Definition at line 1144 of file ixgbe_type.h.

#define IXGBE_CONTROL_SHIFT_NL 12

Definition at line 1141 of file ixgbe_type.h.

#define IXGBE_CONTROL_SOL_NL 0x0000

Definition at line 1146 of file ixgbe_type.h.

#define IXGBE_CORE0_PTR 0x09

Definition at line 1699 of file ixgbe_type.h.

#define IXGBE_CORE1_PTR 0x0A

Definition at line 1700 of file ixgbe_type.h.

#define IXGBE_CORECTL 0x014F00

Definition at line 969 of file ixgbe_type.h.

#define IXGBE_CORECTL_WRITE_CMD 0x00010000

Definition at line 1098 of file ixgbe_type.h.

#define IXGBE_CORESPARE 0x00600

Definition at line 84 of file ixgbe_type.h.

#define IXGBE_CRCERRS 0x04000

Definition at line 626 of file ixgbe_type.h.

#define IXGBE_CSR0_CONFIG_PTR 0x0D

Definition at line 1703 of file ixgbe_type.h.

#define IXGBE_CSR1_CONFIG_PTR 0x0E

Definition at line 1704 of file ixgbe_type.h.

#define IXGBE_CTRL 0x00000

Definition at line 75 of file ixgbe_type.h.

#define IXGBE_CTRL_EXT 0x00018

Definition at line 77 of file ixgbe_type.h.

#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */

Definition at line 1030 of file ixgbe_type.h.

#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */

Definition at line 1028 of file ixgbe_type.h.

#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */

Definition at line 1027 of file ixgbe_type.h.

#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */

Definition at line 1029 of file ixgbe_type.h.

#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */

Definition at line 1014 of file ixgbe_type.h.

#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */

Definition at line 1015 of file ixgbe_type.h.

#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */

Definition at line 1016 of file ixgbe_type.h.

#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)

Definition at line 1017 of file ixgbe_type.h.

#define IXGBE_DAQF ( _i ) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */

Definition at line 252 of file ixgbe_type.h.

#define IXGBE_DATA_MASK_NL 0x0FFF

Definition at line 1140 of file ixgbe_type.h.

#define IXGBE_DATA_NL 1

Definition at line 1143 of file ixgbe_type.h.

#define IXGBE_DCA_CTRL 0x11074

Definition at line 766 of file ixgbe_type.h.

#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */

Definition at line 1034 of file ixgbe_type.h.

#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */

Definition at line 1033 of file ixgbe_type.h.

#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */

Definition at line 1036 of file ixgbe_type.h.

#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */

Definition at line 1037 of file ixgbe_type.h.

#define IXGBE_DCA_ID 0x11070

Definition at line 765 of file ixgbe_type.h.

#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */

Definition at line 1056 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL ( _i )

Value:

(((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
                                 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
                 (0x0D00C + (((_i) - 64) * 0x40))))

Definition at line 217 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */

Definition at line 1039 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */

Definition at line 1040 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */

Definition at line 1041 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */

Definition at line 1044 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */

Definition at line 1046 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */

Definition at line 1042 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */

Definition at line 1045 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */

Definition at line 1043 of file ixgbe_type.h.

#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */

Definition at line 1047 of file ixgbe_type.h.

#define IXGBE_DCA_TXCTRL ( _i ) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */

Definition at line 349 of file ixgbe_type.h.

#define IXGBE_DCA_TXCTRL_82599 ( _i ) (0x0600C + ((_i) * 0x40))

Definition at line 351 of file ixgbe_type.h.

#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */

Definition at line 1049 of file ixgbe_type.h.

#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */

Definition at line 1050 of file ixgbe_type.h.

#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */

Definition at line 1051 of file ixgbe_type.h.

#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */

Definition at line 1055 of file ixgbe_type.h.

#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */

Definition at line 1052 of file ixgbe_type.h.

#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */

Definition at line 1053 of file ixgbe_type.h.

#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */

Definition at line 1054 of file ixgbe_type.h.

#define IXGBE_DELAY_NL 0

Definition at line 1142 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598 0x10B6

Definition at line 36 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598_BX 0x1508

Definition at line 37 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC

Definition at line 44 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1

Definition at line 45 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1

Definition at line 46 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6

Definition at line 38 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7

Definition at line 39 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598AT 0x10C8

Definition at line 41 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598AT2 0x150B

Definition at line 42 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598EB_CX4 0x10DD

Definition at line 43 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB

Definition at line 40 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4

Definition at line 47 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a

Definition at line 54 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8

Definition at line 63 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_CX4 0x10F9

Definition at line 52 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_KR 0x1517

Definition at line 50 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_KX4 0x10F7

Definition at line 48 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514

Definition at line 49 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_LS 0x154F

Definition at line 65 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_SFP 0x10FB

Definition at line 53 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_SFP_EM 0x1507

Definition at line 59 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529

Definition at line 55 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D

Definition at line 60 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A

Definition at line 67 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_T3_LOM 0x151C

Definition at line 51 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_VF 0x10ED

Definition at line 71 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC

Definition at line 62 of file ixgbe_type.h.

#define IXGBE_DEV_ID_82599EN_SFP 0x1557

Definition at line 61 of file ixgbe_type.h.

#define IXGBE_DEV_ID_X540_VF 0x1515

Definition at line 72 of file ixgbe_type.h.

#define IXGBE_DEV_ID_X540T 0x1528

Definition at line 66 of file ixgbe_type.h.

#define IXGBE_DEV_ID_X540T1 0x1560

Definition at line 68 of file ixgbe_type.h.

#define IXGBE_DEVICE_CAPS 0x2C

Definition at line 1726 of file ixgbe_type.h.

#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1

Definition at line 1790 of file ixgbe_type.h.

#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2

Definition at line 1791 of file ixgbe_type.h.

#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */

Definition at line 1813 of file ixgbe_type.h.

#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */

Definition at line 1812 of file ixgbe_type.h.

#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */

Definition at line 1811 of file ixgbe_type.h.

#define IXGBE_DMATXCTL 0x04A80

Definition at line 327 of file ixgbe_type.h.

#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */

Definition at line 338 of file ixgbe_type.h.

#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */

Definition at line 337 of file ixgbe_type.h.

#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */

Definition at line 336 of file ixgbe_type.h.

#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */

Definition at line 339 of file ixgbe_type.h.

#define IXGBE_DPMCS 0x07F40

Definition at line 433 of file ixgbe_type.h.

#define IXGBE_DRECCCTL 0x02F08

Definition at line 230 of file ixgbe_type.h.

#define IXGBE_DRECCCTL_DISABLE 0

Definition at line 231 of file ixgbe_type.h.

#define IXGBE_DROPEN 0x03D04

Definition at line 224 of file ixgbe_type.h.

#define IXGBE_DTXCTL 0x07E00

Definition at line 325 of file ixgbe_type.h.

#define IXGBE_DTXMXSZRQ 0x08100

Definition at line 330 of file ixgbe_type.h.

#define IXGBE_DTXTCPFLGH 0x04A8C

Definition at line 332 of file ixgbe_type.h.

#define IXGBE_DTXTCPFLGL 0x04A88

Definition at line 331 of file ixgbe_type.h.

#define IXGBE_DV	(	_max_frame_link,
		_max_frame_tc
	)

Value:

((36 * \
              (IXGBE_B2BT(_max_frame_link) + \
               IXGBE_PFC_D + \
               (2 * IXGBE_CABLE_DC) + \
               (2 * IXGBE_ID) + \
               IXGBE_HD) / 25 + 1) + \
             2 * IXGBE_B2BT(_max_frame_tc))

Definition at line 2462 of file ixgbe_type.h.

#define IXGBE_DV_X540	(	_max_frame_link,
		_max_frame_tc
	)

Value:

((36 * \
              (IXGBE_B2BT(_max_frame_link) + \
               IXGBE_PFC_D + \
               (2 * IXGBE_CABLE_DC) + \
               (2 * IXGBE_ID_X540) + \
               IXGBE_HD) / 25 + 1) + \
             2 * IXGBE_B2BT(_max_frame_tc))

Definition at line 2452 of file ixgbe_type.h.

#define IXGBE_ECC_CTRL_0_82599 0x11100

Definition at line 786 of file ixgbe_type.h.

#define IXGBE_ECC_CTRL_1_82599 0x11104

Definition at line 787 of file ixgbe_type.h.

#define IXGBE_ECC_STATUS_82599 0x110E0

Definition at line 788 of file ixgbe_type.h.

#define IXGBE_EEC 0x10010

Definition at line 88 of file ixgbe_type.h.

#define IXGBE_EEC_ADDR_SIZE 0x00000400

Definition at line 1676 of file ixgbe_type.h.

#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */

Definition at line 1671 of file ixgbe_type.h.

#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */

Definition at line 1661 of file ixgbe_type.h.

#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */

Definition at line 1662 of file ixgbe_type.h.

#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */

Definition at line 1663 of file ixgbe_type.h.

#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */

Definition at line 1674 of file ixgbe_type.h.

#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */

Definition at line 1672 of file ixgbe_type.h.

#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */

Definition at line 1665 of file ixgbe_type.h.

#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */

Definition at line 1666 of file ixgbe_type.h.

#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */

Definition at line 1664 of file ixgbe_type.h.

#define IXGBE_EEC_FWE_SHIFT 4

Definition at line 1667 of file ixgbe_type.h.

#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */

Definition at line 1669 of file ixgbe_type.h.

#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */

Definition at line 1670 of file ixgbe_type.h.

#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */

Definition at line 1668 of file ixgbe_type.h.

#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */

Definition at line 1673 of file ixgbe_type.h.

#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */

Definition at line 1677 of file ixgbe_type.h.

#define IXGBE_EEC_SIZE_SHIFT 11

Definition at line 1680 of file ixgbe_type.h.

#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */

Definition at line 1660 of file ixgbe_type.h.

#define IXGBE_EEMNGCTL 0x10110

Definition at line 92 of file ixgbe_type.h.

#define IXGBE_EEMNGDATA 0x10114

Definition at line 93 of file ixgbe_type.h.

#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */

Definition at line 1746 of file ixgbe_type.h.

#define IXGBE_EEPROM_CHECKSUM 0x3F

Definition at line 1689 of file ixgbe_type.h.

#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */

Definition at line 1754 of file ixgbe_type.h.

#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */

Definition at line 1752 of file ixgbe_type.h.

#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */

Definition at line 1753 of file ixgbe_type.h.

#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */

Definition at line 1769 of file ixgbe_type.h.

#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */

Definition at line 1742 of file ixgbe_type.h.

#define IXGBE_EEPROM_OPCODE_BITS 8

Definition at line 1682 of file ixgbe_type.h.

#define IXGBE_EEPROM_PAGE_SIZE_MAX 128

Definition at line 1764 of file ixgbe_type.h.

#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */

Definition at line 1765 of file ixgbe_type.h.

#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */

Definition at line 1750 of file ixgbe_type.h.

#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */

Definition at line 1744 of file ixgbe_type.h.

#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */

Definition at line 1760 of file ixgbe_type.h.

#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */

Definition at line 1757 of file ixgbe_type.h.

#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */

Definition at line 1758 of file ixgbe_type.h.

#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */

Definition at line 1759 of file ixgbe_type.h.

#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01

Definition at line 1743 of file ixgbe_type.h.

#define IXGBE_EEPROM_SUM 0xBABA

Definition at line 1690 of file ixgbe_type.h.

#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6

Definition at line 1681 of file ixgbe_type.h.

#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */

Definition at line 1766 of file ixgbe_type.h.

#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04

Definition at line 1749 of file ixgbe_type.h.

#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */

Definition at line 1747 of file ixgbe_type.h.

#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */

Definition at line 1745 of file ixgbe_type.h.

#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */

Definition at line 1751 of file ixgbe_type.h.

#define IXGBE_EERD 0x10014

Definition at line 89 of file ixgbe_type.h.

#define IXGBE_EERD_EEWR_ATTEMPTS 100000

Definition at line 1775 of file ixgbe_type.h.

#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */

Definition at line 1678 of file ixgbe_type.h.

#define IXGBE_EEWR 0x10018

Definition at line 90 of file ixgbe_type.h.

#define IXGBE_EIAC 0x00810

Definition at line 140 of file ixgbe_type.h.

#define IXGBE_EIAM 0x00890

Definition at line 141 of file ixgbe_type.h.

#define IXGBE_EIAM_EX ( _i ) (0x00AD0 + (_i) * 4)

Definition at line 145 of file ixgbe_type.h.

#define IXGBE_EICR 0x00800

Definition at line 136 of file ixgbe_type.h.

#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */

Definition at line 1318 of file ixgbe_type.h.

#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */

Definition at line 1316 of file ixgbe_type.h.

#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */

Definition at line 1304 of file ixgbe_type.h.

#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */

Definition at line 1313 of file ixgbe_type.h.

#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */

Definition at line 1314 of file ixgbe_type.h.

#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */

Definition at line 1315 of file ixgbe_type.h.

#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */

Definition at line 1309 of file ixgbe_type.h.

#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */

Definition at line 1308 of file ixgbe_type.h.

#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */

Definition at line 1307 of file ixgbe_type.h.

#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */

Definition at line 1310 of file ixgbe_type.h.

#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */

Definition at line 1320 of file ixgbe_type.h.

#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */

Definition at line 1317 of file ixgbe_type.h.

#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */

Definition at line 1306 of file ixgbe_type.h.

#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */

Definition at line 1303 of file ixgbe_type.h.

#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */

Definition at line 1305 of file ixgbe_type.h.

#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */

Definition at line 1319 of file ixgbe_type.h.

#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */

Definition at line 1312 of file ixgbe_type.h.

#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */

Definition at line 1311 of file ixgbe_type.h.

#define IXGBE_EICS 0x00808

Definition at line 137 of file ixgbe_type.h.

#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */

Definition at line 1336 of file ixgbe_type.h.

#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */

Definition at line 1334 of file ixgbe_type.h.

#define IXGBE_EICS_EX ( _i ) (0x00A90 + (_i) * 4)

Definition at line 142 of file ixgbe_type.h.

#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */

Definition at line 1324 of file ixgbe_type.h.

#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */

Definition at line 1331 of file ixgbe_type.h.

#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */

Definition at line 1332 of file ixgbe_type.h.

#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */

Definition at line 1333 of file ixgbe_type.h.

#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */

Definition at line 1328 of file ixgbe_type.h.

#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */

Definition at line 1327 of file ixgbe_type.h.

#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */

Definition at line 1329 of file ixgbe_type.h.

#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */

Definition at line 1338 of file ixgbe_type.h.

#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */

Definition at line 1335 of file ixgbe_type.h.

#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */

Definition at line 1326 of file ixgbe_type.h.

#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */

Definition at line 1323 of file ixgbe_type.h.

#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */

Definition at line 1325 of file ixgbe_type.h.

#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */

Definition at line 1337 of file ixgbe_type.h.

#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */

Definition at line 1330 of file ixgbe_type.h.

#define IXGBE_EIMC 0x00888

Definition at line 139 of file ixgbe_type.h.

#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */

Definition at line 1373 of file ixgbe_type.h.

#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */

Definition at line 1371 of file ixgbe_type.h.

#define IXGBE_EIMC_EX ( _i ) (0x00AB0 + (_i) * 4)

Definition at line 144 of file ixgbe_type.h.

#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */

Definition at line 1361 of file ixgbe_type.h.

#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */

Definition at line 1368 of file ixgbe_type.h.

#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */

Definition at line 1369 of file ixgbe_type.h.

#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */

Definition at line 1370 of file ixgbe_type.h.

#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */

Definition at line 1365 of file ixgbe_type.h.

#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */

Definition at line 1364 of file ixgbe_type.h.

#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */

Definition at line 1366 of file ixgbe_type.h.

#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */

Definition at line 1375 of file ixgbe_type.h.

#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */

Definition at line 1372 of file ixgbe_type.h.

#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */

Definition at line 1363 of file ixgbe_type.h.

#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */

Definition at line 1360 of file ixgbe_type.h.

#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */

Definition at line 1362 of file ixgbe_type.h.

#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */

Definition at line 1374 of file ixgbe_type.h.

#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */

Definition at line 1367 of file ixgbe_type.h.

#define IXGBE_EIMS 0x00880

Definition at line 138 of file ixgbe_type.h.

#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */

Definition at line 1355 of file ixgbe_type.h.

#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */

Definition at line 1353 of file ixgbe_type.h.

#define IXGBE_EIMS_ENABLE_MASK

Value:

( \
                                IXGBE_EIMS_RTX_QUEUE       | \
                                IXGBE_EIMS_LSC             | \
                                IXGBE_EIMS_TCP_TIMER       | \
                                IXGBE_EIMS_OTHER)

Definition at line 1377 of file ixgbe_type.h.

#define IXGBE_EIMS_EX ( _i ) (0x00AA0 + (_i) * 4)

Definition at line 143 of file ixgbe_type.h.

#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */

Definition at line 1342 of file ixgbe_type.h.

#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */

Definition at line 1350 of file ixgbe_type.h.

#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */

Definition at line 1351 of file ixgbe_type.h.

#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */

Definition at line 1352 of file ixgbe_type.h.

#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */

Definition at line 1346 of file ixgbe_type.h.

#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */

Definition at line 1345 of file ixgbe_type.h.

#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */

Definition at line 1347 of file ixgbe_type.h.

#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */

Definition at line 1357 of file ixgbe_type.h.

#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */

Definition at line 1354 of file ixgbe_type.h.

#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */

Definition at line 1344 of file ixgbe_type.h.

#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */

Definition at line 1341 of file ixgbe_type.h.

#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */

Definition at line 1343 of file ixgbe_type.h.

#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */

Definition at line 1356 of file ixgbe_type.h.

#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */

Definition at line 1349 of file ixgbe_type.h.

#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermel Sensor Event */

Definition at line 1348 of file ixgbe_type.h.

#define IXGBE_EITR ( _i )

Value:

(((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \

(0x012300 + (((_i) - 24) * 4)))

Definition at line 155 of file ixgbe_type.h.

#define IXGBE_EITR_CNT_WDIS 0x80000000

Definition at line 159 of file ixgbe_type.h.

#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8

Definition at line 157 of file ixgbe_type.h.

#define IXGBE_EITR_LLI_MOD 0x00008000

Definition at line 158 of file ixgbe_type.h.

#define IXGBE_EITRSEL 0x00894

Definition at line 162 of file ixgbe_type.h.

#define IXGBE_EMC_DIODE1_DATA 0x01

Definition at line 117 of file ixgbe_type.h.

#define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19

Definition at line 118 of file ixgbe_type.h.

#define IXGBE_EMC_DIODE2_DATA 0x23

Definition at line 119 of file ixgbe_type.h.

#define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A

Definition at line 120 of file ixgbe_type.h.

#define IXGBE_EMC_INTERNAL_DATA 0x00

Definition at line 115 of file ixgbe_type.h.

#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20

Definition at line 116 of file ixgbe_type.h.

#define IXGBE_EODSDP 0x00028

Definition at line 79 of file ixgbe_type.h.

#define IXGBE_ERR_ADAPTER_STOPPED -9

Definition at line 3015 of file ixgbe_type.h.

#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14

Definition at line 3020 of file ixgbe_type.h.

#define IXGBE_ERR_CONFIG -4

Definition at line 3010 of file ixgbe_type.h.

#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11

Definition at line 3017 of file ixgbe_type.h.

#define IXGBE_ERR_EEPROM -1

Definition at line 3007 of file ixgbe_type.h.

#define IXGBE_ERR_EEPROM_CHECKSUM -2

Definition at line 3008 of file ixgbe_type.h.

#define IXGBE_ERR_EEPROM_VERSION -24

Definition at line 3030 of file ixgbe_type.h.

#define IXGBE_ERR_FC_NOT_NEGOTIATED -27

Definition at line 3033 of file ixgbe_type.h.

#define IXGBE_ERR_FC_NOT_SUPPORTED -28

Definition at line 3034 of file ixgbe_type.h.

#define IXGBE_ERR_FDIR_REINIT_FAILED -23

Definition at line 3029 of file ixgbe_type.h.

#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33

Definition at line 3038 of file ixgbe_type.h.

#define IXGBE_ERR_I2C -18

Definition at line 3024 of file ixgbe_type.h.

#define IXGBE_ERR_INVALID_ARGUMENT -32

Definition at line 3037 of file ixgbe_type.h.

#define IXGBE_ERR_INVALID_LINK_SETTINGS -13

Definition at line 3019 of file ixgbe_type.h.

#define IXGBE_ERR_INVALID_MAC_ADDR -10

Definition at line 3016 of file ixgbe_type.h.

#define IXGBE_ERR_LINK_SETUP -8

Definition at line 3014 of file ixgbe_type.h.

#define IXGBE_ERR_MAC_TYPE -6

Definition at line 3012 of file ixgbe_type.h.

#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12

Definition at line 3018 of file ixgbe_type.h.

#define IXGBE_ERR_NO_SAN_ADDR_PTR -22

Definition at line 3028 of file ixgbe_type.h.

#define IXGBE_ERR_NO_SPACE -25

Definition at line 3031 of file ixgbe_type.h.

#define IXGBE_ERR_OVERTEMP -26

Definition at line 3032 of file ixgbe_type.h.

#define IXGBE_ERR_PARAM -5

Definition at line 3011 of file ixgbe_type.h.

#define IXGBE_ERR_PBA_SECTION -31

Definition at line 3036 of file ixgbe_type.h.

#define IXGBE_ERR_PHY -3

Definition at line 3009 of file ixgbe_type.h.

#define IXGBE_ERR_PHY_ADDR_INVALID -17

Definition at line 3023 of file ixgbe_type.h.

#define IXGBE_ERR_RESET_FAILED -15

Definition at line 3021 of file ixgbe_type.h.

#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21

Definition at line 3027 of file ixgbe_type.h.

#define IXGBE_ERR_SFP_NOT_PRESENT -20

Definition at line 3026 of file ixgbe_type.h.

#define IXGBE_ERR_SFP_NOT_SUPPORTED -19

Definition at line 3025 of file ixgbe_type.h.

#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30

Definition at line 3035 of file ixgbe_type.h.

#define IXGBE_ERR_SWFW_SYNC -16

Definition at line 3022 of file ixgbe_type.h.

#define IXGBE_ERR_UNKNOWN_PHY -7

Definition at line 3013 of file ixgbe_type.h.

#define IXGBE_ERRBC 0x04008

Definition at line 628 of file ixgbe_type.h.

#define IXGBE_ESDP 0x00020

Definition at line 78 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */

Definition at line 1502 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */

Definition at line 1509 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 Native Function */

Definition at line 1512 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */

Definition at line 1503 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */

Definition at line 1504 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */

Definition at line 1505 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */

Definition at line 1506 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */

Definition at line 1510 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */

Definition at line 1507 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */

Definition at line 1511 of file ixgbe_type.h.

#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */

Definition at line 1508 of file ixgbe_type.h.

#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */

Definition at line 1491 of file ixgbe_type.h.

#define IXGBE_ETQF ( _i ) (0x05128 + ((_i) * 4)) /* EType Queue Filter */

Definition at line 255 of file ixgbe_type.h.

#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */

Definition at line 1450 of file ixgbe_type.h.

#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */

Definition at line 1449 of file ixgbe_type.h.

#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */

Definition at line 1448 of file ixgbe_type.h.

#define IXGBE_ETQF_FILTER_1588 3

Definition at line 1473 of file ixgbe_type.h.

#define IXGBE_ETQF_FILTER_EAPOL 0

Definition at line 1471 of file ixgbe_type.h.

#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */

Definition at line 1451 of file ixgbe_type.h.

#define IXGBE_ETQF_FILTER_FCOE 2

Definition at line 1472 of file ixgbe_type.h.

#define IXGBE_ETQF_FILTER_FIP 4

Definition at line 1474 of file ixgbe_type.h.

#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */

Definition at line 1452 of file ixgbe_type.h.

#define IXGBE_ETQF_POOL_SHIFT 20

Definition at line 1453 of file ixgbe_type.h.

#define IXGBE_ETQS ( _i ) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */

Definition at line 256 of file ixgbe_type.h.

#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */

Definition at line 1457 of file ixgbe_type.h.

#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */

Definition at line 1458 of file ixgbe_type.h.

#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */

Definition at line 1455 of file ixgbe_type.h.

#define IXGBE_ETQS_RX_QUEUE_SHIFT 16

Definition at line 1456 of file ixgbe_type.h.

#define IXGBE_ETS_CFG 0x26

Definition at line 1711 of file ixgbe_type.h.

#define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF

Definition at line 1723 of file ixgbe_type.h.

#define IXGBE_ETS_DATA_INDEX_MASK 0x0300

Definition at line 1721 of file ixgbe_type.h.

#define IXGBE_ETS_DATA_INDEX_SHIFT 8

Definition at line 1722 of file ixgbe_type.h.

#define IXGBE_ETS_DATA_LOC_MASK 0x3C00

Definition at line 1719 of file ixgbe_type.h.

#define IXGBE_ETS_DATA_LOC_SHIFT 10

Definition at line 1720 of file ixgbe_type.h.

#define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0

Definition at line 1712 of file ixgbe_type.h.

#define IXGBE_ETS_LTHRES_DELTA_SHIFT 6

Definition at line 1713 of file ixgbe_type.h.

#define IXGBE_ETS_NUM_SENSORS_MASK 0x0007

Definition at line 1718 of file ixgbe_type.h.

#define IXGBE_ETS_TYPE_EMC 0x000

Definition at line 1716 of file ixgbe_type.h.

#define IXGBE_ETS_TYPE_EMC_SHIFTED 0x000

Definition at line 1717 of file ixgbe_type.h.

#define IXGBE_ETS_TYPE_MASK 0x0038

Definition at line 1714 of file ixgbe_type.h.

#define IXGBE_ETS_TYPE_SHIFT 3

Definition at line 1715 of file ixgbe_type.h.

#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2

Definition at line 372 of file ixgbe_type.h.

#define IXGBE_EXVET 0x05078

Definition at line 85 of file ixgbe_type.h.

#define IXGBE_FACTPS 0x10150

Definition at line 759 of file ixgbe_type.h.

#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */

Definition at line 1020 of file ixgbe_type.h.

#define IXGBE_FCADBUH 0x03214

Definition at line 170 of file ixgbe_type.h.

#define IXGBE_FCADBUL 0x03210

Definition at line 169 of file ixgbe_type.h.

#define IXGBE_FCAMACH 0x0432C

Definition at line 172 of file ixgbe_type.h.

#define IXGBE_FCAMACL 0x04328

Definition at line 171 of file ixgbe_type.h.

#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */

Definition at line 571 of file ixgbe_type.h.

#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */

Definition at line 578 of file ixgbe_type.h.

#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8

Definition at line 581 of file ixgbe_type.h.

#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */

Definition at line 576 of file ixgbe_type.h.

#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3

Definition at line 580 of file ixgbe_type.h.

#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */

Definition at line 579 of file ixgbe_type.h.

#define IXGBE_FCBUFF_OFFSET_SHIFT 16

Definition at line 582 of file ixgbe_type.h.

#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */

Definition at line 575 of file ixgbe_type.h.

#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */

Definition at line 577 of file ixgbe_type.h.

#define IXGBE_FCCFG 0x03D00

Definition at line 180 of file ixgbe_type.h.

#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */

Definition at line 1297 of file ixgbe_type.h.

#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */

Definition at line 1298 of file ixgbe_type.h.

#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */

Definition at line 698 of file ixgbe_type.h.

#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */

Definition at line 572 of file ixgbe_type.h.

#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */

Definition at line 585 of file ixgbe_type.h.

#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */

Definition at line 586 of file ixgbe_type.h.

#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16

Definition at line 587 of file ixgbe_type.h.

#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */

Definition at line 584 of file ixgbe_type.h.

#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */

Definition at line 583 of file ixgbe_type.h.

#define IXGBE_FCFLT 0x05108 /* FC FLT Context */

Definition at line 595 of file ixgbe_type.h.

#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */

Definition at line 599 of file ixgbe_type.h.

#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */

Definition at line 601 of file ixgbe_type.h.

#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */

Definition at line 600 of file ixgbe_type.h.

#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */

Definition at line 598 of file ixgbe_type.h.

#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */

Definition at line 596 of file ixgbe_type.h.

#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */

Definition at line 604 of file ixgbe_type.h.

#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */

Definition at line 602 of file ixgbe_type.h.

#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */

Definition at line 603 of file ixgbe_type.h.

#define IXGBE_FCINVST ( _i ) (IXGBE_FCINVST0 + ((_i) * 4))

Definition at line 574 of file ixgbe_type.h.

#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */

Definition at line 573 of file ixgbe_type.h.

#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */

Definition at line 700 of file ixgbe_type.h.

#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */

Definition at line 1797 of file ixgbe_type.h.

#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */

Definition at line 1798 of file ixgbe_type.h.

#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */

Definition at line 702 of file ixgbe_type.h.

#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */

Definition at line 704 of file ixgbe_type.h.

#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */

Definition at line 701 of file ixgbe_type.h.

#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */

Definition at line 703 of file ixgbe_type.h.

#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */

Definition at line 699 of file ixgbe_type.h.

#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */

Definition at line 597 of file ixgbe_type.h.

#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */

Definition at line 570 of file ixgbe_type.h.

#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */

Definition at line 569 of file ixgbe_type.h.

#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */

Definition at line 618 of file ixgbe_type.h.

#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */

Definition at line 621 of file ixgbe_type.h.

#define IXGBE_FCRETA ( _i ) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */

Definition at line 620 of file ixgbe_type.h.

#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */

Definition at line 619 of file ixgbe_type.h.

#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */

Definition at line 623 of file ixgbe_type.h.

#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */

Definition at line 622 of file ixgbe_type.h.

#define IXGBE_FCRTH ( _i ) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */

Definition at line 178 of file ixgbe_type.h.

#define IXGBE_FCRTH_82599 ( _i ) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 173 of file ixgbe_type.h.

#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */

Definition at line 1282 of file ixgbe_type.h.

#define IXGBE_FCRTL ( _i ) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */

Definition at line 177 of file ixgbe_type.h.

#define IXGBE_FCRTL_82599 ( _i ) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 174 of file ixgbe_type.h.

#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */

Definition at line 1281 of file ixgbe_type.h.

#define IXGBE_FCRTV 0x032A0

Definition at line 179 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */

Definition at line 606 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */

Definition at line 611 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */

Definition at line 614 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */

Definition at line 607 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */

Definition at line 615 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8

Definition at line 616 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */

Definition at line 609 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */

Definition at line 612 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */

Definition at line 613 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */

Definition at line 610 of file ixgbe_type.h.

#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */

Definition at line 608 of file ixgbe_type.h.

#define IXGBE_FCTRL 0x05080

Definition at line 247 of file ixgbe_type.h.

#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */

Definition at line 1926 of file ixgbe_type.h.

#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */

Definition at line 1928 of file ixgbe_type.h.

#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/

Definition at line 1924 of file ixgbe_type.h.

#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */

Definition at line 1927 of file ixgbe_type.h.

#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */

Definition at line 1931 of file ixgbe_type.h.

#define IXGBE_FCTRL_RPFCE 0x00004000

Definition at line 1930 of file ixgbe_type.h.

#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */

Definition at line 1923 of file ixgbe_type.h.

#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */

Definition at line 1925 of file ixgbe_type.h.

#define IXGBE_FCTTV ( _i ) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */

Definition at line 176 of file ixgbe_type.h.

#define IXGBE_FDIR_DROP_QUEUE 127

Definition at line 2236 of file ixgbe_type.h.

#define IXGBE_FDIR_INIT_DONE_POLL 10

Definition at line 2233 of file ixgbe_type.h.

#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16

Definition at line 2165 of file ixgbe_type.h.

#define IXGBE_FDIRCMD 0x0EE2C

Definition at line 314 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_CLEARHT 0x00000100

Definition at line 2224 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001

Definition at line 2214 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_CMD_MASK 0x00000003

Definition at line 2213 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_CMD_POLL 10

Definition at line 2234 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003

Definition at line 2216 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002

Definition at line 2215 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_COLLISION 0x00001000

Definition at line 2228 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_DROP 0x00000200

Definition at line 2225 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008

Definition at line 2218 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004

Definition at line 2217 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5

Definition at line 2230 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_INT 0x00000400

Definition at line 2226 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_IPV6 0x00000080

Definition at line 2223 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010

Definition at line 2219 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060

Definition at line 2222 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040

Definition at line 2221 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020

Definition at line 2220 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_LAST 0x00000800

Definition at line 2227 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000

Definition at line 2229 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16

Definition at line 2231 of file ixgbe_type.h.

#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24

Definition at line 2232 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL 0x0EE00

Definition at line 289 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8

Definition at line 2175 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_FLEX_SHIFT 16

Definition at line 2176 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000

Definition at line 2179 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28

Definition at line 2180 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008

Definition at line 2171 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24

Definition at line 2178 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002

Definition at line 2169 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003

Definition at line 2170 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001

Definition at line 2168 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010

Definition at line 2172 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020

Definition at line 2173 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080

Definition at line 2174 of file ixgbe_type.h.

#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000

Definition at line 2177 of file ixgbe_type.h.

#define IXGBE_FDIRDIP4M 0x0EE3C

Definition at line 292 of file ixgbe_type.h.

#define IXGBE_FDIRFREE 0x0EE38

Definition at line 300 of file ixgbe_type.h.

#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000

Definition at line 2194 of file ixgbe_type.h.

#define IXGBE_FDIRFREE_COLL_SHIFT 16

Definition at line 2195 of file ixgbe_type.h.

#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF

Definition at line 2192 of file ixgbe_type.h.

#define IXGBE_FDIRFREE_FREE_SHIFT 0

Definition at line 2193 of file ixgbe_type.h.

#define IXGBE_FDIRFSTAT 0x0EE54

Definition at line 303 of file ixgbe_type.h.

#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF

Definition at line 2204 of file ixgbe_type.h.

#define IXGBE_FDIRFSTAT_FADD_SHIFT 0

Definition at line 2205 of file ixgbe_type.h.

#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00

Definition at line 2206 of file ixgbe_type.h.

#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8

Definition at line 2207 of file ixgbe_type.h.

#define IXGBE_FDIRHASH 0x0EE28

Definition at line 313 of file ixgbe_type.h.

#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15

Definition at line 2210 of file ixgbe_type.h.

#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16

Definition at line 2211 of file ixgbe_type.h.

#define IXGBE_FDIRHKEY 0x0EE68

Definition at line 290 of file ixgbe_type.h.

#define IXGBE_FDIRIP6M 0x0EE74

Definition at line 296 of file ixgbe_type.h.

#define IXGBE_FDIRIP6M_DIPM_SHIFT 16

Definition at line 2184 of file ixgbe_type.h.

#define IXGBE_FDIRIPDA 0x0EE1C

Definition at line 310 of file ixgbe_type.h.

#define IXGBE_FDIRIPSA 0x0EE18

Definition at line 309 of file ixgbe_type.h.

#define IXGBE_FDIRLEN 0x0EE4C

Definition at line 301 of file ixgbe_type.h.

#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000

Definition at line 2198 of file ixgbe_type.h.

#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16

Definition at line 2199 of file ixgbe_type.h.

#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F

Definition at line 2196 of file ixgbe_type.h.

#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0

Definition at line 2197 of file ixgbe_type.h.

#define IXGBE_FDIRM 0x0EE70

Definition at line 297 of file ixgbe_type.h.

#define IXGBE_FDIRM_DIPv6 0x00000020

Definition at line 2190 of file ixgbe_type.h.

#define IXGBE_FDIRM_FLEX 0x00000010

Definition at line 2189 of file ixgbe_type.h.

#define IXGBE_FDIRM_L4P 0x00000008

Definition at line 2188 of file ixgbe_type.h.

#define IXGBE_FDIRM_POOL 0x00000004

Definition at line 2187 of file ixgbe_type.h.

#define IXGBE_FDIRM_VLANID 0x00000001

Definition at line 2185 of file ixgbe_type.h.

#define IXGBE_FDIRM_VLANP 0x00000002

Definition at line 2186 of file ixgbe_type.h.

#define IXGBE_FDIRMATCH 0x0EE58

Definition at line 304 of file ixgbe_type.h.

#define IXGBE_FDIRMISS 0x0EE5C

Definition at line 305 of file ixgbe_type.h.

#define IXGBE_FDIRPORT 0x0EE20

Definition at line 311 of file ixgbe_type.h.

#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16

Definition at line 2208 of file ixgbe_type.h.

#define IXGBE_FDIRSIP4M 0x0EE40

Definition at line 293 of file ixgbe_type.h.

#define IXGBE_FDIRSIPv6 ( _i ) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */

Definition at line 308 of file ixgbe_type.h.

#define IXGBE_FDIRSKEY 0x0EE6C

Definition at line 291 of file ixgbe_type.h.

#define IXGBE_FDIRTCPM 0x0EE44

Definition at line 294 of file ixgbe_type.h.

#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16

Definition at line 2182 of file ixgbe_type.h.

#define IXGBE_FDIRUDPM 0x0EE48

Definition at line 295 of file ixgbe_type.h.

#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16

Definition at line 2183 of file ixgbe_type.h.

#define IXGBE_FDIRUSTAT 0x0EE50

Definition at line 302 of file ixgbe_type.h.

#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF

Definition at line 2200 of file ixgbe_type.h.

#define IXGBE_FDIRUSTAT_ADD_SHIFT 0

Definition at line 2201 of file ixgbe_type.h.

#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000

Definition at line 2202 of file ixgbe_type.h.

#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16

Definition at line 2203 of file ixgbe_type.h.

#define IXGBE_FDIRVLAN 0x0EE24

Definition at line 312 of file ixgbe_type.h.

#define IXGBE_FDIRVLAN_FLEX_SHIFT 16

Definition at line 2209 of file ixgbe_type.h.

#define IXGBE_FECS1 0x042E8

Definition at line 937 of file ixgbe_type.h.

#define IXGBE_FECS2 0x042EC

Definition at line 938 of file ixgbe_type.h.

#define IXGBE_FHFT ( _n ) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */

Definition at line 368 of file ixgbe_type.h.

#define IXGBE_FHFT_EXT ( _n )

Value:

(0x09800 + ((_n) * 0x100)) /* Ext Flexible Host

* Filter Table */

Definition at line 369 of file ixgbe_type.h.

#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */

Definition at line 377 of file ixgbe_type.h.

#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */

Definition at line 376 of file ixgbe_type.h.

#define IXGBE_FLA 0x1001C

Definition at line 91 of file ixgbe_type.h.

#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01

Definition at line 2897 of file ixgbe_type.h.

#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */

Definition at line 737 of file ixgbe_type.h.

#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4

Definition at line 371 of file ixgbe_type.h.

#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128

Definition at line 375 of file ixgbe_type.h.

#define IXGBE_FLMNGCNT 0x10120

Definition at line 96 of file ixgbe_type.h.

#define IXGBE_FLMNGCTL 0x10118

Definition at line 94 of file ixgbe_type.h.

#define IXGBE_FLMNGDATA 0x1011C

Definition at line 95 of file ixgbe_type.h.

#define IXGBE_FLOP 0x1013C

Definition at line 97 of file ixgbe_type.h.

#define IXGBE_FLUDONE_ATTEMPTS 20000

Definition at line 1780 of file ixgbe_type.h.

#define IXGBE_FREE_SPACE_PTR 0X3E

Definition at line 1708 of file ixgbe_type.h.

#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */

Definition at line 827 of file ixgbe_type.h.

#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */

Definition at line 828 of file ixgbe_type.h.

#define IXGBE_FRTIMER 0x00048

Definition at line 82 of file ixgbe_type.h.

#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */

Definition at line 725 of file ixgbe_type.h.

#define IXGBE_FTQF ( _i ) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */

Definition at line 254 of file ixgbe_type.h.

#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F

Definition at line 1417 of file ixgbe_type.h.

#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25

Definition at line 1418 of file ixgbe_type.h.

#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D

Definition at line 1420 of file ixgbe_type.h.

#define IXGBE_FTQF_DEST_PORT_MASK 0x17

Definition at line 1422 of file ixgbe_type.h.

#define IXGBE_FTQF_POOL_MASK 0x0000003F

Definition at line 1415 of file ixgbe_type.h.

#define IXGBE_FTQF_POOL_MASK_EN 0x40000000

Definition at line 1424 of file ixgbe_type.h.

#define IXGBE_FTQF_POOL_SHIFT 8

Definition at line 1416 of file ixgbe_type.h.

#define IXGBE_FTQF_PRIORITY_MASK 0x00000007

Definition at line 1413 of file ixgbe_type.h.

#define IXGBE_FTQF_PRIORITY_SHIFT 2

Definition at line 1414 of file ixgbe_type.h.

#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F

Definition at line 1423 of file ixgbe_type.h.

#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003

Definition at line 1409 of file ixgbe_type.h.

#define IXGBE_FTQF_PROTOCOL_SCTP 2

Definition at line 1412 of file ixgbe_type.h.

#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000

Definition at line 1410 of file ixgbe_type.h.

#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001

Definition at line 1411 of file ixgbe_type.h.

#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000

Definition at line 1425 of file ixgbe_type.h.

#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E

Definition at line 1419 of file ixgbe_type.h.

#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B

Definition at line 1421 of file ixgbe_type.h.

#define IXGBE_FUNCTAG 0x11008

Definition at line 749 of file ixgbe_type.h.

#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2

Definition at line 1792 of file ixgbe_type.h.

#define IXGBE_FW_LESM_STATE_1 0x1

Definition at line 1793 of file ixgbe_type.h.

#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */

Definition at line 1794 of file ixgbe_type.h.

#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4

Definition at line 1795 of file ixgbe_type.h.

#define IXGBE_FW_PATCH_VERSION_4 0x7

Definition at line 1796 of file ixgbe_type.h.

#define IXGBE_FW_PTR 0x0F

Definition at line 1705 of file ixgbe_type.h.

#define IXGBE_FWSM 0x10148

Definition at line 762 of file ixgbe_type.h.

#define IXGBE_FWSTS 0x15F0C

Definition at line 732 of file ixgbe_type.h.

#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */

Definition at line 1657 of file ixgbe_type.h.

#define IXGBE_GCR 0x11000

Definition at line 747 of file ixgbe_type.h.

#define IXGBE_GCR_CAP_VER2 0x00040000

Definition at line 795 of file ixgbe_type.h.

#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000

Definition at line 793 of file ixgbe_type.h.

#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000

Definition at line 792 of file ixgbe_type.h.

#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000

Definition at line 794 of file ixgbe_type.h.

#define IXGBE_GCR_EXT 0x11050

Definition at line 770 of file ixgbe_type.h.

#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000

Definition at line 798 of file ixgbe_type.h.

#define IXGBE_GCR_EXT_MSIX_EN 0x80000000

Definition at line 797 of file ixgbe_type.h.

#define IXGBE_GCR_EXT_SRIOV

Value:

(IXGBE_GCR_EXT_MSIX_EN | \

IXGBE_GCR_EXT_VT_MODE_64)

Definition at line 802 of file ixgbe_type.h.

#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001

Definition at line 799 of file ixgbe_type.h.

#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002

Definition at line 800 of file ixgbe_type.h.

#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003

Definition at line 801 of file ixgbe_type.h.

#define IXGBE_GHECCR 0x110B0

Definition at line 892 of file ixgbe_type.h.

#define IXGBE_GLT 0x1100C

Definition at line 750 of file ixgbe_type.h.

#define IXGBE_GORCH 0x0408C

Definition at line 658 of file ixgbe_type.h.

#define IXGBE_GORCL 0x04088

Definition at line 657 of file ixgbe_type.h.

#define IXGBE_GOTCH 0x04094

Definition at line 660 of file ixgbe_type.h.

#define IXGBE_GOTCL 0x04090

Definition at line 659 of file ixgbe_type.h.

#define IXGBE_GPIE 0x00898

Definition at line 166 of file ixgbe_type.h.

#define IXGBE_GPIE_EIAME 0x40000000

Definition at line 1155 of file ixgbe_type.h.

#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */

Definition at line 1154 of file ixgbe_type.h.

#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */

Definition at line 1152 of file ixgbe_type.h.

#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */

Definition at line 1153 of file ixgbe_type.h.

#define IXGBE_GPIE_PBA_SUPPORT 0x80000000

Definition at line 1156 of file ixgbe_type.h.

#define IXGBE_GPIE_RSC_DELAY_SHIFT 11

Definition at line 1157 of file ixgbe_type.h.

#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */

Definition at line 1159 of file ixgbe_type.h.

#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */

Definition at line 1160 of file ixgbe_type.h.

#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */

Definition at line 1161 of file ixgbe_type.h.

#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */

Definition at line 1158 of file ixgbe_type.h.

#define IXGBE_GPRC 0x04074

Definition at line 653 of file ixgbe_type.h.

#define IXGBE_GPTC 0x04080

Definition at line 656 of file ixgbe_type.h.

#define IXGBE_GRC 0x10200

Definition at line 98 of file ixgbe_type.h.

#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */

Definition at line 102 of file ixgbe_type.h.

#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */

Definition at line 101 of file ixgbe_type.h.

#define IXGBE_GSCL_1 0x11010

Definition at line 751 of file ixgbe_type.h.

#define IXGBE_GSCL_2 0x11014

Definition at line 752 of file ixgbe_type.h.

#define IXGBE_GSCL_3 0x11018

Definition at line 753 of file ixgbe_type.h.

#define IXGBE_GSCL_4 0x1101C

Definition at line 754 of file ixgbe_type.h.

#define IXGBE_GSCL_5_82599 0x11030

Definition at line 771 of file ixgbe_type.h.

#define IXGBE_GSCL_6_82599 0x11034

Definition at line 772 of file ixgbe_type.h.

#define IXGBE_GSCL_7_82599 0x11038

Definition at line 773 of file ixgbe_type.h.

#define IXGBE_GSCL_8_82599 0x1103C

Definition at line 774 of file ixgbe_type.h.

#define IXGBE_GSCN_0 0x11020

Definition at line 755 of file ixgbe_type.h.

#define IXGBE_GSCN_1 0x11024

Definition at line 756 of file ixgbe_type.h.

#define IXGBE_GSCN_2 0x11028

Definition at line 757 of file ixgbe_type.h.

#define IXGBE_GSCN_3 0x1102C

Definition at line 758 of file ixgbe_type.h.

#define IXGBE_GSSR 0x10160

Definition at line 763 of file ixgbe_type.h.

#define IXGBE_GSSR_EEP_SM 0x0001

Definition at line 1649 of file ixgbe_type.h.

#define IXGBE_GSSR_FLASH_SM 0x0010

Definition at line 1653 of file ixgbe_type.h.

#define IXGBE_GSSR_MAC_CSR_SM 0x0008

Definition at line 1652 of file ixgbe_type.h.

#define IXGBE_GSSR_PHY0_SM 0x0002

Definition at line 1650 of file ixgbe_type.h.

#define IXGBE_GSSR_PHY1_SM 0x0004

Definition at line 1651 of file ixgbe_type.h.

#define IXGBE_GSSR_SW_MNG_SM 0x0400

Definition at line 1654 of file ixgbe_type.h.

#define IXGBE_GTV 0x11004

Definition at line 748 of file ixgbe_type.h.

#define IXGBE_HD 6144

Definition at line 2446 of file ixgbe_type.h.

#define IXGBE_HFDR 0x15FE8

Definition at line 736 of file ixgbe_type.h.

#define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */

Definition at line 2241 of file ixgbe_type.h.

#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */

Definition at line 2239 of file ixgbe_type.h.

#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */

Definition at line 2240 of file ixgbe_type.h.

#define IXGBE_HICR 0x15F00

Definition at line 731 of file ixgbe_type.h.

#define IXGBE_HICR_C 0x02

Definition at line 741 of file ixgbe_type.h.

#define IXGBE_HICR_EN 0x01 /* Enable bit - RO */

Definition at line 739 of file ixgbe_type.h.

#define IXGBE_HICR_FW_RESET 0x80

Definition at line 744 of file ixgbe_type.h.

#define IXGBE_HICR_FW_RESET_ENABLE 0x40

Definition at line 743 of file ixgbe_type.h.

#define IXGBE_HICR_SV 0x04 /* Status Validity */

Definition at line 742 of file ixgbe_type.h.

#define IXGBE_HLREG0 0x04240

Definition at line 904 of file ixgbe_type.h.

#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */

Definition at line 1211 of file ixgbe_type.h.

#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */

Definition at line 1212 of file ixgbe_type.h.

#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */

Definition at line 1205 of file ixgbe_type.h.

#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */

Definition at line 1209 of file ixgbe_type.h.

#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */

Definition at line 1210 of file ixgbe_type.h.

#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */

Definition at line 1213 of file ixgbe_type.h.

#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */

Definition at line 1214 of file ixgbe_type.h.

#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */

Definition at line 1204 of file ixgbe_type.h.

#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */

Definition at line 1216 of file ixgbe_type.h.

#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */

Definition at line 1217 of file ixgbe_type.h.

#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */

Definition at line 1208 of file ixgbe_type.h.

#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */

Definition at line 1215 of file ixgbe_type.h.

#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */

Definition at line 1203 of file ixgbe_type.h.

#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */

Definition at line 1206 of file ixgbe_type.h.

#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */

Definition at line 1207 of file ixgbe_type.h.

#define IXGBE_HLREG1 0x04244

Definition at line 905 of file ixgbe_type.h.

#define IXGBE_HSMC0R 0x15F04

Definition at line 733 of file ixgbe_type.h.

#define IXGBE_HSMC1R 0x15F08

Definition at line 734 of file ixgbe_type.h.

#define IXGBE_I2C_CLK_IN 0x00000001

Definition at line 108 of file ixgbe_type.h.

#define IXGBE_I2C_CLK_OUT 0x00000002

Definition at line 109 of file ixgbe_type.h.

#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500

Definition at line 112 of file ixgbe_type.h.

#define IXGBE_I2C_DATA_IN 0x00000004

Definition at line 110 of file ixgbe_type.h.

#define IXGBE_I2C_DATA_OUT 0x00000008

Definition at line 111 of file ixgbe_type.h.

#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8

Definition at line 114 of file ixgbe_type.h.

#define IXGBE_I2CCTL 0x00028

Definition at line 80 of file ixgbe_type.h.

#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)

Definition at line 2443 of file ixgbe_type.h.

#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)

Definition at line 2436 of file ixgbe_type.h.

#define IXGBE_ILLERRC 0x04004

Definition at line 627 of file ixgbe_type.h.

#define IXGBE_IMIR ( _i ) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 281 of file ixgbe_type.h.

#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */

Definition at line 1396 of file ixgbe_type.h.

#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */

Definition at line 1401 of file ixgbe_type.h.

#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */

Definition at line 1400 of file ixgbe_type.h.

#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */

Definition at line 1397 of file ixgbe_type.h.

#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */

Definition at line 1398 of file ixgbe_type.h.

#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */

Definition at line 1399 of file ixgbe_type.h.

#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */

Definition at line 1395 of file ixgbe_type.h.

#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */

Definition at line 1402 of file ixgbe_type.h.

#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */

Definition at line 1385 of file ixgbe_type.h.

#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */

Definition at line 1384 of file ixgbe_type.h.

#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */

Definition at line 1403 of file ixgbe_type.h.

#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */

Definition at line 1404 of file ixgbe_type.h.

#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */

Definition at line 1394 of file ixgbe_type.h.

#define IXGBE_IMIREXT ( _i ) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 282 of file ixgbe_type.h.

#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */

Definition at line 1388 of file ixgbe_type.h.

#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */

Definition at line 1393 of file ixgbe_type.h.

#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */

Definition at line 1392 of file ixgbe_type.h.

#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */

Definition at line 1389 of file ixgbe_type.h.

#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */

Definition at line 1390 of file ixgbe_type.h.

#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */

Definition at line 1391 of file ixgbe_type.h.

#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */

Definition at line 1387 of file ixgbe_type.h.

#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */

Definition at line 1386 of file ixgbe_type.h.

#define IXGBE_IMIRVP 0x05AC0

Definition at line 283 of file ixgbe_type.h.

#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */

Definition at line 1406 of file ixgbe_type.h.

#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */

Definition at line 1405 of file ixgbe_type.h.

#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */

Definition at line 363 of file ixgbe_type.h.

#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */

Definition at line 364 of file ixgbe_type.h.

#define IXGBE_IPAV 0x05838

Definition at line 362 of file ixgbe_type.h.

#define IXGBE_IPSRXIDX 0x08E00

Definition at line 531 of file ixgbe_type.h.

#define IXGBE_IPSRXIPADDR ( _i ) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */

Definition at line 532 of file ixgbe_type.h.

#define IXGBE_IPSRXIPIDX 0x08E18

Definition at line 534 of file ixgbe_type.h.

#define IXGBE_IPSRXKEY ( _i ) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */

Definition at line 535 of file ixgbe_type.h.

#define IXGBE_IPSRXMOD 0x08E30

Definition at line 537 of file ixgbe_type.h.

#define IXGBE_IPSRXSALT 0x08E2C

Definition at line 536 of file ixgbe_type.h.

#define IXGBE_IPSRXSPI 0x08E14

Definition at line 533 of file ixgbe_type.h.

#define IXGBE_IPSTXIDX 0x08900

Definition at line 528 of file ixgbe_type.h.

#define IXGBE_IPSTXKEY ( _i ) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */

Definition at line 530 of file ixgbe_type.h.

#define IXGBE_IPSTXSALT 0x08904

Definition at line 529 of file ixgbe_type.h.

#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF

Definition at line 1428 of file ixgbe_type.h.

#define IXGBE_IS_BROADCAST ( Address )

Value:

((((u8 *)(Address))[0] == ((u8)0xff)) && \

(((u8 *)(Address))[1] == ((u8)0xff)))

Definition at line 1840 of file ixgbe_type.h.

#define IXGBE_IS_MULTICAST ( Address ) (bool)(((u8 *)(Address))[0] & ((u8)0x01))

Definition at line 1836 of file ixgbe_type.h.

#define IXGBE_ISCSI_BOOT_CAPS 0x0033

Definition at line 1737 of file ixgbe_type.h.

#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */

Definition at line 1799 of file ixgbe_type.h.

#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */

Definition at line 1801 of file ixgbe_type.h.

#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */

Definition at line 1800 of file ixgbe_type.h.

#define IXGBE_ISCSI_SETUP_PORT_0 0x0030

Definition at line 1738 of file ixgbe_type.h.

#define IXGBE_ISCSI_SETUP_PORT_1 0x0034

Definition at line 1739 of file ixgbe_type.h.

#define IXGBE_IVAR ( _i ) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */

Definition at line 160 of file ixgbe_type.h.

#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */

Definition at line 1444 of file ixgbe_type.h.

#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */

Definition at line 161 of file ixgbe_type.h.

#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */

Definition at line 1440 of file ixgbe_type.h.

#define IXGBE_IVAR_REG_NUM 25

Definition at line 1431 of file ixgbe_type.h.

#define IXGBE_IVAR_REG_NUM_82599 64

Definition at line 1432 of file ixgbe_type.h.

#define IXGBE_IVAR_RX_ENTRY 64

Definition at line 1434 of file ixgbe_type.h.

#define IXGBE_IVAR_RX_QUEUE ( _i ) (0 + (_i))

Definition at line 1435 of file ixgbe_type.h.

#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */

Definition at line 1439 of file ixgbe_type.h.

#define IXGBE_IVAR_TX_ENTRY 32

Definition at line 1437 of file ixgbe_type.h.

#define IXGBE_IVAR_TX_QUEUE ( _i ) (64 + (_i))

Definition at line 1436 of file ixgbe_type.h.

#define IXGBE_IVAR_TXRX_ENTRY 96

Definition at line 1433 of file ixgbe_type.h.

#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */

Definition at line 1873 of file ixgbe_type.h.

#define IXGBE_KRPCSFC 0x042E0

Definition at line 935 of file ixgbe_type.h.

#define IXGBE_KRPCSS 0x042E4

Definition at line 936 of file ixgbe_type.h.

#define IXGBE_L34T_IMIR ( _i ) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/

Definition at line 278 of file ixgbe_type.h.

#define IXGBE_LBDRPEN 0x0CA00

Definition at line 333 of file ixgbe_type.h.

#define IXGBE_LDPCECH 0x0E821

Definition at line 713 of file ixgbe_type.h.

#define IXGBE_LDPCECL 0x0E820

Definition at line 712 of file ixgbe_type.h.

#define IXGBE_LED_BLINK ( _i ) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)

Definition at line 1521 of file ixgbe_type.h.

#define IXGBE_LED_BLINK_BASE 0x00000080

Definition at line 1516 of file ixgbe_type.h.

#define IXGBE_LED_FILTER 0x3

Definition at line 1528 of file ixgbe_type.h.

#define IXGBE_LED_IVRT ( _i ) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)

Definition at line 1520 of file ixgbe_type.h.

#define IXGBE_LED_IVRT_BASE 0x00000040

Definition at line 1515 of file ixgbe_type.h.

#define IXGBE_LED_LINK_10G 0x1

Definition at line 1526 of file ixgbe_type.h.

#define IXGBE_LED_LINK_1G 0x5

Definition at line 1530 of file ixgbe_type.h.

#define IXGBE_LED_LINK_ACTIVE 0x4

Definition at line 1529 of file ixgbe_type.h.

#define IXGBE_LED_LINK_UP 0x0

Definition at line 1525 of file ixgbe_type.h.

#define IXGBE_LED_MAC 0x2

Definition at line 1527 of file ixgbe_type.h.

#define IXGBE_LED_MODE_MASK ( _i ) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)

Definition at line 1522 of file ixgbe_type.h.

#define IXGBE_LED_MODE_MASK_BASE 0x0000000F

Definition at line 1517 of file ixgbe_type.h.

#define IXGBE_LED_MODE_SHIFT ( _i ) (8 * (_i))

Definition at line 1519 of file ixgbe_type.h.

#define IXGBE_LED_OFF 0xF

Definition at line 1532 of file ixgbe_type.h.

#define IXGBE_LED_OFFSET	(	_base,
		_i
	)	(_base << (8 * (_i)))

Definition at line 1518 of file ixgbe_type.h.

#define IXGBE_LED_ON 0xE

Definition at line 1531 of file ixgbe_type.h.

#define IXGBE_LEDCTL 0x00200

Definition at line 81 of file ixgbe_type.h.

#define IXGBE_LINK_SPEED_100_FULL 0x0008

Definition at line 2388 of file ixgbe_type.h.

#define IXGBE_LINK_SPEED_10GB_FULL 0x0080

Definition at line 2390 of file ixgbe_type.h.

#define IXGBE_LINK_SPEED_1GB_FULL 0x0020

Definition at line 2389 of file ixgbe_type.h.

#define IXGBE_LINK_SPEED_82598_AUTONEG

Value:

(IXGBE_LINK_SPEED_1GB_FULL | \

IXGBE_LINK_SPEED_10GB_FULL)

Definition at line 2391 of file ixgbe_type.h.

#define IXGBE_LINK_SPEED_82599_AUTONEG

Value:

(IXGBE_LINK_SPEED_100_FULL | \
                                        IXGBE_LINK_SPEED_1GB_FULL | \
                                        IXGBE_LINK_SPEED_10GB_FULL)

Definition at line 2393 of file ixgbe_type.h.

#define IXGBE_LINK_SPEED_UNKNOWN 0

Definition at line 2387 of file ixgbe_type.h.

#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */

Definition at line 1611 of file ixgbe_type.h.

#define IXGBE_LINKS 0x042A4

Definition at line 924 of file ixgbe_type.h.

#define IXGBE_LINKS2 0x04324

Definition at line 925 of file ixgbe_type.h.

#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040

Definition at line 1614 of file ixgbe_type.h.

#define IXGBE_LINKS_10G_ALIGN 0x00020000

Definition at line 1602 of file ixgbe_type.h.

#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000

Definition at line 1603 of file ixgbe_type.h.

#define IXGBE_LINKS_1G_AN_EN 0x00100000

Definition at line 1599 of file ixgbe_type.h.

#define IXGBE_LINKS_1G_SYNC 0x00040000

Definition at line 1601 of file ixgbe_type.h.

#define IXGBE_LINKS_KX_AN_COMP 0x80000000

Definition at line 1590 of file ixgbe_type.h.

#define IXGBE_LINKS_KX_AN_IDLE 0x00080000

Definition at line 1600 of file ixgbe_type.h.

#define IXGBE_LINKS_MODE 0x18000000

Definition at line 1593 of file ixgbe_type.h.

#define IXGBE_LINKS_PCS_1G_EN 0x00200000

Definition at line 1598 of file ixgbe_type.h.

#define IXGBE_LINKS_RX_MODE 0x06000000

Definition at line 1594 of file ixgbe_type.h.

#define IXGBE_LINKS_SGMII_EN 0x02000000

Definition at line 1597 of file ixgbe_type.h.

#define IXGBE_LINKS_SIGNAL 0x00000F00

Definition at line 1605 of file ixgbe_type.h.

#define IXGBE_LINKS_SPEED 0x20000000

Definition at line 1592 of file ixgbe_type.h.

#define IXGBE_LINKS_SPEED_100_82599 0x10000000

Definition at line 1610 of file ixgbe_type.h.

#define IXGBE_LINKS_SPEED_10G_82599 0x30000000

Definition at line 1608 of file ixgbe_type.h.

#define IXGBE_LINKS_SPEED_1G_82599 0x20000000

Definition at line 1609 of file ixgbe_type.h.

#define IXGBE_LINKS_SPEED_82599 0x30000000

Definition at line 1607 of file ixgbe_type.h.

#define IXGBE_LINKS_TL_FAULT 0x00001000

Definition at line 1604 of file ixgbe_type.h.

#define IXGBE_LINKS_TX_MODE 0x01800000

Definition at line 1595 of file ixgbe_type.h.

#define IXGBE_LINKS_UP 0x40000000

Definition at line 1591 of file ixgbe_type.h.

#define IXGBE_LINKS_XGXS_EN 0x00400000

Definition at line 1596 of file ixgbe_type.h.

#define IXGBE_LLITHRESH 0x0EC90

Definition at line 280 of file ixgbe_type.h.

#define IXGBE_LOW_DV ( _max_frame_tc ) (2 * IXGBE_LOW_DV_X540(_max_frame_tc))

Definition at line 2475 of file ixgbe_type.h.

#define IXGBE_LOW_DV_X540 ( _max_frame_tc )

Value:

(2 * IXGBE_B2BT(_max_frame_tc) + \

(36 * IXGBE_PCI_DELAY / 25) + 1)

Definition at line 2472 of file ixgbe_type.h.

#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */

Definition at line 491 of file ixgbe_type.h.

#define IXGBE_LSECRXCAP 0x08F00

Definition at line 468 of file ixgbe_type.h.

#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000

Definition at line 506 of file ixgbe_type.h.

#define IXGBE_LSECRXCAP_SUM_SHIFT 16

Definition at line 507 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL 0x08F04

Definition at line 477 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL_CHECK 0x1

Definition at line 520 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL_DISABLE 0x0

Definition at line 519 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL_DROP 0x3

Definition at line 522 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C

Definition at line 517 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL_EN_SHIFT 2

Definition at line 518 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL_PLSH 0x00000040

Definition at line 523 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL_RP 0x00000080

Definition at line 524 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33

Definition at line 525 of file ixgbe_type.h.

#define IXGBE_LSECRXCTRL_STRICT 0x2

Definition at line 521 of file ixgbe_type.h.

#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */

Definition at line 495 of file ixgbe_type.h.

#define IXGBE_LSECRXINV ( _n ) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */

Definition at line 498 of file ixgbe_type.h.

#define IXGBE_LSECRXKEY	(	_n,
		_m
	)	(0x08F20 + ((0x10 * (_n)) + (4 * (_m))))

Definition at line 482 of file ixgbe_type.h.

#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */

Definition at line 496 of file ixgbe_type.h.

#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */

Definition at line 492 of file ixgbe_type.h.

#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */

Definition at line 501 of file ixgbe_type.h.

#define IXGBE_LSECRXNV ( _n ) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */

Definition at line 499 of file ixgbe_type.h.

#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */

Definition at line 489 of file ixgbe_type.h.

#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */

Definition at line 490 of file ixgbe_type.h.

#define IXGBE_LSECRXOK ( _n ) (0x08F64 + (0x04 * (_n))) /* InPktsOk */

Definition at line 497 of file ixgbe_type.h.

#define IXGBE_LSECRXPN ( _i ) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */

Definition at line 481 of file ixgbe_type.h.

#define IXGBE_LSECRXSA ( _i ) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */

Definition at line 480 of file ixgbe_type.h.

#define IXGBE_LSECRXSCH 0x08F0C

Definition at line 479 of file ixgbe_type.h.

#define IXGBE_LSECRXSCL 0x08F08

Definition at line 478 of file ixgbe_type.h.

#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */

Definition at line 494 of file ixgbe_type.h.

#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */

Definition at line 500 of file ixgbe_type.h.

#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */

Definition at line 493 of file ixgbe_type.h.

#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */

Definition at line 488 of file ixgbe_type.h.

#define IXGBE_LSECTXCAP 0x08A00

Definition at line 467 of file ixgbe_type.h.

#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000

Definition at line 504 of file ixgbe_type.h.

#define IXGBE_LSECTXCAP_SUM_SHIFT 16

Definition at line 505 of file ixgbe_type.h.

#define IXGBE_LSECTXCTRL 0x08A04

Definition at line 469 of file ixgbe_type.h.

#define IXGBE_LSECTXCTRL_AISCI 0x00000020

Definition at line 513 of file ixgbe_type.h.

#define IXGBE_LSECTXCTRL_AUTH 0x1

Definition at line 511 of file ixgbe_type.h.

#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2

Definition at line 512 of file ixgbe_type.h.

#define IXGBE_LSECTXCTRL_DISABLE 0x0

Definition at line 510 of file ixgbe_type.h.

#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003

Definition at line 509 of file ixgbe_type.h.

#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00

Definition at line 514 of file ixgbe_type.h.

#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8

Definition at line 515 of file ixgbe_type.h.

#define IXGBE_LSECTXKEY0 ( _n ) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */

Definition at line 475 of file ixgbe_type.h.

#define IXGBE_LSECTXKEY1 ( _n ) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */

Definition at line 476 of file ixgbe_type.h.

#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */

Definition at line 486 of file ixgbe_type.h.

#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */

Definition at line 487 of file ixgbe_type.h.

#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */

Definition at line 484 of file ixgbe_type.h.

#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */

Definition at line 485 of file ixgbe_type.h.

#define IXGBE_LSECTXPN0 0x08A14

Definition at line 473 of file ixgbe_type.h.

#define IXGBE_LSECTXPN1 0x08A18

Definition at line 474 of file ixgbe_type.h.

#define IXGBE_LSECTXSA 0x08A10

Definition at line 472 of file ixgbe_type.h.

#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */

Definition at line 471 of file ixgbe_type.h.

#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */

Definition at line 470 of file ixgbe_type.h.

#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */

Definition at line 483 of file ixgbe_type.h.

#define IXGBE_LSWFW 0x15014

Definition at line 728 of file ixgbe_type.h.

#define IXGBE_LXOFFRXC 0x0CF68

Definition at line 637 of file ixgbe_type.h.

#define IXGBE_LXOFFRXCNT 0x041A8

Definition at line 639 of file ixgbe_type.h.

#define IXGBE_LXOFFTXC 0x03F68

Definition at line 636 of file ixgbe_type.h.

#define IXGBE_LXONRXC 0x0CF60

Definition at line 635 of file ixgbe_type.h.

#define IXGBE_LXONRXCNT 0x041A4

Definition at line 638 of file ixgbe_type.h.

#define IXGBE_LXONTXC 0x03F60

Definition at line 634 of file ixgbe_type.h.

#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0

Definition at line 1134 of file ixgbe_type.h.

#define IXGBE_MAC0_PTR 0x0B

Definition at line 1701 of file ixgbe_type.h.

#define IXGBE_MAC1_PTR 0x0C

Definition at line 1702 of file ixgbe_type.h.

#define IXGBE_MAC_D 4096

Definition at line 2440 of file ixgbe_type.h.

#define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */

Definition at line 2433 of file ixgbe_type.h.

#define IXGBE_MAC_RX2TX_LPBK 0x00000002

Definition at line 1587 of file ixgbe_type.h.

#define IXGBE_MACA 0x0424C

Definition at line 907 of file ixgbe_type.h.

#define IXGBE_MACC 0x04330

Definition at line 930 of file ixgbe_type.h.

#define IXGBE_MACC_FLU 0x00000001

Definition at line 1584 of file ixgbe_type.h.

#define IXGBE_MACC_FS 0x00040000

Definition at line 1586 of file ixgbe_type.h.

#define IXGBE_MACC_FSV_10G 0x00030000

Definition at line 1585 of file ixgbe_type.h.

#define IXGBE_MACS 0x0429C

Definition at line 922 of file ixgbe_type.h.

#define IXGBE_MANC 0x05820

Definition at line 718 of file ixgbe_type.h.

#define IXGBE_MANC2H 0x05860

Definition at line 720 of file ixgbe_type.h.

#define IXGBE_MAVTV ( _i ) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 716 of file ixgbe_type.h.

#define IXGBE_MAX_EITR 0x00000FF8

Definition at line 153 of file ixgbe_type.h.

#define IXGBE_MAX_ETQF_FILTERS 8

Definition at line 1447 of file ixgbe_type.h.

#define IXGBE_MAX_FRAME_SZ 0x40040000

Definition at line 1875 of file ixgbe_type.h.

#define IXGBE_MAX_FTQF_FILTERS 128

Definition at line 1408 of file ixgbe_type.h.

#define IXGBE_MAX_INT_RATE 488281

Definition at line 151 of file ixgbe_type.h.

#define IXGBE_MAX_MSIX_VECTORS_82598 0x13

Definition at line 1731 of file ixgbe_type.h.

#define IXGBE_MAX_MSIX_VECTORS_82599 0x40

Definition at line 1729 of file ixgbe_type.h.

#define IXGBE_MAX_MTA 128

Definition at line 2909 of file ixgbe_type.h.

#define IXGBE_MAX_PB 8

Definition at line 1174 of file ixgbe_type.h.

#define IXGBE_MAX_PHY_ADDR 32

Definition at line 1123 of file ixgbe_type.h.

#define IXGBE_MAX_SENSORS 3

Definition at line 122 of file ixgbe_type.h.

#define IXGBE_MAXFRS 0x04268

Definition at line 915 of file ixgbe_type.h.

#define IXGBE_MBVFICR ( _i ) (0x00710 + ((_i) * 4))

Definition at line 2155 of file ixgbe_type.h.

#define IXGBE_MBVFICR_INDEX ( vf_number ) (vf_number >> 4)

Definition at line 2154 of file ixgbe_type.h.

#define IXGBE_MCSTCTRL 0x05090

Definition at line 249 of file ixgbe_type.h.

#define IXGBE_MCSTCTRL_MFE 0x4

Definition at line 2140 of file ixgbe_type.h.

#define IXGBE_MDEF ( _i ) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 721 of file ixgbe_type.h.

#define IXGBE_MDEF_EXT ( _i ) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 727 of file ixgbe_type.h.

#define IXGBE_MDFTC1 0x042B8

Definition at line 862 of file ixgbe_type.h.

#define IXGBE_MDFTC2 0x042C0

Definition at line 863 of file ixgbe_type.h.

#define IXGBE_MDFTFIFO1 0x042C4

Definition at line 864 of file ixgbe_type.h.

#define IXGBE_MDFTFIFO2 0x042C8

Definition at line 865 of file ixgbe_type.h.

#define IXGBE_MDFTS 0x042CC

Definition at line 866 of file ixgbe_type.h.

#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */

Definition at line 1102 of file ixgbe_type.h.

#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */

Definition at line 1111 of file ixgbe_type.h.

#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */

Definition at line 1112 of file ixgbe_type.h.

#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */

Definition at line 1113 of file ixgbe_type.h.

#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018

Definition at line 1108 of file ixgbe_type.h.

#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010

Definition at line 1109 of file ixgbe_type.h.

#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */

Definition at line 1104 of file ixgbe_type.h.

#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */

Definition at line 1106 of file ixgbe_type.h.

#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */

Definition at line 1107 of file ixgbe_type.h.

#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */

Definition at line 1105 of file ixgbe_type.h.

#define IXGBE_METF ( _i ) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */

Definition at line 726 of file ixgbe_type.h.

#define IXGBE_MFLCN 0x04294

Definition at line 920 of file ixgbe_type.h.

#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */

Definition at line 1933 of file ixgbe_type.h.

#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */

Definition at line 1932 of file ixgbe_type.h.

#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */

Definition at line 1935 of file ixgbe_type.h.

#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */

Definition at line 1934 of file ixgbe_type.h.

#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Receive FC Mask */

Definition at line 1936 of file ixgbe_type.h.

#define IXGBE_MFLCN_RPFCE_SHIFT 4

Definition at line 1938 of file ixgbe_type.h.

#define IXGBE_MFUTP ( _i ) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 717 of file ixgbe_type.h.

#define IXGBE_MFVAL 0x05824

Definition at line 719 of file ixgbe_type.h.

#define IXGBE_MHADD 0x04268

Definition at line 914 of file ixgbe_type.h.

#define IXGBE_MHADD_MFS_MASK 0xFFFF0000

Definition at line 1023 of file ixgbe_type.h.

#define IXGBE_MHADD_MFS_SHIFT 16

Definition at line 1024 of file ixgbe_type.h.

#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/

Definition at line 1119 of file ixgbe_type.h.

#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/

Definition at line 1118 of file ixgbe_type.h.

#define IXGBE_MII_AUTONEG_REG 0x0

Definition at line 1120 of file ixgbe_type.h.

#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */

Definition at line 1116 of file ixgbe_type.h.

#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */

Definition at line 1117 of file ixgbe_type.h.

#define IXGBE_MIN_EITR 8

Definition at line 154 of file ixgbe_type.h.

#define IXGBE_MIN_INT_RATE 956

Definition at line 152 of file ixgbe_type.h.

#define IXGBE_MIPAF 0x058B0

Definition at line 722 of file ixgbe_type.h.

#define IXGBE_MISC_REG_82599 0x110F0

Definition at line 785 of file ixgbe_type.h.

#define IXGBE_MLADD 0x04264

Definition at line 913 of file ixgbe_type.h.

#define IXGBE_MLFC 0x04034

Definition at line 631 of file ixgbe_type.h.

#define IXGBE_MMAH ( _i ) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */

Definition at line 724 of file ixgbe_type.h.

#define IXGBE_MMAL ( _i ) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */

Definition at line 723 of file ixgbe_type.h.

#define IXGBE_MMNGC 0x042D0

Definition at line 932 of file ixgbe_type.h.

#define IXGBE_MNGPDC 0x040B8

Definition at line 667 of file ixgbe_type.h.

#define IXGBE_MNGPRC 0x040B4

Definition at line 666 of file ixgbe_type.h.

#define IXGBE_MNGPTC 0x0CF90

Definition at line 668 of file ixgbe_type.h.

#define IXGBE_MNGTXMAP 0x0CD10

Definition at line 354 of file ixgbe_type.h.

#define IXGBE_MPC ( _i ) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/

Definition at line 630 of file ixgbe_type.h.

#define IXGBE_MPRC 0x0407C

Definition at line 655 of file ixgbe_type.h.

#define IXGBE_MPSAR_HI ( _i ) (0x0A604 + ((_i) * 8))

Definition at line 239 of file ixgbe_type.h.

#define IXGBE_MPSAR_LO ( _i ) (0x0A600 + ((_i) * 8))

Definition at line 238 of file ixgbe_type.h.

#define IXGBE_MPTC 0x040F0

Definition at line 679 of file ixgbe_type.h.

#define IXGBE_MPVC 0x04318

Definition at line 940 of file ixgbe_type.h.

#define IXGBE_MRCTL ( _i ) (0x0F600 + ((_i) * 4))

Definition at line 275 of file ixgbe_type.h.

#define IXGBE_MREVID 0x11064

Definition at line 764 of file ixgbe_type.h.

#define IXGBE_MRFC 0x04038

Definition at line 632 of file ixgbe_type.h.

#define IXGBE_MRQC 0x05818

Definition at line 250 of file ixgbe_type.h.

#define IXGBE_MRQC_L3L4TXSWEN 0x00008000

Definition at line 1962 of file ixgbe_type.h.

#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */

Definition at line 1942 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000

Definition at line 1954 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000

Definition at line 1953 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000

Definition at line 1959 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000

Definition at line 1957 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000

Definition at line 1956 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000

Definition at line 1955 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000

Definition at line 1961 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000

Definition at line 1958 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000

Definition at line 1960 of file ixgbe_type.h.

#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000

Definition at line 1952 of file ixgbe_type.h.

#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */

Definition at line 1941 of file ixgbe_type.h.

#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */

Definition at line 1944 of file ixgbe_type.h.

#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */

Definition at line 1943 of file ixgbe_type.h.

#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */

Definition at line 1946 of file ixgbe_type.h.

#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */

Definition at line 1945 of file ixgbe_type.h.

#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */

Definition at line 1947 of file ixgbe_type.h.

#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */

Definition at line 1948 of file ixgbe_type.h.

#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */

Definition at line 1949 of file ixgbe_type.h.

#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */

Definition at line 1951 of file ixgbe_type.h.

#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */

Definition at line 1950 of file ixgbe_type.h.

#define IXGBE_MSCA 0x0425C

Definition at line 911 of file ixgbe_type.h.

#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */

Definition at line 1067 of file ixgbe_type.h.

#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */

Definition at line 1061 of file ixgbe_type.h.

#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */

Definition at line 1062 of file ixgbe_type.h.

#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */

Definition at line 1075 of file ixgbe_type.h.

#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */

Definition at line 1076 of file ixgbe_type.h.

#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */

Definition at line 1073 of file ixgbe_type.h.

#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */

Definition at line 1059 of file ixgbe_type.h.

#define IXGBE_MSCA_NP_ADDR_SHIFT 0

Definition at line 1060 of file ixgbe_type.h.

#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */

Definition at line 1074 of file ixgbe_type.h.

#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */

Definition at line 1065 of file ixgbe_type.h.

#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */

Definition at line 1066 of file ixgbe_type.h.

#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */

Definition at line 1063 of file ixgbe_type.h.

#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/

Definition at line 1064 of file ixgbe_type.h.

#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */

Definition at line 1069 of file ixgbe_type.h.

#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/

Definition at line 1070 of file ixgbe_type.h.

#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */

Definition at line 1071 of file ixgbe_type.h.

#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */

Definition at line 1072 of file ixgbe_type.h.

#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */

Definition at line 1068 of file ixgbe_type.h.

#define IXGBE_MSIX_VECTOR ( _i ) (0 + (_i))

Definition at line 1442 of file ixgbe_type.h.

#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */

Definition at line 164 of file ixgbe_type.h.

#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */

Definition at line 163 of file ixgbe_type.h.

#define IXGBE_MSPDC 0x04010

Definition at line 629 of file ixgbe_type.h.

#define IXGBE_MSRWD 0x04260

Definition at line 912 of file ixgbe_type.h.

#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000

Definition at line 1081 of file ixgbe_type.h.

#define IXGBE_MSRWD_READ_DATA_SHIFT 16

Definition at line 1082 of file ixgbe_type.h.

#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF

Definition at line 1079 of file ixgbe_type.h.

#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0

Definition at line 1080 of file ixgbe_type.h.

#define IXGBE_MTA ( _i ) (0x05200 + ((_i) * 4))

Definition at line 233 of file ixgbe_type.h.

#define IXGBE_MTQC 0x08120

Definition at line 259 of file ixgbe_type.h.

#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */

Definition at line 1988 of file ixgbe_type.h.

#define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */

Definition at line 1991 of file ixgbe_type.h.

#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */

Definition at line 1987 of file ixgbe_type.h.

#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */

Definition at line 1989 of file ixgbe_type.h.

#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */

Definition at line 1990 of file ixgbe_type.h.

#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */

Definition at line 1985 of file ixgbe_type.h.

#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */

Definition at line 1986 of file ixgbe_type.h.

#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF

Definition at line 3039 of file ixgbe_type.h.

#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */

Definition at line 1762 of file ixgbe_type.h.

#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */

Definition at line 1761 of file ixgbe_type.h.

#define IXGBE_O2BGPTC 0x041C4

Definition at line 705 of file ixgbe_type.h.

#define IXGBE_O2BSPC 0x087B0

Definition at line 706 of file ixgbe_type.h.

#define IXGBE_OPTION_ROM_PTR 0x05

Definition at line 1695 of file ixgbe_type.h.

#define IXGBE_PAP 0x04248

Definition at line 906 of file ixgbe_type.h.

#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */

Definition at line 1285 of file ixgbe_type.h.

#define IXGBE_PBACL ( _i ) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))

Definition at line 165 of file ixgbe_type.h.

#define IXGBE_PBACLR_82599 0x11068

Definition at line 778 of file ixgbe_type.h.

#define IXGBE_PBANUM0_PTR 0x15

Definition at line 1706 of file ixgbe_type.h.

#define IXGBE_PBANUM1_PTR 0x16

Definition at line 1707 of file ixgbe_type.h.

#define IXGBE_PBANUM_LENGTH 11

Definition at line 1685 of file ixgbe_type.h.

#define IXGBE_PBANUM_PTR_GUARD 0xFAFA

Definition at line 1688 of file ixgbe_type.h.

#define IXGBE_PBRXECC 0x03300

Definition at line 891 of file ixgbe_type.h.

#define IXGBE_PBTXECC 0x0C300

Definition at line 890 of file ixgbe_type.h.

#define IXGBE_PCI_DELAY 10000

Definition at line 2449 of file ixgbe_type.h.

#define IXGBE_PCI_DEVICE_CONTROL2 0xC8

Definition at line 1819 of file ixgbe_type.h.

#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005

Definition at line 1830 of file ixgbe_type.h.

#define IXGBE_PCI_DEVICE_STATUS 0xAA

Definition at line 1816 of file ixgbe_type.h.

#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020

Definition at line 1817 of file ixgbe_type.h.

#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80

Definition at line 1829 of file ixgbe_type.h.

#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E

Definition at line 1828 of file ixgbe_type.h.

#define IXGBE_PCI_LINK_SPEED 0xF

Definition at line 1825 of file ixgbe_type.h.

#define IXGBE_PCI_LINK_SPEED_2500 0x1

Definition at line 1826 of file ixgbe_type.h.

#define IXGBE_PCI_LINK_SPEED_5000 0x2

Definition at line 1827 of file ixgbe_type.h.

#define IXGBE_PCI_LINK_STATUS 0xB2

Definition at line 1818 of file ixgbe_type.h.

#define IXGBE_PCI_LINK_WIDTH 0x3F0

Definition at line 1820 of file ixgbe_type.h.

#define IXGBE_PCI_LINK_WIDTH_1 0x10

Definition at line 1821 of file ixgbe_type.h.

#define IXGBE_PCI_LINK_WIDTH_2 0x20

Definition at line 1822 of file ixgbe_type.h.

#define IXGBE_PCI_LINK_WIDTH_4 0x40

Definition at line 1823 of file ixgbe_type.h.

#define IXGBE_PCI_LINK_WIDTH_8 0x80

Definition at line 1824 of file ixgbe_type.h.

#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800

Definition at line 1833 of file ixgbe_type.h.

#define IXGBE_PCIE_ANALOG_PTR 0x03

Definition at line 1691 of file ixgbe_type.h.

#define IXGBE_PCIE_CONFIG0_PTR 0x07

Definition at line 1697 of file ixgbe_type.h.

#define IXGBE_PCIE_CONFIG1_PTR 0x08

Definition at line 1698 of file ixgbe_type.h.

#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */

Definition at line 1783 of file ixgbe_type.h.

#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */

Definition at line 1786 of file ixgbe_type.h.

#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */

Definition at line 1784 of file ixgbe_type.h.

#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */

Definition at line 1785 of file ixgbe_type.h.

#define IXGBE_PCIE_DIAG ( _i ) (0x11090 + ((_i) * 4)) /* 8 of these */

Definition at line 860 of file ixgbe_type.h.

#define IXGBE_PCIE_GENERAL_PTR 0x06

Definition at line 1696 of file ixgbe_type.h.

#define IXGBE_PCIE_MSIX_82598_CAPS 0x62

Definition at line 1730 of file ixgbe_type.h.

#define IXGBE_PCIE_MSIX_82599_CAPS 0x72

Definition at line 1728 of file ixgbe_type.h.

#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF

Definition at line 1734 of file ixgbe_type.h.

#define IXGBE_PCIEANACTL 0x11040

Definition at line 760 of file ixgbe_type.h.

#define IXGBE_PCIEECCCTL 0x1106C

Definition at line 875 of file ixgbe_type.h.

#define IXGBE_PCIEECCCTL0 0x11100

Definition at line 884 of file ixgbe_type.h.

#define IXGBE_PCIEECCCTL1 0x11104

Definition at line 885 of file ixgbe_type.h.

#define IXGBE_PCIESPARE 0x110BC

Definition at line 784 of file ixgbe_type.h.

#define IXGBE_PCRC8ECH 0x0E811

Definition at line 710 of file ixgbe_type.h.

#define IXGBE_PCRC8ECH_MASK 0x1F

Definition at line 711 of file ixgbe_type.h.

#define IXGBE_PCRC8ECL 0x0E810

Definition at line 709 of file ixgbe_type.h.

#define IXGBE_PCS1GANA 0x04218

Definition at line 900 of file ixgbe_type.h.

#define IXGBE_PCS1GANA_ASM_PAUSE 0x100

Definition at line 1626 of file ixgbe_type.h.

#define IXGBE_PCS1GANA_SYM_PAUSE 0x80

Definition at line 1625 of file ixgbe_type.h.

#define IXGBE_PCS1GANLP 0x0421C

Definition at line 901 of file ixgbe_type.h.

#define IXGBE_PCS1GANLPNP 0x04224

Definition at line 903 of file ixgbe_type.h.

#define IXGBE_PCS1GANNP 0x04220

Definition at line 902 of file ixgbe_type.h.

#define IXGBE_PCS1GCFIG 0x04200

Definition at line 895 of file ixgbe_type.h.

#define IXGBE_PCS1GDBG0 0x04210

Definition at line 898 of file ixgbe_type.h.

#define IXGBE_PCS1GDBG1 0x04214

Definition at line 899 of file ixgbe_type.h.

#define IXGBE_PCS1GLCTL 0x04208

Definition at line 896 of file ixgbe_type.h.

#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */

Definition at line 1629 of file ixgbe_type.h.

#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000

Definition at line 1633 of file ixgbe_type.h.

#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000

Definition at line 1634 of file ixgbe_type.h.

#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1

Definition at line 1630 of file ixgbe_type.h.

#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20

Definition at line 1631 of file ixgbe_type.h.

#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40

Definition at line 1632 of file ixgbe_type.h.

#define IXGBE_PCS1GLSTA 0x0420C

Definition at line 897 of file ixgbe_type.h.

#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000

Definition at line 1619 of file ixgbe_type.h.

#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000

Definition at line 1623 of file ixgbe_type.h.

#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000

Definition at line 1620 of file ixgbe_type.h.

#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000

Definition at line 1622 of file ixgbe_type.h.

#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000

Definition at line 1621 of file ixgbe_type.h.

#define IXGBE_PCS1GLSTA_LINK_OK 1

Definition at line 1617 of file ixgbe_type.h.

#define IXGBE_PCS1GLSTA_SYNK_OK 0x10

Definition at line 1618 of file ixgbe_type.h.

#define IXGBE_PCSS1 0x04288

Definition at line 917 of file ixgbe_type.h.

#define IXGBE_PCSS2 0x0428C

Definition at line 918 of file ixgbe_type.h.

#define IXGBE_PDPMCS 0x0CD00

Definition at line 434 of file ixgbe_type.h.

#define IXGBE_PFC_D 672

Definition at line 2425 of file ixgbe_type.h.

#define IXGBE_PFCTOP 0x03008

Definition at line 175 of file ixgbe_type.h.

#define IXGBE_PFDTXGSWC 0x08220

Definition at line 329 of file ixgbe_type.h.

#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */

Definition at line 341 of file ixgbe_type.h.

#define IXGBE_PFMAILBOX ( _i ) (0x04B00 + (4 * (_i))) /* 64 total */

Definition at line 264 of file ixgbe_type.h.

#define IXGBE_PFMBICR ( _i ) (0x00710 + (4 * (_i))) /* 4 total */

Definition at line 266 of file ixgbe_type.h.

#define IXGBE_PFMBIMR ( _i ) (0x00720 + (4 * (_i))) /* 4 total */

Definition at line 267 of file ixgbe_type.h.

#define IXGBE_PFMBMEM ( _i ) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */

Definition at line 265 of file ixgbe_type.h.

#define IXGBE_PFVFSPOOF ( _i ) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */

Definition at line 328 of file ixgbe_type.h.

#define IXGBE_PFVFSPOOF_REG_COUNT 8

Definition at line 347 of file ixgbe_type.h.

#define IXGBE_PHY_D 12800

Definition at line 2439 of file ixgbe_type.h.

#define IXGBE_PHY_DC 25600 /* Delay 10G BASET */

Definition at line 2432 of file ixgbe_type.h.

#define IXGBE_PHY_INIT_END_NL 0xFFFF

Definition at line 1138 of file ixgbe_type.h.

#define IXGBE_PHY_INIT_OFFSET_NL 0x002B

Definition at line 1137 of file ixgbe_type.h.

#define IXGBE_PHY_PTR 0x04

Definition at line 1693 of file ixgbe_type.h.

#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0

Definition at line 1122 of file ixgbe_type.h.

#define IXGBE_PHYADR_82599 0x11040

Definition at line 775 of file ixgbe_type.h.

#define IXGBE_PHYCTL_82599 0x11048

Definition at line 777 of file ixgbe_type.h.

#define IXGBE_PHYDAT_82599 0x11044

Definition at line 776 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400

Definition at line 2411 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200

Definition at line 2410 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002

Definition at line 2402 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004

Definition at line 2403 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100

Definition at line 2409 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800

Definition at line 2412 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080

Definition at line 2408 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010

Definition at line 2405 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020

Definition at line 2406 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040

Definition at line 2407 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001

Definition at line 2401 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000

Definition at line 2413 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000

Definition at line 2414 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008

Definition at line 2404 of file ixgbe_type.h.

#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0

Definition at line 2400 of file ixgbe_type.h.

#define IXGBE_PICAUSE 0x110B0

Definition at line 781 of file ixgbe_type.h.

#define IXGBE_PIENA 0x110B8

Definition at line 782 of file ixgbe_type.h.

#define IXGBE_PRC1023 0x0406C

Definition at line 651 of file ixgbe_type.h.

#define IXGBE_PRC127 0x04060

Definition at line 648 of file ixgbe_type.h.

#define IXGBE_PRC1522 0x04070

Definition at line 652 of file ixgbe_type.h.

#define IXGBE_PRC255 0x04064

Definition at line 649 of file ixgbe_type.h.

#define IXGBE_PRC511 0x04068

Definition at line 650 of file ixgbe_type.h.

#define IXGBE_PRC64 0x0405C

Definition at line 647 of file ixgbe_type.h.

#define IXGBE_PSRTYPE ( _i )

Value:

(((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \

(0x0EA00 + ((_i) * 4)))

Definition at line 241 of file ixgbe_type.h.

#define IXGBE_PSRTYPE_IPV4HDR 0x00000100

Definition at line 2057 of file ixgbe_type.h.

#define IXGBE_PSRTYPE_IPV6HDR 0x00000200

Definition at line 2058 of file ixgbe_type.h.

#define IXGBE_PSRTYPE_L2HDR 0x00001000

Definition at line 2059 of file ixgbe_type.h.

#define IXGBE_PSRTYPE_RQPL_MASK 0x7

Definition at line 1010 of file ixgbe_type.h.

#define IXGBE_PSRTYPE_RQPL_SHIFT 29

Definition at line 1011 of file ixgbe_type.h.

#define IXGBE_PSRTYPE_TCPHDR 0x00000010

Definition at line 2055 of file ixgbe_type.h.

#define IXGBE_PSRTYPE_UDPHDR 0x00000020

Definition at line 2056 of file ixgbe_type.h.

#define IXGBE_PTC1023 0x040E8

Definition at line 677 of file ixgbe_type.h.

#define IXGBE_PTC127 0x040DC

Definition at line 674 of file ixgbe_type.h.

#define IXGBE_PTC1522 0x040EC

Definition at line 678 of file ixgbe_type.h.

#define IXGBE_PTC255 0x040E0

Definition at line 675 of file ixgbe_type.h.

#define IXGBE_PTC511 0x040E4

Definition at line 676 of file ixgbe_type.h.

#define IXGBE_PTC64 0x040D8

Definition at line 673 of file ixgbe_type.h.

#define IXGBE_PXOFFRXC ( _i ) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/

Definition at line 646 of file ixgbe_type.h.

#define IXGBE_PXOFFRXCNT ( _i ) (0x04160 + ((_i) * 4)) /* 8 of these */

Definition at line 641 of file ixgbe_type.h.

#define IXGBE_PXOFFTXC ( _i ) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/

Definition at line 645 of file ixgbe_type.h.

#define IXGBE_PXON2OFFCNT ( _i ) (0x03240 + ((_i) * 4)) /* 8 of these */

Definition at line 642 of file ixgbe_type.h.

#define IXGBE_PXONRXC ( _i ) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/

Definition at line 644 of file ixgbe_type.h.

#define IXGBE_PXONRXCNT ( _i ) (0x04140 + ((_i) * 4)) /* 8 of these */

Definition at line 640 of file ixgbe_type.h.

#define IXGBE_PXONTXC ( _i ) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/

Definition at line 643 of file ixgbe_type.h.

#define IXGBE_QBRC ( _i ) (0x01034 + ((_i) * 0x40)) /* 16 of these */

Definition at line 691 of file ixgbe_type.h.

#define IXGBE_QBRC_H ( _i ) (0x01038 + ((_i) * 0x40)) /* 16 of these */

Definition at line 694 of file ixgbe_type.h.

#define IXGBE_QBRC_L ( _i ) (0x01034 + ((_i) * 0x40)) /* 16 of these */

Definition at line 693 of file ixgbe_type.h.

#define IXGBE_QBTC ( _i ) (0x06034 + ((_i) * 0x40)) /* 16 of these */

Definition at line 692 of file ixgbe_type.h.

#define IXGBE_QBTC_H ( _i ) (0x08704 + ((_i) * 0x8)) /* 16 of these */

Definition at line 697 of file ixgbe_type.h.

#define IXGBE_QBTC_L ( _i ) (0x08700 + ((_i) * 0x8)) /* 16 of these */

Definition at line 696 of file ixgbe_type.h.

#define IXGBE_QDE 0x2F04

Definition at line 271 of file ixgbe_type.h.

#define IXGBE_QDE_ENABLE 0x00000001

Definition at line 1965 of file ixgbe_type.h.

#define IXGBE_QDE_IDX_MASK 0x00007F00

Definition at line 1966 of file ixgbe_type.h.

#define IXGBE_QDE_IDX_SHIFT 8

Definition at line 1967 of file ixgbe_type.h.

#define IXGBE_QPRC ( _i ) (0x01030 + ((_i) * 0x40)) /* 16 of these */

Definition at line 689 of file ixgbe_type.h.

#define IXGBE_QPRDC ( _i ) (0x01430 + ((_i) * 0x40)) /* 16 of these */

Definition at line 695 of file ixgbe_type.h.

#define IXGBE_QPTC ( _i ) (0x06030 + ((_i) * 0x40)) /* 16 of these */

Definition at line 690 of file ixgbe_type.h.

#define IXGBE_RAH ( _i )

Value:

(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \

(0x0A204 + ((_i) * 8)))

Definition at line 236 of file ixgbe_type.h.

#define IXGBE_RAH_AV 0x80000000

Definition at line 1847 of file ixgbe_type.h.

#define IXGBE_RAH_VIND_MASK 0x003C0000

Definition at line 1845 of file ixgbe_type.h.

#define IXGBE_RAH_VIND_SHIFT 18

Definition at line 1846 of file ixgbe_type.h.

#define IXGBE_RAL ( _i )

Value:

(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \

(0x0A200 + ((_i) * 8)))

Definition at line 234 of file ixgbe_type.h.

#define IXGBE_RDBAH ( _i )

Value:

(((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \

(0x0D004 + (((_i) - 64) * 0x40)))

Definition at line 186 of file ixgbe_type.h.

#define IXGBE_RDBAL ( _i )

Value:

(((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \

(0x0D000 + (((_i) - 64) * 0x40)))

Definition at line 184 of file ixgbe_type.h.

#define IXGBE_RDDCC 0x02F20

Definition at line 199 of file ixgbe_type.h.

#define IXGBE_RDH ( _i )

Value:

(((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \

(0x0D010 + (((_i) - 64) * 0x40)))

Definition at line 190 of file ixgbe_type.h.

#define IXGBE_RDHMPN 0x02F08

Definition at line 837 of file ixgbe_type.h.

#define IXGBE_RDHMPN_RDICADDR 0x007FF800

Definition at line 1243 of file ixgbe_type.h.

#define IXGBE_RDHMPN_RDICADDR_SHIFT 11

Definition at line 1245 of file ixgbe_type.h.

#define IXGBE_RDHMPN_RDICRDREQ 0x00800000

Definition at line 1244 of file ixgbe_type.h.

#define IXGBE_RDLEN ( _i )

Value:

(((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \

(0x0D008 + (((_i) - 64) * 0x40)))

Definition at line 188 of file ixgbe_type.h.

#define IXGBE_RDMAD 0x02F34

Definition at line 841 of file ixgbe_type.h.

#define IXGBE_RDMAM 0x02F30

Definition at line 840 of file ixgbe_type.h.

#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4

Definition at line 1260 of file ixgbe_type.h.

#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135

Definition at line 1259 of file ixgbe_type.h.

#define IXGBE_RDMAM_DESC_COMP_FIFO 1

Definition at line 1252 of file ixgbe_type.h.

#define IXGBE_RDMAM_DFC_CMD_FIFO 2

Definition at line 1253 of file ixgbe_type.h.

#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7

Definition at line 1262 of file ixgbe_type.h.

#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48

Definition at line 1261 of file ixgbe_type.h.

#define IXGBE_RDMAM_DWORD_SHIFT 9

Definition at line 1251 of file ixgbe_type.h.

#define IXGBE_RDMAM_MEM_SEL_SHIFT 13

Definition at line 1250 of file ixgbe_type.h.

#define IXGBE_RDMAM_QSC_CNT_RAM 6

Definition at line 1256 of file ixgbe_type.h.

#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4

Definition at line 1268 of file ixgbe_type.h.

#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64

Definition at line 1267 of file ixgbe_type.h.

#define IXGBE_RDMAM_QSC_QUEUE_CNT 8

Definition at line 1257 of file ixgbe_type.h.

#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4

Definition at line 1270 of file ixgbe_type.h.

#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32

Definition at line 1269 of file ixgbe_type.h.

#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA

Definition at line 1258 of file ixgbe_type.h.

#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8

Definition at line 1272 of file ixgbe_type.h.

#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128

Definition at line 1271 of file ixgbe_type.h.

#define IXGBE_RDMAM_TCN_STATUS_RAM 4

Definition at line 1254 of file ixgbe_type.h.

#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9

Definition at line 1264 of file ixgbe_type.h.

#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256

Definition at line 1263 of file ixgbe_type.h.

#define IXGBE_RDMAM_WB_COLL_FIFO 5

Definition at line 1255 of file ixgbe_type.h.

#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4

Definition at line 1266 of file ixgbe_type.h.

#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8

Definition at line 1265 of file ixgbe_type.h.

#define IXGBE_RDPROBE 0x02F20

Definition at line 839 of file ixgbe_type.h.

#define IXGBE_RDRXCTL 0x02F00

Definition at line 220 of file ixgbe_type.h.

#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */

Definition at line 992 of file ixgbe_type.h.

#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */

Definition at line 989 of file ixgbe_type.h.

#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */

Definition at line 991 of file ixgbe_type.h.

#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */

Definition at line 996 of file ixgbe_type.h.

#define IXGBE_RDRXCTL_MVMEN 0x00000020

Definition at line 990 of file ixgbe_type.h.

#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */

Definition at line 988 of file ixgbe_type.h.

#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */

Definition at line 995 of file ixgbe_type.h.

#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */

Definition at line 993 of file ixgbe_type.h.

#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */

Definition at line 994 of file ixgbe_type.h.

#define IXGBE_RDSTAT ( _i ) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */

Definition at line 836 of file ixgbe_type.h.

#define IXGBE_RDSTATCTL 0x02C20

Definition at line 835 of file ixgbe_type.h.

#define IXGBE_RDT ( _i )

Value:

(((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \

(0x0D018 + (((_i) - 64) * 0x40)))

Definition at line 192 of file ixgbe_type.h.

#define IXGBE_REOFF 0x05158 /* Rx FC EOF */

Definition at line 592 of file ixgbe_type.h.

#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8

Definition at line 2144 of file ixgbe_type.h.

#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024

Definition at line 2145 of file ixgbe_type.h.

#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8

Definition at line 2143 of file ixgbe_type.h.

#define IXGBE_RETA ( _i ) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */

Definition at line 285 of file ixgbe_type.h.

#define IXGBE_RFC 0x040A8

Definition at line 663 of file ixgbe_type.h.

#define IXGBE_RFCTL 0x05008

Definition at line 229 of file ixgbe_type.h.

#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000

Definition at line 1863 of file ixgbe_type.h.

#define IXGBE_RFCTL_IPV6_DIS 0x00000400

Definition at line 1861 of file ixgbe_type.h.

#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000

Definition at line 1864 of file ixgbe_type.h.

#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800

Definition at line 1862 of file ixgbe_type.h.

#define IXGBE_RFCTL_ISCSI_DIS 0x00000001

Definition at line 1851 of file ixgbe_type.h.

#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E

Definition at line 1852 of file ixgbe_type.h.

#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1

Definition at line 1853 of file ixgbe_type.h.

#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000

Definition at line 1865 of file ixgbe_type.h.

#define IXGBE_RFCTL_NFS_VER_2 0

Definition at line 1858 of file ixgbe_type.h.

#define IXGBE_RFCTL_NFS_VER_3 1

Definition at line 1859 of file ixgbe_type.h.

#define IXGBE_RFCTL_NFS_VER_4 2

Definition at line 1860 of file ixgbe_type.h.

#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300

Definition at line 1856 of file ixgbe_type.h.

#define IXGBE_RFCTL_NFS_VER_SHIFT 8

Definition at line 1857 of file ixgbe_type.h.

#define IXGBE_RFCTL_NFSR_DIS 0x00000080

Definition at line 1855 of file ixgbe_type.h.

#define IXGBE_RFCTL_NFSW_DIS 0x00000040

Definition at line 1854 of file ixgbe_type.h.

#define IXGBE_RFVAL 0x050A4

Definition at line 861 of file ixgbe_type.h.

#define IXGBE_RIC_DW ( _i ) (0x02F10 + ((_i) * 4))

Definition at line 838 of file ixgbe_type.h.

#define IXGBE_RJC 0x040B0

Definition at line 665 of file ixgbe_type.h.

#define IXGBE_RLEC 0x04040

Definition at line 633 of file ixgbe_type.h.

#define IXGBE_RMCS 0x03D00

Definition at line 432 of file ixgbe_type.h.

#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */

Definition at line 1294 of file ixgbe_type.h.

#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */

Definition at line 1291 of file ixgbe_type.h.

#define IXGBE_RMCS_RAC 0x00000004

Definition at line 1290 of file ixgbe_type.h.

#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */

Definition at line 1288 of file ixgbe_type.h.

#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */

Definition at line 1292 of file ixgbe_type.h.

#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */

Definition at line 1293 of file ixgbe_type.h.

#define IXGBE_RNBC ( _i ) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/

Definition at line 661 of file ixgbe_type.h.

#define IXGBE_ROC 0x040AC

Definition at line 664 of file ixgbe_type.h.

#define IXGBE_RQSMR ( _i ) (0x02300 + ((_i) * 4))

Definition at line 684 of file ixgbe_type.h.

#define IXGBE_RQTC 0x0EC70

Definition at line 258 of file ixgbe_type.h.

#define IXGBE_RQTC_SHIFT_TC ( _i ) ((_i) * 4)

Definition at line 999 of file ixgbe_type.h.

#define IXGBE_RQTC_TC0_MASK (0x7 << 0)

Definition at line 1000 of file ixgbe_type.h.

#define IXGBE_RQTC_TC1_MASK (0x7 << 4)

Definition at line 1001 of file ixgbe_type.h.

#define IXGBE_RQTC_TC2_MASK (0x7 << 8)

Definition at line 1002 of file ixgbe_type.h.

#define IXGBE_RQTC_TC3_MASK (0x7 << 12)

Definition at line 1003 of file ixgbe_type.h.

#define IXGBE_RQTC_TC4_MASK (0x7 << 16)

Definition at line 1004 of file ixgbe_type.h.

#define IXGBE_RQTC_TC5_MASK (0x7 << 20)

Definition at line 1005 of file ixgbe_type.h.

#define IXGBE_RQTC_TC6_MASK (0x7 << 24)

Definition at line 1006 of file ixgbe_type.h.

#define IXGBE_RQTC_TC7_MASK (0x7 << 28)

Definition at line 1007 of file ixgbe_type.h.

#define IXGBE_RSCCTL ( _i )

Value:

(((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \

(0x0D02C + (((_i) - 64) * 0x40)))

Definition at line 196 of file ixgbe_type.h.

#define IXGBE_RSCCTL_MAXDESC_1 0x00

Definition at line 978 of file ixgbe_type.h.

#define IXGBE_RSCCTL_MAXDESC_16 0x0C

Definition at line 981 of file ixgbe_type.h.

#define IXGBE_RSCCTL_MAXDESC_4 0x04

Definition at line 979 of file ixgbe_type.h.

#define IXGBE_RSCCTL_MAXDESC_8 0x08

Definition at line 980 of file ixgbe_type.h.

#define IXGBE_RSCCTL_RSCEN 0x01

Definition at line 977 of file ixgbe_type.h.

#define IXGBE_RSCDBU 0x03028

Definition at line 198 of file ixgbe_type.h.

#define IXGBE_RSCDBU_RSCACKDIS 0x00000080

Definition at line 985 of file ixgbe_type.h.

#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F

Definition at line 984 of file ixgbe_type.h.

#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */

Definition at line 593 of file ixgbe_type.h.

#define IXGBE_RSSRK ( _i ) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */

Definition at line 286 of file ixgbe_type.h.

#define IXGBE_RT2CR ( _i ) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 436 of file ixgbe_type.h.

#define IXGBE_RT2SR ( _i ) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 437 of file ixgbe_type.h.

#define IXGBE_RTRPCS 0x02430

Definition at line 542 of file ixgbe_type.h.

#define IXGBE_RTRPT4C ( _i ) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 548 of file ixgbe_type.h.

#define IXGBE_RTRPT4S ( _i ) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 550 of file ixgbe_type.h.

#define IXGBE_RTRUP2TC 0x03020

Definition at line 546 of file ixgbe_type.h.

#define IXGBE_RTTBCNRC 0x04984

Definition at line 560 of file ixgbe_type.h.

#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF

Definition at line 562 of file ixgbe_type.h.

#define IXGBE_RTTBCNRC_RF_INT_MASK (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)

Definition at line 564 of file ixgbe_type.h.

#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14

Definition at line 563 of file ixgbe_type.h.

#define IXGBE_RTTBCNRC_RS_ENA 0x80000000

Definition at line 561 of file ixgbe_type.h.

#define IXGBE_RTTBCNRM 0x04980

Definition at line 566 of file ixgbe_type.h.

#define IXGBE_RTTDCS 0x04900

Definition at line 543 of file ixgbe_type.h.

#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */

Definition at line 544 of file ixgbe_type.h.

#define IXGBE_RTTDQSEL 0x04904

Definition at line 555 of file ixgbe_type.h.

#define IXGBE_RTTDT1C 0x04908

Definition at line 556 of file ixgbe_type.h.

#define IXGBE_RTTDT1S 0x0490C

Definition at line 557 of file ixgbe_type.h.

#define IXGBE_RTTDT2C ( _i ) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 551 of file ixgbe_type.h.

#define IXGBE_RTTDT2S ( _i ) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 552 of file ixgbe_type.h.

#define IXGBE_RTTDTECC 0x04990

Definition at line 558 of file ixgbe_type.h.

#define IXGBE_RTTDTECC_NO_BCN 0x00000100

Definition at line 559 of file ixgbe_type.h.

#define IXGBE_RTTPCS 0x0CD00

Definition at line 545 of file ixgbe_type.h.

#define IXGBE_RTTPT2C ( _i ) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 553 of file ixgbe_type.h.

#define IXGBE_RTTPT2S ( _i ) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 554 of file ixgbe_type.h.

#define IXGBE_RTTUP2TC 0x0C800

Definition at line 547 of file ixgbe_type.h.

#define IXGBE_RUC 0x040A4

Definition at line 662 of file ixgbe_type.h.

#define IXGBE_RUPPBMR 0x050A0

Definition at line 435 of file ixgbe_type.h.

#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */

Definition at line 2149 of file ixgbe_type.h.

#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */

Definition at line 2150 of file ixgbe_type.h.

#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */

Definition at line 2148 of file ixgbe_type.h.

#define IXGBE_RXBUFCTRL 0x03600

Definition at line 855 of file ixgbe_type.h.

#define IXGBE_RXBUFDATA0 0x03610

Definition at line 856 of file ixgbe_type.h.

#define IXGBE_RXBUFDATA1 0x03614

Definition at line 857 of file ixgbe_type.h.

#define IXGBE_RXBUFDATA2 0x03618

Definition at line 858 of file ixgbe_type.h.

#define IXGBE_RXBUFDATA3 0x0361C

Definition at line 859 of file ixgbe_type.h.

#define IXGBE_RXCSUM 0x05000

Definition at line 228 of file ixgbe_type.h.

#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */

Definition at line 1277 of file ixgbe_type.h.

#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */

Definition at line 1278 of file ixgbe_type.h.

#define IXGBE_RXCTRL 0x03000

Definition at line 223 of file ixgbe_type.h.

#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */

Definition at line 1882 of file ixgbe_type.h.

#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */

Definition at line 1881 of file ixgbe_type.h.

#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */

Definition at line 2038 of file ixgbe_type.h.

#define IXGBE_RXD_CFI_SHIFT 12

Definition at line 2039 of file ixgbe_type.h.

#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */

Definition at line 2013 of file ixgbe_type.h.

#define IXGBE_RXD_ERR_FRAME_ERR_MASK

Value:

( \
                                      IXGBE_RXD_ERR_CE | \
                                      IXGBE_RXD_ERR_LE | \
                                      IXGBE_RXD_ERR_PE | \
                                      IXGBE_RXD_ERR_OSE | \
                                      IXGBE_RXD_ERR_USE)

Definition at line 2125 of file ixgbe_type.h.

#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */

Definition at line 2019 of file ixgbe_type.h.

#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */

Definition at line 2014 of file ixgbe_type.h.

#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */

Definition at line 2016 of file ixgbe_type.h.

#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */

Definition at line 2015 of file ixgbe_type.h.

#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */

Definition at line 2018 of file ixgbe_type.h.

#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */

Definition at line 2017 of file ixgbe_type.h.

#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */

Definition at line 2036 of file ixgbe_type.h.

#define IXGBE_RXD_PRI_SHIFT 13

Definition at line 2037 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */

Definition at line 2012 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */

Definition at line 2004 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */

Definition at line 1994 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */

Definition at line 2007 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */

Definition at line 1995 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */

Definition at line 1996 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */

Definition at line 2002 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */

Definition at line 2001 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */

Definition at line 2011 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */

Definition at line 2008 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */

Definition at line 2003 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */

Definition at line 2010 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */

Definition at line 2009 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */

Definition at line 2000 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */

Definition at line 2006 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */

Definition at line 2005 of file ixgbe_type.h.

#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */

Definition at line 1997 of file ixgbe_type.h.

#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */

Definition at line 2035 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */

Definition at line 2028 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */

Definition at line 2022 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */

Definition at line 2023 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */

Definition at line 2026 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */

Definition at line 2025 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */

Definition at line 2024 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK

Value:

( \
                                      IXGBE_RXDADV_ERR_CE | \
                                      IXGBE_RXDADV_ERR_LE | \
                                      IXGBE_RXDADV_ERR_PE | \
                                      IXGBE_RXDADV_ERR_OSE | \
                                      IXGBE_RXDADV_ERR_USE)

Definition at line 2132 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */

Definition at line 2027 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */

Definition at line 2034 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */

Definition at line 2029 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */

Definition at line 2020 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */

Definition at line 2031 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */

Definition at line 2030 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */

Definition at line 2021 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */

Definition at line 2033 of file ixgbe_type.h.

#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */

Definition at line 2032 of file ixgbe_type.h.

#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0

Definition at line 2081 of file ixgbe_type.h.

#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5

Definition at line 2084 of file ixgbe_type.h.

#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000

Definition at line 1982 of file ixgbe_type.h.

#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000

Definition at line 1983 of file ixgbe_type.h.

#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000

Definition at line 1981 of file ixgbe_type.h.

#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000

Definition at line 1980 of file ixgbe_type.h.

#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000

Definition at line 1979 of file ixgbe_type.h.

#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000

Definition at line 2122 of file ixgbe_type.h.

#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000

Definition at line 2121 of file ixgbe_type.h.

#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000

Definition at line 2119 of file ixgbe_type.h.

#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000

Definition at line 2120 of file ixgbe_type.h.

#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000

Definition at line 2118 of file ixgbe_type.h.

#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */

Definition at line 1998 of file ixgbe_type.h.

#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004

Definition at line 1999 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */

Definition at line 2113 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */

Definition at line 2114 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */

Definition at line 2115 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */

Definition at line 2111 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */

Definition at line 2110 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */

Definition at line 2102 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */

Definition at line 2103 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */

Definition at line 2104 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */

Definition at line 2105 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */

Definition at line 2112 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0

Definition at line 2079 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0

Definition at line 2080 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */

Definition at line 2109 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000

Definition at line 2101 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */

Definition at line 2108 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */

Definition at line 2106 of file ixgbe_type.h.

#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */

Definition at line 2107 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000

Definition at line 2082 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSCCNT_SHIFT 17

Definition at line 2083 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002

Definition at line 2091 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001

Definition at line 2090 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007

Definition at line 2096 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005

Definition at line 2094 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004

Definition at line 2093 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003

Definition at line 2092 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006

Definition at line 2095 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008

Definition at line 2097 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009

Definition at line 2098 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F

Definition at line 2078 of file ixgbe_type.h.

#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000

Definition at line 2089 of file ixgbe_type.h.

#define IXGBE_RXDADV_SPH 0x8000

Definition at line 2086 of file ixgbe_type.h.

#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000

Definition at line 2085 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */

Definition at line 2041 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */

Definition at line 2042 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */

Definition at line 2046 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */

Definition at line 2047 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */

Definition at line 2051 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */

Definition at line 2050 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */

Definition at line 2049 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */

Definition at line 2048 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */

Definition at line 2043 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */

Definition at line 2045 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE 1588 Time Stamp */

Definition at line 2052 of file ixgbe_type.h.

#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */

Definition at line 2044 of file ixgbe_type.h.

#define IXGBE_RXDATARDPTR ( _i ) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/

Definition at line 869 of file ixgbe_type.h.

#define IXGBE_RXDATAWRPTR ( _i ) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/

Definition at line 867 of file ixgbe_type.h.

#define IXGBE_RXDBUECC 0x03F70

Definition at line 886 of file ixgbe_type.h.

#define IXGBE_RXDBUEST 0x03F74

Definition at line 888 of file ixgbe_type.h.

#define IXGBE_RXDCTL ( _i )

Value:

(((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \

(0x0D028 + (((_i) - 64) * 0x40)))

Definition at line 194 of file ixgbe_type.h.

#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */

Definition at line 1883 of file ixgbe_type.h.

#define IXGBE_RXDCTL_RLPML_EN 0x00008000

Definition at line 1886 of file ixgbe_type.h.

#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */

Definition at line 1885 of file ixgbe_type.h.

#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */

Definition at line 1884 of file ixgbe_type.h.

#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */

Definition at line 1887 of file ixgbe_type.h.

#define IXGBE_RXDDGBCH 0x02F64

Definition at line 952 of file ixgbe_type.h.

#define IXGBE_RXDDGBCL 0x02F60

Definition at line 951 of file ixgbe_type.h.

#define IXGBE_RXDDGPC 0x02F5C

Definition at line 950 of file ixgbe_type.h.

#define IXGBE_RXDESCRDPTR ( _i ) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/

Definition at line 870 of file ixgbe_type.h.

#define IXGBE_RXDESCWRPTR ( _i ) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/

Definition at line 868 of file ixgbe_type.h.

#define IXGBE_RXDGBCH 0x02F58

Definition at line 949 of file ixgbe_type.h.

#define IXGBE_RXDGBCL 0x02F54

Definition at line 948 of file ixgbe_type.h.

#define IXGBE_RXDGPC 0x02F50

Definition at line 947 of file ixgbe_type.h.

#define IXGBE_RXDLPBKGBCH 0x02F7C

Definition at line 958 of file ixgbe_type.h.

#define IXGBE_RXDLPBKGBCL 0x02F78

Definition at line 957 of file ixgbe_type.h.

#define IXGBE_RXDLPBKGPC 0x02F74

Definition at line 956 of file ixgbe_type.h.

#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF

Definition at line 2076 of file ixgbe_type.h.

#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000

Definition at line 2075 of file ixgbe_type.h.

#define IXGBE_RXDSTATCTRL 0x02F40

Definition at line 963 of file ixgbe_type.h.

#define IXGBE_RXFECCERR0 0x051B8

Definition at line 279 of file ixgbe_type.h.

#define IXGBE_RXLPBKGBCH 0x02F70

Definition at line 955 of file ixgbe_type.h.

#define IXGBE_RXLPBKGBCL 0x02F6C

Definition at line 954 of file ixgbe_type.h.

#define IXGBE_RXLPBKGPC 0x02F68

Definition at line 953 of file ixgbe_type.h.

#define IXGBE_RXMEMWRAP 0x03190

Definition at line 200 of file ixgbe_type.h.

#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */

Definition at line 812 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF

Definition at line 1904 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01

Definition at line 1906 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03

Definition at line 1908 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02

Definition at line 1907 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04

Definition at line 1909 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00

Definition at line 1905 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00

Definition at line 1919 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100

Definition at line 1913 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900

Definition at line 1917 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800

Definition at line 1916 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00

Definition at line 1921 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00

Definition at line 1911 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00

Definition at line 1918 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200

Definition at line 1914 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300

Definition at line 1915 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00

Definition at line 1920 of file ixgbe_type.h.

#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000

Definition at line 1912 of file ixgbe_type.h.

#define IXGBE_RXNFGBCH 0x041B8

Definition at line 946 of file ixgbe_type.h.

#define IXGBE_RXNFGBCL 0x041B4

Definition at line 945 of file ixgbe_type.h.

#define IXGBE_RXNFGPC 0x041B0

Definition at line 944 of file ixgbe_type.h.

#define IXGBE_RXPBSIZE ( _i ) (0x03C00 + ((_i) * 4))

Definition at line 221 of file ixgbe_type.h.

#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */

Definition at line 1169 of file ixgbe_type.h.

#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */

Definition at line 1166 of file ixgbe_type.h.

#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */

Definition at line 1167 of file ixgbe_type.h.

#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */

Definition at line 1168 of file ixgbe_type.h.

#define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer*/

Definition at line 1170 of file ixgbe_type.h.

#define IXGBE_RXPBSIZE_SHIFT 10

Definition at line 225 of file ixgbe_type.h.

#define IXGBE_RXRDPTR ( _i ) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/

Definition at line 878 of file ixgbe_type.h.

#define IXGBE_RXRDWRPTR ( _i ) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/

Definition at line 879 of file ixgbe_type.h.

#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */

Definition at line 811 of file ixgbe_type.h.

#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */

Definition at line 810 of file ixgbe_type.h.

#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */

Definition at line 809 of file ixgbe_type.h.

#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */

Definition at line 808 of file ixgbe_type.h.

#define IXGBE_RXUSED ( _i ) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/

Definition at line 877 of file ixgbe_type.h.

#define IXGBE_RXWRPTR ( _i ) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/

Definition at line 876 of file ixgbe_type.h.

#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0

Definition at line 1788 of file ixgbe_type.h.

#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3

Definition at line 1789 of file ixgbe_type.h.

#define IXGBE_SAN_MAC_ADDR_PTR 0x28

Definition at line 1725 of file ixgbe_type.h.

#define IXGBE_SAQF ( _i ) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */

Definition at line 251 of file ixgbe_type.h.

#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */

Definition at line 1149 of file ixgbe_type.h.

#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */

Definition at line 1150 of file ixgbe_type.h.

#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */

Definition at line 1151 of file ixgbe_type.h.

#define IXGBE_SDPQF ( _i ) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */

Definition at line 253 of file ixgbe_type.h.

#define IXGBE_SECRXCTRL 0x08D00

Definition at line 449 of file ixgbe_type.h.

#define IXGBE_SECRXCTRL_RX_DIS 0x00000002

Definition at line 461 of file ixgbe_type.h.

#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001

Definition at line 460 of file ixgbe_type.h.

#define IXGBE_SECRXSTAT 0x08D04

Definition at line 450 of file ixgbe_type.h.

#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002

Definition at line 464 of file ixgbe_type.h.

#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001

Definition at line 463 of file ixgbe_type.h.

#define IXGBE_SECTXBUFFAF 0x08808

Definition at line 447 of file ixgbe_type.h.

#define IXGBE_SECTXCTRL 0x08800

Definition at line 445 of file ixgbe_type.h.

#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001

Definition at line 453 of file ixgbe_type.h.

#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004

Definition at line 455 of file ixgbe_type.h.

#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4

Definition at line 539 of file ixgbe_type.h.

#define IXGBE_SECTXCTRL_TX_DIS 0x00000002

Definition at line 454 of file ixgbe_type.h.

#define IXGBE_SECTXMINIFG 0x08810

Definition at line 448 of file ixgbe_type.h.

#define IXGBE_SECTXSTAT 0x08804

Definition at line 446 of file ixgbe_type.h.

#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002

Definition at line 458 of file ixgbe_type.h.

#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001

Definition at line 457 of file ixgbe_type.h.

#define IXGBE_SERDESC 0x04298

Definition at line 921 of file ixgbe_type.h.

#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11

Definition at line 1727 of file ixgbe_type.h.

#define IXGBE_SGMIIC 0x04314

Definition at line 941 of file ixgbe_type.h.

#define IXGBE_SMADARCTL 0x14F10

Definition at line 939 of file ixgbe_type.h.

#define IXGBE_SMARTSPEED_MAX_RETRIES 3

Definition at line 2632 of file ixgbe_type.h.

#define IXGBE_SPOOF_MACAS_MASK 0xFF

Definition at line 344 of file ixgbe_type.h.

#define IXGBE_SPOOF_VLANAS_MASK 0xFF00

Definition at line 345 of file ixgbe_type.h.

#define IXGBE_SPOOF_VLANAS_SHIFT 8

Definition at line 346 of file ixgbe_type.h.

#define IXGBE_SRRCTL ( _i )

Value:

(((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
                          (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
              (0x0D014 + (((_i) - 64) * 0x40))))

Definition at line 208 of file ixgbe_type.h.

#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00

Definition at line 2067 of file ixgbe_type.h.

#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F

Definition at line 2066 of file ixgbe_type.h.

#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */

Definition at line 2062 of file ixgbe_type.h.

#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000

Definition at line 2069 of file ixgbe_type.h.

#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000

Definition at line 2071 of file ixgbe_type.h.

#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000

Definition at line 2070 of file ixgbe_type.h.

#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000

Definition at line 2072 of file ixgbe_type.h.

#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000

Definition at line 2068 of file ixgbe_type.h.

#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000

Definition at line 2073 of file ixgbe_type.h.

#define IXGBE_SRRCTL_DROP_EN 0x10000000

Definition at line 2065 of file ixgbe_type.h.

#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000

Definition at line 2064 of file ixgbe_type.h.

#define IXGBE_SRRCTL_RDMTS_SHIFT 22

Definition at line 2063 of file ixgbe_type.h.

#define IXGBE_SSVPC 0x08780

Definition at line 682 of file ixgbe_type.h.

#define IXGBE_STARCTRL 0x03024

Definition at line 201 of file ixgbe_type.h.

#define IXGBE_STATUS 0x00008

Definition at line 76 of file ixgbe_type.h.

#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */

Definition at line 1496 of file ixgbe_type.h.

#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */

Definition at line 1494 of file ixgbe_type.h.

#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */

Definition at line 1498 of file ixgbe_type.h.

#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */

Definition at line 1499 of file ixgbe_type.h.

#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/

Definition at line 1495 of file ixgbe_type.h.

#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0

Definition at line 58 of file ixgbe_type.h.

#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C

Definition at line 64 of file ixgbe_type.h.

#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72

Definition at line 57 of file ixgbe_type.h.

#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9

Definition at line 56 of file ixgbe_type.h.

#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */

Definition at line 1646 of file ixgbe_type.h.

#define IXGBE_SWFW_SYNC IXGBE_GSSR

Definition at line 767 of file ixgbe_type.h.

#define IXGBE_SWSM 0x10140

Definition at line 761 of file ixgbe_type.h.

#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */

Definition at line 1643 of file ixgbe_type.h.

#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */

Definition at line 1644 of file ixgbe_type.h.

#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */

Definition at line 1645 of file ixgbe_type.h.

#define IXGBE_SWSR 0x15F10

Definition at line 735 of file ixgbe_type.h.

#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */

Definition at line 257 of file ixgbe_type.h.

#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */

Definition at line 816 of file ixgbe_type.h.

#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */

Definition at line 815 of file ixgbe_type.h.

#define IXGBE_TCPTIMER 0x0004C

Definition at line 83 of file ixgbe_type.h.

#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200

Definition at line 1197 of file ixgbe_type.h.

#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400

Definition at line 1198 of file ixgbe_type.h.

#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF

Definition at line 1200 of file ixgbe_type.h.

#define IXGBE_TCPTIMER_KS 0x00000100

Definition at line 1196 of file ixgbe_type.h.

#define IXGBE_TCPTIMER_LOOP 0x00000800

Definition at line 1199 of file ixgbe_type.h.

#define IXGBE_TDBAH ( _i ) (0x06004 + ((_i) * 0x40))

Definition at line 318 of file ixgbe_type.h.

#define IXGBE_TDBAL ( _i ) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/

Definition at line 317 of file ixgbe_type.h.

#define IXGBE_TDH ( _i ) (0x06010 + ((_i) * 0x40))

Definition at line 320 of file ixgbe_type.h.

#define IXGBE_TDHMPN 0x07F08

Definition at line 844 of file ixgbe_type.h.

#define IXGBE_TDHMPN2 0x082FC

Definition at line 845 of file ixgbe_type.h.

#define IXGBE_TDHMPN_TDICADDR 0x003FF800

Definition at line 1246 of file ixgbe_type.h.

#define IXGBE_TDHMPN_TDICADDR_SHIFT 11

Definition at line 1248 of file ixgbe_type.h.

#define IXGBE_TDHMPN_TDICRDREQ 0x00800000

Definition at line 1247 of file ixgbe_type.h.

#define IXGBE_TDLEN ( _i ) (0x06008 + ((_i) * 0x40))

Definition at line 319 of file ixgbe_type.h.

#define IXGBE_TDPROBE 0x07F20

Definition at line 849 of file ixgbe_type.h.

#define IXGBE_TDPT2TCCR ( _i ) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 440 of file ixgbe_type.h.

#define IXGBE_TDPT2TCSR ( _i ) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */

Definition at line 441 of file ixgbe_type.h.

#define IXGBE_TDSTAT ( _i ) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */

Definition at line 843 of file ixgbe_type.h.

#define IXGBE_TDSTATCTL 0x07C20

Definition at line 842 of file ixgbe_type.h.

#define IXGBE_TDT ( _i ) (0x06018 + ((_i) * 0x40))

Definition at line 321 of file ixgbe_type.h.

#define IXGBE_TDTQ2TCCR ( _i ) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */

Definition at line 438 of file ixgbe_type.h.

#define IXGBE_TDTQ2TCSR ( _i ) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */

Definition at line 439 of file ixgbe_type.h.

#define IXGBE_TDWBAH ( _i ) (0x0603C + ((_i) * 0x40))

Definition at line 324 of file ixgbe_type.h.

#define IXGBE_TDWBAL ( _i ) (0x06038 + ((_i) * 0x40))

Definition at line 323 of file ixgbe_type.h.

#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */

Definition at line 1877 of file ixgbe_type.h.

#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */

Definition at line 1878 of file ixgbe_type.h.

#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */

Definition at line 590 of file ixgbe_type.h.

#define IXGBE_TFCS 0x0CE00

Definition at line 181 of file ixgbe_type.h.

#define IXGBE_TFCS_TXOFF 0x00000001

Definition at line 1185 of file ixgbe_type.h.

#define IXGBE_TFCS_TXOFF0 0x00000100

Definition at line 1186 of file ixgbe_type.h.

#define IXGBE_TFCS_TXOFF1 0x00000200

Definition at line 1187 of file ixgbe_type.h.

#define IXGBE_TFCS_TXOFF2 0x00000400

Definition at line 1188 of file ixgbe_type.h.

#define IXGBE_TFCS_TXOFF3 0x00000800

Definition at line 1189 of file ixgbe_type.h.

#define IXGBE_TFCS_TXOFF4 0x00001000

Definition at line 1190 of file ixgbe_type.h.

#define IXGBE_TFCS_TXOFF5 0x00002000

Definition at line 1191 of file ixgbe_type.h.

#define IXGBE_TFCS_TXOFF6 0x00004000

Definition at line 1192 of file ixgbe_type.h.

#define IXGBE_TFCS_TXOFF7 0x00008000

Definition at line 1193 of file ixgbe_type.h.

#define IXGBE_TIC_DW ( _i ) (0x07F10 + ((_i) * 4))

Definition at line 847 of file ixgbe_type.h.

#define IXGBE_TIC_DW2 ( _i ) (0x082B0 + ((_i) * 4))

Definition at line 848 of file ixgbe_type.h.

#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */

Definition at line 819 of file ixgbe_type.h.

#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */

Definition at line 818 of file ixgbe_type.h.

#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */

Definition at line 817 of file ixgbe_type.h.

#define IXGBE_TIPG 0x0CB00

Definition at line 352 of file ixgbe_type.h.

#define IXGBE_TIPG_FIBER_DEFAULT 3

Definition at line 355 of file ixgbe_type.h.

#define IXGBE_TORH 0x040C4

Definition at line 670 of file ixgbe_type.h.

#define IXGBE_TORL 0x040C0

Definition at line 669 of file ixgbe_type.h.

#define IXGBE_TPR 0x040D0

Definition at line 671 of file ixgbe_type.h.

#define IXGBE_TPT 0x040D4

Definition at line 672 of file ixgbe_type.h.

#define IXGBE_TQSM ( _i ) (0x08600 + ((_i) * 4))

Definition at line 687 of file ixgbe_type.h.

#define IXGBE_TQSMR ( _i )

Value:

(((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \

(0x08600 + ((_i) * 4)))

Definition at line 685 of file ixgbe_type.h.

#define IXGBE_TREG 0x0426C

Definition at line 916 of file ixgbe_type.h.

#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */

Definition at line 822 of file ixgbe_type.h.

#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */

Definition at line 824 of file ixgbe_type.h.

#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */

Definition at line 821 of file ixgbe_type.h.

#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */

Definition at line 823 of file ixgbe_type.h.

#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */

Definition at line 820 of file ixgbe_type.h.

#define IXGBE_TSAUXC_EN_CLK 0x00000004

Definition at line 1889 of file ixgbe_type.h.

#define IXGBE_TSAUXC_SDP0_INT 0x00000040

Definition at line 1891 of file ixgbe_type.h.

#define IXGBE_TSAUXC_SYNCLK 0x00000008

Definition at line 1890 of file ixgbe_type.h.

#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */

Definition at line 591 of file ixgbe_type.h.

#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */

Definition at line 806 of file ixgbe_type.h.

#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */

Definition at line 1902 of file ixgbe_type.h.

#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A

Definition at line 1901 of file ixgbe_type.h.

#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04

Definition at line 1900 of file ixgbe_type.h.

#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00

Definition at line 1898 of file ixgbe_type.h.

#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02

Definition at line 1899 of file ixgbe_type.h.

#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */

Definition at line 1897 of file ixgbe_type.h.

#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */

Definition at line 1896 of file ixgbe_type.h.

#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */

Definition at line 807 of file ixgbe_type.h.

#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */

Definition at line 1894 of file ixgbe_type.h.

#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */

Definition at line 1893 of file ixgbe_type.h.

#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT

Definition at line 2151 of file ixgbe_type.h.

#define IXGBE_TX_PAD_ENABLE 0x00000400

Definition at line 1872 of file ixgbe_type.h.

#define IXGBE_TXBUFCTRL 0x0C600

Definition at line 850 of file ixgbe_type.h.

#define IXGBE_TXBUFDATA0 0x0C610

Definition at line 851 of file ixgbe_type.h.

#define IXGBE_TXBUFDATA1 0x0C614

Definition at line 852 of file ixgbe_type.h.

#define IXGBE_TXBUFDATA2 0x0C618

Definition at line 853 of file ixgbe_type.h.

#define IXGBE_TXBUFDATA3 0x0C61C

Definition at line 854 of file ixgbe_type.h.

#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */

Definition at line 1975 of file ixgbe_type.h.

#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */

Definition at line 1971 of file ixgbe_type.h.

#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */

Definition at line 1973 of file ixgbe_type.h.

#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */

Definition at line 1972 of file ixgbe_type.h.

#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */

Definition at line 1974 of file ixgbe_type.h.

#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */

Definition at line 1976 of file ixgbe_type.h.

#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */

Definition at line 1969 of file ixgbe_type.h.

#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */

Definition at line 1970 of file ixgbe_type.h.

#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */

Definition at line 1977 of file ixgbe_type.h.

#define IXGBE_TXDATARDPTR ( _i ) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/

Definition at line 873 of file ixgbe_type.h.

#define IXGBE_TXDATAWRPTR ( _i ) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/

Definition at line 871 of file ixgbe_type.h.

#define IXGBE_TXDBUECC 0x0CF70

Definition at line 887 of file ixgbe_type.h.

#define IXGBE_TXDBUEST 0x0CF74

Definition at line 889 of file ixgbe_type.h.

#define IXGBE_TXDCTL ( _i ) (0x06028 + ((_i) * 0x40))

Definition at line 322 of file ixgbe_type.h.

#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */

Definition at line 1868 of file ixgbe_type.h.

#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */

Definition at line 1869 of file ixgbe_type.h.

#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */

Definition at line 1870 of file ixgbe_type.h.

#define IXGBE_TXDESCIC 0x082CC

Definition at line 846 of file ixgbe_type.h.

#define IXGBE_TXDESCIC_READY 0x80000000

Definition at line 1274 of file ixgbe_type.h.

#define IXGBE_TXDESCRDPTR ( _i ) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/

Definition at line 874 of file ixgbe_type.h.

#define IXGBE_TXDESCWRPTR ( _i ) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/

Definition at line 872 of file ixgbe_type.h.

#define IXGBE_TXDGBCH 0x087A8

Definition at line 961 of file ixgbe_type.h.

#define IXGBE_TXDGBCL 0x087A4

Definition at line 960 of file ixgbe_type.h.

#define IXGBE_TXDGPC 0x087A0

Definition at line 959 of file ixgbe_type.h.

#define IXGBE_TXLLQ ( _i ) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */

Definition at line 549 of file ixgbe_type.h.

#define IXGBE_TXPBSIZE ( _i ) (0x0CC00 + ((_i) * 4)) /* 8 of these */

Definition at line 353 of file ixgbe_type.h.

#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */

Definition at line 1164 of file ixgbe_type.h.

#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */

Definition at line 1165 of file ixgbe_type.h.

#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/

Definition at line 1171 of file ixgbe_type.h.

#define IXGBE_TXPBSIZE_SHIFT 10

Definition at line 356 of file ixgbe_type.h.

#define IXGBE_TXPBTHRESH ( _i ) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */

Definition at line 334 of file ixgbe_type.h.

#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */

Definition at line 1173 of file ixgbe_type.h.

#define IXGBE_TXRDPTR ( _i ) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/

Definition at line 882 of file ixgbe_type.h.

#define IXGBE_TXRDWRPTR ( _i ) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/

Definition at line 883 of file ixgbe_type.h.

#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */

Definition at line 814 of file ixgbe_type.h.

#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */

Definition at line 813 of file ixgbe_type.h.

#define IXGBE_TXUSED ( _i ) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/

Definition at line 881 of file ixgbe_type.h.

#define IXGBE_TXWRPTR ( _i ) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/

Definition at line 880 of file ixgbe_type.h.

#define IXGBE_UTA ( _i ) (0x0F400 + ((_i) * 4))

Definition at line 274 of file ixgbe_type.h.

#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50

Definition at line 966 of file ixgbe_type.h.

#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */

Definition at line 1240 of file ixgbe_type.h.

#define IXGBE_VFLRE ( _i ) ((((_i) & 1) ? 0x001C0 : 0x00600))

Definition at line 2156 of file ixgbe_type.h.

#define IXGBE_VFLREC ( _i ) (0x00700 + ((_i) * 4))

Definition at line 2157 of file ixgbe_type.h.

#define IXGBE_VFRE ( _i ) (0x051E0 + ((_i) * 4))

Definition at line 268 of file ixgbe_type.h.

#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF

Definition at line 1238 of file ixgbe_type.h.

#define IXGBE_VFTA ( _i ) (0x0A000 + ((_i) * 4))

Definition at line 244 of file ixgbe_type.h.

#define IXGBE_VFTAVIND	(	_j,
		_i
	)	(0x0A200 + ((_j) * 0x200) + ((_i) * 4))

Definition at line 246 of file ixgbe_type.h.

#define IXGBE_VFTE ( _i ) (0x08110 + ((_i) * 4))

Definition at line 269 of file ixgbe_type.h.

#define IXGBE_VLNCTRL 0x05088

Definition at line 248 of file ixgbe_type.h.

#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */

Definition at line 1477 of file ixgbe_type.h.

#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */

Definition at line 1478 of file ixgbe_type.h.

#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */

Definition at line 1476 of file ixgbe_type.h.

#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */

Definition at line 1479 of file ixgbe_type.h.

#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */

Definition at line 1480 of file ixgbe_type.h.

#define IXGBE_VLVF ( _i ) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */

Definition at line 260 of file ixgbe_type.h.

#define IXGBE_VLVF_ENTRIES 64

Definition at line 1484 of file ixgbe_type.h.

#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */

Definition at line 1483 of file ixgbe_type.h.

#define IXGBE_VLVF_VLANID_MASK 0x00000FFF

Definition at line 1485 of file ixgbe_type.h.

#define IXGBE_VLVFB ( _i ) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */

Definition at line 261 of file ixgbe_type.h.

#define IXGBE_VMD_CTL 0x0581C

Definition at line 284 of file ixgbe_type.h.

#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001

Definition at line 1220 of file ixgbe_type.h.

#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002

Definition at line 1221 of file ixgbe_type.h.

#define IXGBE_VMECM ( _i ) (0x08790 + ((_i) * 4))

Definition at line 270 of file ixgbe_type.h.

#define IXGBE_VMOLR ( _i ) (0x0F000 + ((_i) * 4)) /* 64 total */

Definition at line 273 of file ixgbe_type.h.

#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */

Definition at line 1231 of file ixgbe_type.h.

#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */

Definition at line 1234 of file ixgbe_type.h.

#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */

Definition at line 1235 of file ixgbe_type.h.

#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */

Definition at line 1232 of file ixgbe_type.h.

#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */

Definition at line 1233 of file ixgbe_type.h.

#define IXGBE_VMRVLAN ( _i ) (0x0F610 + ((_i) * 4))

Definition at line 276 of file ixgbe_type.h.

#define IXGBE_VMRVM ( _i ) (0x0F630 + ((_i) * 4))

Definition at line 277 of file ixgbe_type.h.

#define IXGBE_VMTXSW ( _i ) (0x05180 + ((_i) * 4)) /* 2 total */

Definition at line 272 of file ixgbe_type.h.

#define IXGBE_VMVIR ( _i ) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */

Definition at line 262 of file ixgbe_type.h.

#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */

Definition at line 1488 of file ixgbe_type.h.

#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */

Definition at line 1489 of file ixgbe_type.h.

#define IXGBE_VPDDIAG0 0x10204

Definition at line 104 of file ixgbe_type.h.

#define IXGBE_VPDDIAG1 0x10208

Definition at line 105 of file ixgbe_type.h.

#define IXGBE_VT_CTL 0x051B0

Definition at line 263 of file ixgbe_type.h.

#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */

Definition at line 1224 of file ixgbe_type.h.

#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)

Definition at line 1228 of file ixgbe_type.h.

#define IXGBE_VT_CTL_POOL_SHIFT 7

Definition at line 1227 of file ixgbe_type.h.

#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */

Definition at line 1225 of file ixgbe_type.h.

#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */

Definition at line 1226 of file ixgbe_type.h.

#define IXGBE_WUC 0x05800

Definition at line 359 of file ixgbe_type.h.

#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */

Definition at line 381 of file ixgbe_type.h.

#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */

Definition at line 382 of file ixgbe_type.h.

#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */

Definition at line 383 of file ixgbe_type.h.

#define IXGBE_WUFC 0x05808

Definition at line 360 of file ixgbe_type.h.

#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */

Definition at line 405 of file ixgbe_type.h.

#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */

Definition at line 391 of file ixgbe_type.h.

#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */

Definition at line 390 of file ixgbe_type.h.

#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */

Definition at line 388 of file ixgbe_type.h.

#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */

Definition at line 404 of file ixgbe_type.h.

#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */

Definition at line 397 of file ixgbe_type.h.

#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */

Definition at line 398 of file ixgbe_type.h.

#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */

Definition at line 399 of file ixgbe_type.h.

#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */

Definition at line 400 of file ixgbe_type.h.

#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */

Definition at line 401 of file ixgbe_type.h.

#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */

Definition at line 402 of file ixgbe_type.h.

#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */

Definition at line 403 of file ixgbe_type.h.

#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */

Definition at line 406 of file ixgbe_type.h.

#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */

Definition at line 396 of file ixgbe_type.h.

#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */

Definition at line 392 of file ixgbe_type.h.

#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */

Definition at line 393 of file ixgbe_type.h.

#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */

Definition at line 386 of file ixgbe_type.h.

#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */

Definition at line 387 of file ixgbe_type.h.

#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */

Definition at line 389 of file ixgbe_type.h.

#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */

Definition at line 394 of file ixgbe_type.h.

#define IXGBE_WUPL 0x05900

Definition at line 366 of file ixgbe_type.h.

#define IXGBE_WUPL_LENGTH_MASK 0xFFFF

Definition at line 427 of file ixgbe_type.h.

#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */

Definition at line 367 of file ixgbe_type.h.

#define IXGBE_WUS 0x05810

Definition at line 361 of file ixgbe_type.h.

#define IXGBE_WUS_ARP IXGBE_WUFC_ARP

Definition at line 414 of file ixgbe_type.h.

#define IXGBE_WUS_BC IXGBE_WUFC_BC

Definition at line 413 of file ixgbe_type.h.

#define IXGBE_WUS_EX IXGBE_WUFC_EX

Definition at line 411 of file ixgbe_type.h.

#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0

Definition at line 418 of file ixgbe_type.h.

#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1

Definition at line 419 of file ixgbe_type.h.

#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2

Definition at line 420 of file ixgbe_type.h.

#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3

Definition at line 421 of file ixgbe_type.h.

#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4

Definition at line 422 of file ixgbe_type.h.

#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5

Definition at line 423 of file ixgbe_type.h.

#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS

Definition at line 424 of file ixgbe_type.h.

#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4

Definition at line 415 of file ixgbe_type.h.

#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6

Definition at line 416 of file ixgbe_type.h.

#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC

Definition at line 409 of file ixgbe_type.h.

#define IXGBE_WUS_MAG IXGBE_WUFC_MAG

Definition at line 410 of file ixgbe_type.h.

#define IXGBE_WUS_MC IXGBE_WUFC_MC

Definition at line 412 of file ixgbe_type.h.

#define IXGBE_WUS_MNG IXGBE_WUFC_MNG

Definition at line 417 of file ixgbe_type.h.

#define IXGBE_XAUI_D (2 * 1024)

Definition at line 2441 of file ixgbe_type.h.

#define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */

Definition at line 2434 of file ixgbe_type.h.

#define IXGBE_XEC 0x04120

Definition at line 681 of file ixgbe_type.h.

#define IXGBE_XPCSS 0x04290

Definition at line 919 of file ixgbe_type.h.

#define MAX_TRAFFIC_CLASS 8

Definition at line 430 of file ixgbe_type.h.

#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL

Definition at line 1179 of file ixgbe_type.h.

#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED

Definition at line 1181 of file ixgbe_type.h.

#define QT2022_PHY_ID 0x0043A400

Definition at line 1129 of file ixgbe_type.h.

#define TN1010_PHY_ID 0x00A19410

Definition at line 1126 of file ixgbe_type.h.

#define TNX_FW_REV 0xB

Definition at line 1127 of file ixgbe_type.h.

#define X540_PHY_ID 0x01540200

Definition at line 1128 of file ixgbe_type.h.

#define X540_TRAFFIC_CLASS 4

Definition at line 431 of file ixgbe_type.h.

Typedef Documentation

typedef u32 ixgbe_autoneg_advertised

Definition at line 2384 of file ixgbe_type.h.

typedef u32 ixgbe_link_speed

Definition at line 2386 of file ixgbe_type.h.

typedef u8*(* ixgbe_mc_addr_itr)(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)

Definition at line 2788 of file ixgbe_type.h.

typedef u32 ixgbe_physical_layer

Definition at line 2399 of file ixgbe_type.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

PBA_STRATEGY_EQUAL
PBA_STRATEGY_EQUAL
PBA_STRATEGY_WEIGHTED
PBA_STRATEGY_WEIGHTED

Definition at line 1177 of file ixgbe_type.h.

enum ixgbe_atr_flow_type

Enumerator:

IXGBE_ATR_FLOW_TYPE_IPV4
IXGBE_ATR_FLOW_TYPE_UDPV4
IXGBE_ATR_FLOW_TYPE_TCPV4
IXGBE_ATR_FLOW_TYPE_SCTPV4
IXGBE_ATR_FLOW_TYPE_IPV6
IXGBE_ATR_FLOW_TYPE_UDPV6
IXGBE_ATR_FLOW_TYPE_TCPV6
IXGBE_ATR_FLOW_TYPE_SCTPV6

Definition at line 2489 of file ixgbe_type.h.

enum ixgbe_bus_speed

Enumerator:

ixgbe_bus_speed_unknown
ixgbe_bus_speed_33
ixgbe_bus_speed_66
ixgbe_bus_speed_100
ixgbe_bus_speed_120
ixgbe_bus_speed_133
ixgbe_bus_speed_2500
ixgbe_bus_speed_5000
ixgbe_bus_speed_reserved

Definition at line 2649 of file ixgbe_type.h.

enum ixgbe_bus_type

Enumerator:

ixgbe_bus_type_unknown
ixgbe_bus_type_pci
ixgbe_bus_type_pcix
ixgbe_bus_type_pci_express
ixgbe_bus_type_reserved

Definition at line 2640 of file ixgbe_type.h.

enum ixgbe_bus_width

Enumerator:

ixgbe_bus_width_unknown
ixgbe_bus_width_pcie_x1
ixgbe_bus_width_pcie_x2
ixgbe_bus_width_pcie_x4
ixgbe_bus_width_pcie_x8
ixgbe_bus_width_32
ixgbe_bus_width_64
ixgbe_bus_width_reserved

Definition at line 2662 of file ixgbe_type.h.

enum ixgbe_eeprom_type

Enumerator:

ixgbe_eeprom_uninitialized
ixgbe_eeprom_spi
ixgbe_flash
ixgbe_eeprom_none

Definition at line 2545 of file ixgbe_type.h.

enum ixgbe_fc_mode

Enumerator:

ixgbe_fc_none
ixgbe_fc_rx_pause
ixgbe_fc_tx_pause
ixgbe_fc_full
ixgbe_fc_default

Definition at line 2623 of file ixgbe_type.h.

enum ixgbe_fdir_pballoc_type

Enumerator:

IXGBE_FDIR_PBALLOC_NONE
IXGBE_FDIR_PBALLOC_64K
IXGBE_FDIR_PBALLOC_128K
IXGBE_FDIR_PBALLOC_256K

Definition at line 2159 of file ixgbe_type.h.

enum ixgbe_mac_type

Enumerator:

ixgbe_mac_unknown
ixgbe_mac_82598EB
ixgbe_mac_82599EB
ixgbe_mac_X540
ixgbe_num_macs
ixgbe_mac_unknown
ixgbe_mac_82599_vf
ixgbe_mac_X540_vf
ixgbe_num_macs

Definition at line 2552 of file ixgbe_type.h.

enum ixgbe_media_type

Enumerator:

ixgbe_media_type_unknown
ixgbe_media_type_fiber
ixgbe_media_type_fiber_lco
ixgbe_media_type_copper
ixgbe_media_type_backplane
ixgbe_media_type_cx4
ixgbe_media_type_virtual

Definition at line 2612 of file ixgbe_type.h.

enum ixgbe_phy_type

Enumerator:

ixgbe_phy_unknown
ixgbe_phy_none
ixgbe_phy_tn
ixgbe_phy_aq
ixgbe_phy_cu_unknown
ixgbe_phy_qt
ixgbe_phy_xaui
ixgbe_phy_nl
ixgbe_phy_sfp_passive_tyco
ixgbe_phy_sfp_passive_unknown
ixgbe_phy_sfp_active_unknown
ixgbe_phy_sfp_avago
ixgbe_phy_sfp_ftl
ixgbe_phy_sfp_ftl_active
ixgbe_phy_sfp_unknown
ixgbe_phy_sfp_intel
ixgbe_phy_sfp_unsupported
ixgbe_phy_generic

Definition at line 2560 of file ixgbe_type.h.

enum ixgbe_sfp_type

Enumerator:

ixgbe_sfp_type_da_cu
ixgbe_sfp_type_sr
ixgbe_sfp_type_lr
ixgbe_sfp_type_da_cu_core0
ixgbe_sfp_type_da_cu_core1
ixgbe_sfp_type_srlr_core0
ixgbe_sfp_type_srlr_core1
ixgbe_sfp_type_da_act_lmt_core0
ixgbe_sfp_type_da_act_lmt_core1
ixgbe_sfp_type_1g_cu_core0
ixgbe_sfp_type_1g_cu_core1
ixgbe_sfp_type_1g_sx_core0
ixgbe_sfp_type_1g_sx_core1
ixgbe_sfp_type_not_present
ixgbe_sfp_type_unknown

Definition at line 2594 of file ixgbe_type.h.

enum ixgbe_smart_speed

Enumerator:

ixgbe_smart_speed_auto
ixgbe_smart_speed_on
ixgbe_smart_speed_off

Definition at line 2633 of file ixgbe_type.h.

Data Structures

Macros

Typedefs

Enumerations

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation