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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/kernel.h>#include <linux/types.h>#include <linux/tty.h>#include <linux/serial_core.h>#include <linux/device.h>Go to the source code of this file.
Data Structures | |
| struct | board_ops |
| struct | jsm_board |
| struct | jsm_channel |
| struct | neo_uart_struct |
Macros | |
| #define | jsm_printk(nlevel, klevel, pdev, fmt, args...) |
| #define | MAXLINES 256 |
| #define | MAXPORTS 8 |
| #define | MAX_STOPS_SENT 5 |
| #define | T_NEO 0000 |
| #define | T_CLASSIC 0001 |
| #define | T_PCIBUS 0400 |
| #define | BD_RUNNING 0x0 |
| #define | BD_REASON 0x7f |
| #define | BD_NOTFOUND 0x1 |
| #define | BD_NOIOPORT 0x2 |
| #define | BD_NOMEM 0x3 |
| #define | BD_NOBIOS 0x4 |
| #define | BD_NOFEP 0x5 |
| #define | BD_FAILED 0x6 |
| #define | BD_ALLOCATED 0x7 |
| #define | BD_TRIBOOT 0x8 |
| #define | BD_BADKME 0x80 |
| #define | WRITEBUFLEN ((4096) + 4) |
| #define | JSM_VERSION "jsm: 1.2-1-INKERNEL" |
| #define | JSM_PARTNUM "40002438_A-INKERNEL" |
| #define | CH_PRON 0x0001 /* Printer on string */ |
| #define | CH_STOP 0x0002 /* Output is stopped */ |
| #define | CH_STOPI 0x0004 /* Input is stopped */ |
| #define | CH_CD 0x0008 /* Carrier is present */ |
| #define | CH_FCAR 0x0010 /* Carrier forced on */ |
| #define | CH_HANGUP 0x0020 /* Hangup received */ |
| #define | CH_RECEIVER_OFF 0x0040 /* Receiver is off */ |
| #define | CH_OPENING 0x0080 /* Port in fragile open state */ |
| #define | CH_CLOSING 0x0100 /* Port in fragile close state */ |
| #define | CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */ |
| #define | CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */ |
| #define | CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */ |
| #define | CH_BREAK_SENDING 0x1000 /* Break is being sent */ |
| #define | CH_LOOPBACK 0x2000 /* Channel is in lookback mode */ |
| #define | CH_BAUD0 0x08000 /* Used for checking B0 transitions */ |
| #define | RQUEUEMASK 0x1FFF /* 8 K - 1 */ |
| #define | EQUEUEMASK 0x1FFF /* 8 K - 1 */ |
| #define | RQUEUESIZE (RQUEUEMASK + 1) |
| #define | EQUEUESIZE RQUEUESIZE |
| #define | UART_17158_POLL_ADDR_OFFSET 0x80 |
| #define | UART_17158_FCTR_RTS_NODELAY 0x00 |
| #define | UART_17158_FCTR_RTS_4DELAY 0x01 |
| #define | UART_17158_FCTR_RTS_6DELAY 0x02 |
| #define | UART_17158_FCTR_RTS_8DELAY 0x03 |
| #define | UART_17158_FCTR_RTS_12DELAY 0x12 |
| #define | UART_17158_FCTR_RTS_16DELAY 0x05 |
| #define | UART_17158_FCTR_RTS_20DELAY 0x13 |
| #define | UART_17158_FCTR_RTS_24DELAY 0x06 |
| #define | UART_17158_FCTR_RTS_28DELAY 0x14 |
| #define | UART_17158_FCTR_RTS_32DELAY 0x07 |
| #define | UART_17158_FCTR_RTS_36DELAY 0x16 |
| #define | UART_17158_FCTR_RTS_40DELAY 0x08 |
| #define | UART_17158_FCTR_RTS_44DELAY 0x09 |
| #define | UART_17158_FCTR_RTS_48DELAY 0x10 |
| #define | UART_17158_FCTR_RTS_52DELAY 0x11 |
| #define | UART_17158_FCTR_RTS_IRDA 0x10 |
| #define | UART_17158_FCTR_RS485 0x20 |
| #define | UART_17158_FCTR_TRGA 0x00 |
| #define | UART_17158_FCTR_TRGB 0x40 |
| #define | UART_17158_FCTR_TRGC 0x80 |
| #define | UART_17158_FCTR_TRGD 0xC0 |
| #define | UART_17158_FCTR_BIT6 0x40 |
| #define | UART_17158_FCTR_BIT7 0x80 |
| #define | UART_17158_RX_FIFOSIZE 64 |
| #define | UART_17158_TX_FIFOSIZE 64 |
| #define | UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ |
| #define | UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */ |
| #define | UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */ |
| #define | UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */ |
| #define | UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */ |
| #define | UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */ |
| #define | UART_17158_TXRDY 0x3 /* TX Ready */ |
| #define | UART_17158_MSR 0x4 /* Modem State Change */ |
| #define | UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */ |
| #define | UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */ |
| #define | UART_17158_EFR_ECB 0x10 /* Enhanced control bit */ |
| #define | UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ |
| #define | UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ |
| #define | UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ |
| #define | UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ |
| #define | UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ |
| #define | UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ |
| #define | UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */ |
| #define | UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */ |
| #define | UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */ |
| #define | UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */ |
| #define | PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI" |
| #define | PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator" |
| #define | PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI" |
| #define | PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator" |
| #define | PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM" |
Enumerations | |
| enum | { DBG_INIT = 0x01, DBG_BASIC = 0x02, DBG_CORE = 0x04, DBG_OPEN = 0x08, DBG_CLOSE = 0x10, DBG_READ = 0x20, DBG_WRITE = 0x40, DBG_IOCTL = 0x80, DBG_PROC = 0x100, DBG_PARAM = 0x200, DBG_PSCAN = 0x400, DBG_EVENT = 0x800, DBG_DRAIN = 0x1000, DBG_MSIGS = 0x2000, DBG_MGMT = 0x4000, DBG_INTR = 0x8000, DBG_CARR = 0x10000 } |
Functions | |
| int | jsm_tty_init (struct jsm_board *) |
| int | jsm_uart_port_init (struct jsm_board *) |
| int | jsm_remove_uart_port (struct jsm_board *) |
| void | jsm_input (struct jsm_channel *ch) |
| void | jsm_check_queue_flow_control (struct jsm_channel *ch) |
Variables | |
| struct uart_driver | jsm_uart_driver |
| struct board_ops | jsm_neo_ops |
| int | jsm_debug |
| #define CH_BAUD0 0x08000 /* Used for checking B0 transitions */ |
| #define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */ |
| #define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */ |
| #define EQUEUESIZE RQUEUESIZE |
| #define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI" |
| #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator" |
| #define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI" |
| #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator" |
| #define RQUEUESIZE (RQUEUEMASK + 1) |
| #define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ |
| #define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ |
| #define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ |
| #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */ |
| #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */ |
| #define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */ |
| #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */ |
| #define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ |
| #define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */ |
| #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */ |
| #define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */ |
| #define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ |
| #define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ |
| anonymous enum |
| void jsm_check_queue_flow_control | ( | struct jsm_channel * | ch | ) |
| void jsm_input | ( | struct jsm_channel * | ch | ) |
| int jsm_debug |
Definition at line 63 of file jsm_driver.c.
| struct uart_driver jsm_uart_driver |
Definition at line 43 of file jsm_driver.c.
1.8.2