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jsm_neo.c
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1 /************************************************************************
2  * Copyright 2003 Digi International (www.digi.com)
3  *
4  * Copyright (C) 2004 IBM Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14  * PURPOSE. See the GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19  * MA 02111-1307, USA.
20  *
21  * Contact Information:
22  * Scott H Kilau <[email protected]>
23  * Wendy Xiong <[email protected]>
24  *
25  ***********************************************************************/
26 #include <linux/delay.h> /* For udelay */
27 #include <linux/serial_reg.h> /* For the various UART offsets */
28 #include <linux/tty.h>
29 #include <linux/pci.h>
30 #include <asm/io.h>
31 
32 #include "jsm.h" /* Driver main header file */
33 
34 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
35 
36 /*
37  * This function allows calls to ensure that all outstanding
38  * PCI writes have been completed, by doing a PCI read against
39  * a non-destructive, read-only location on the Neo card.
40  *
41  * In this case, we are reading the DVID (Read-only Device Identification)
42  * value of the Neo card.
43  */
44 static inline void neo_pci_posting_flush(struct jsm_board *bd)
45 {
46  readb(bd->re_map_membase + 0x8D);
47 }
48 
49 static void neo_set_cts_flow_control(struct jsm_channel *ch)
50 {
51  u8 ier, efr;
52  ier = readb(&ch->ch_neo_uart->ier);
53  efr = readb(&ch->ch_neo_uart->efr);
54 
55  jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
56 
57  /* Turn on auto CTS flow control */
58  ier |= (UART_17158_IER_CTSDSR);
59  efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
60 
61  /* Turn off auto Xon flow control */
62  efr &= ~(UART_17158_EFR_IXON);
63 
64  /* Why? Becuz Exar's spec says we have to zero it out before setting it */
65  writeb(0, &ch->ch_neo_uart->efr);
66 
67  /* Turn on UART enhanced bits */
68  writeb(efr, &ch->ch_neo_uart->efr);
69 
70  /* Turn on table D, with 8 char hi/low watermarks */
71  writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
72 
73  /* Feed the UART our trigger levels */
74  writeb(8, &ch->ch_neo_uart->tfifo);
75  ch->ch_t_tlevel = 8;
76 
77  writeb(ier, &ch->ch_neo_uart->ier);
78 }
79 
80 static void neo_set_rts_flow_control(struct jsm_channel *ch)
81 {
82  u8 ier, efr;
83  ier = readb(&ch->ch_neo_uart->ier);
84  efr = readb(&ch->ch_neo_uart->efr);
85 
86  jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
87 
88  /* Turn on auto RTS flow control */
89  ier |= (UART_17158_IER_RTSDTR);
90  efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
91 
92  /* Turn off auto Xoff flow control */
93  ier &= ~(UART_17158_IER_XOFF);
94  efr &= ~(UART_17158_EFR_IXOFF);
95 
96  /* Why? Becuz Exar's spec says we have to zero it out before setting it */
97  writeb(0, &ch->ch_neo_uart->efr);
98 
99  /* Turn on UART enhanced bits */
100  writeb(efr, &ch->ch_neo_uart->efr);
101 
102  writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
103  ch->ch_r_watermark = 4;
104 
105  writeb(56, &ch->ch_neo_uart->rfifo);
106  ch->ch_r_tlevel = 56;
107 
108  writeb(ier, &ch->ch_neo_uart->ier);
109 
110  /*
111  * From the Neo UART spec sheet:
112  * The auto RTS/DTR function must be started by asserting
113  * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
114  * it is enabled.
115  */
116  ch->ch_mostat |= (UART_MCR_RTS);
117 }
118 
119 
120 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
121 {
122  u8 ier, efr;
123  ier = readb(&ch->ch_neo_uart->ier);
124  efr = readb(&ch->ch_neo_uart->efr);
125 
126  jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
127 
128  /* Turn off auto CTS flow control */
129  ier &= ~(UART_17158_IER_CTSDSR);
130  efr &= ~(UART_17158_EFR_CTSDSR);
131 
132  /* Turn on auto Xon flow control */
133  efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
134 
135  /* Why? Becuz Exar's spec says we have to zero it out before setting it */
136  writeb(0, &ch->ch_neo_uart->efr);
137 
138  /* Turn on UART enhanced bits */
139  writeb(efr, &ch->ch_neo_uart->efr);
140 
141  writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
142  ch->ch_r_watermark = 4;
143 
144  writeb(32, &ch->ch_neo_uart->rfifo);
145  ch->ch_r_tlevel = 32;
146 
147  /* Tell UART what start/stop chars it should be looking for */
148  writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
149  writeb(0, &ch->ch_neo_uart->xonchar2);
150 
151  writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
152  writeb(0, &ch->ch_neo_uart->xoffchar2);
153 
154  writeb(ier, &ch->ch_neo_uart->ier);
155 }
156 
157 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
158 {
159  u8 ier, efr;
160  ier = readb(&ch->ch_neo_uart->ier);
161  efr = readb(&ch->ch_neo_uart->efr);
162 
163  jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
164 
165  /* Turn off auto RTS flow control */
166  ier &= ~(UART_17158_IER_RTSDTR);
167  efr &= ~(UART_17158_EFR_RTSDTR);
168 
169  /* Turn on auto Xoff flow control */
170  ier |= (UART_17158_IER_XOFF);
171  efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
172 
173  /* Why? Becuz Exar's spec says we have to zero it out before setting it */
174  writeb(0, &ch->ch_neo_uart->efr);
175 
176  /* Turn on UART enhanced bits */
177  writeb(efr, &ch->ch_neo_uart->efr);
178 
179  /* Turn on table D, with 8 char hi/low watermarks */
180  writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
181 
182  writeb(8, &ch->ch_neo_uart->tfifo);
183  ch->ch_t_tlevel = 8;
184 
185  /* Tell UART what start/stop chars it should be looking for */
186  writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
187  writeb(0, &ch->ch_neo_uart->xonchar2);
188 
189  writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
190  writeb(0, &ch->ch_neo_uart->xoffchar2);
191 
192  writeb(ier, &ch->ch_neo_uart->ier);
193 }
194 
195 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
196 {
197  u8 ier, efr;
198  ier = readb(&ch->ch_neo_uart->ier);
199  efr = readb(&ch->ch_neo_uart->efr);
200 
201  jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
202 
203  /* Turn off auto RTS flow control */
204  ier &= ~(UART_17158_IER_RTSDTR);
205  efr &= ~(UART_17158_EFR_RTSDTR);
206 
207  /* Turn off auto Xoff flow control */
208  ier &= ~(UART_17158_IER_XOFF);
209  if (ch->ch_c_iflag & IXON)
210  efr &= ~(UART_17158_EFR_IXOFF);
211  else
212  efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
213 
214  /* Why? Becuz Exar's spec says we have to zero it out before setting it */
215  writeb(0, &ch->ch_neo_uart->efr);
216 
217  /* Turn on UART enhanced bits */
218  writeb(efr, &ch->ch_neo_uart->efr);
219 
220  /* Turn on table D, with 8 char hi/low watermarks */
221  writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
222 
223  ch->ch_r_watermark = 0;
224 
225  writeb(16, &ch->ch_neo_uart->tfifo);
226  ch->ch_t_tlevel = 16;
227 
228  writeb(16, &ch->ch_neo_uart->rfifo);
229  ch->ch_r_tlevel = 16;
230 
231  writeb(ier, &ch->ch_neo_uart->ier);
232 }
233 
234 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
235 {
236  u8 ier, efr;
237  ier = readb(&ch->ch_neo_uart->ier);
238  efr = readb(&ch->ch_neo_uart->efr);
239 
240  jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
241 
242  /* Turn off auto CTS flow control */
243  ier &= ~(UART_17158_IER_CTSDSR);
244  efr &= ~(UART_17158_EFR_CTSDSR);
245 
246  /* Turn off auto Xon flow control */
247  if (ch->ch_c_iflag & IXOFF)
248  efr &= ~(UART_17158_EFR_IXON);
249  else
250  efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
251 
252  /* Why? Becuz Exar's spec says we have to zero it out before setting it */
253  writeb(0, &ch->ch_neo_uart->efr);
254 
255  /* Turn on UART enhanced bits */
256  writeb(efr, &ch->ch_neo_uart->efr);
257 
258  /* Turn on table D, with 8 char hi/low watermarks */
259  writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
260 
261  ch->ch_r_watermark = 0;
262 
263  writeb(16, &ch->ch_neo_uart->tfifo);
264  ch->ch_t_tlevel = 16;
265 
266  writeb(16, &ch->ch_neo_uart->rfifo);
267  ch->ch_r_tlevel = 16;
268 
269  writeb(ier, &ch->ch_neo_uart->ier);
270 }
271 
272 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
273 {
274 
275  /* if hardware flow control is set, then skip this whole thing */
276  if (ch->ch_c_cflag & CRTSCTS)
277  return;
278 
279  jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "start\n");
280 
281  /* Tell UART what start/stop chars it should be looking for */
282  writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
283  writeb(0, &ch->ch_neo_uart->xonchar2);
284 
285  writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
286  writeb(0, &ch->ch_neo_uart->xoffchar2);
287 }
288 
289 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
290 {
291  int qleft = 0;
292  u8 linestatus = 0;
293  u8 error_mask = 0;
294  int n = 0;
295  int total = 0;
296  u16 head;
297  u16 tail;
298 
299  if (!ch)
300  return;
301 
302  /* cache head and tail of queue */
303  head = ch->ch_r_head & RQUEUEMASK;
304  tail = ch->ch_r_tail & RQUEUEMASK;
305 
306  /* Get our cached LSR */
307  linestatus = ch->ch_cached_lsr;
308  ch->ch_cached_lsr = 0;
309 
310  /* Store how much space we have left in the queue */
311  if ((qleft = tail - head - 1) < 0)
312  qleft += RQUEUEMASK + 1;
313 
314  /*
315  * If the UART is not in FIFO mode, force the FIFO copy to
316  * NOT be run, by setting total to 0.
317  *
318  * On the other hand, if the UART IS in FIFO mode, then ask
319  * the UART to give us an approximation of data it has RX'ed.
320  */
321  if (!(ch->ch_flags & CH_FIFO_ENABLED))
322  total = 0;
323  else {
324  total = readb(&ch->ch_neo_uart->rfifo);
325 
326  /*
327  * EXAR chip bug - RX FIFO COUNT - Fudge factor.
328  *
329  * This resolves a problem/bug with the Exar chip that sometimes
330  * returns a bogus value in the rfifo register.
331  * The count can be any where from 0-3 bytes "off".
332  * Bizarre, but true.
333  */
334  total -= 3;
335  }
336 
337  /*
338  * Finally, bound the copy to make sure we don't overflow
339  * our own queue...
340  * The byte by byte copy loop below this loop this will
341  * deal with the queue overflow possibility.
342  */
343  total = min(total, qleft);
344 
345  while (total > 0) {
346  /*
347  * Grab the linestatus register, we need to check
348  * to see if there are any errors in the FIFO.
349  */
350  linestatus = readb(&ch->ch_neo_uart->lsr);
351 
352  /*
353  * Break out if there is a FIFO error somewhere.
354  * This will allow us to go byte by byte down below,
355  * finding the exact location of the error.
356  */
357  if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
358  break;
359 
360  /* Make sure we don't go over the end of our queue */
361  n = min(((u32) total), (RQUEUESIZE - (u32) head));
362 
363  /*
364  * Cut down n even further if needed, this is to fix
365  * a problem with memcpy_fromio() with the Neo on the
366  * IBM pSeries platform.
367  * 15 bytes max appears to be the magic number.
368  */
369  n = min((u32) n, (u32) 12);
370 
371  /*
372  * Since we are grabbing the linestatus register, which
373  * will reset some bits after our read, we need to ensure
374  * we don't miss our TX FIFO emptys.
375  */
376  if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
377  ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
378 
379  linestatus = 0;
380 
381  /* Copy data from uart to the queue */
382  memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
383  /*
384  * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
385  * that all the data currently in the FIFO is free of
386  * breaks and parity/frame/orun errors.
387  */
388  memset(ch->ch_equeue + head, 0, n);
389 
390  /* Add to and flip head if needed */
391  head = (head + n) & RQUEUEMASK;
392  total -= n;
393  qleft -= n;
394  ch->ch_rxcount += n;
395  }
396 
397  /*
398  * Create a mask to determine whether we should
399  * insert the character (if any) into our queue.
400  */
401  if (ch->ch_c_iflag & IGNBRK)
402  error_mask |= UART_LSR_BI;
403 
404  /*
405  * Now cleanup any leftover bytes still in the UART.
406  * Also deal with any possible queue overflow here as well.
407  */
408  while (1) {
409 
410  /*
411  * Its possible we have a linestatus from the loop above
412  * this, so we "OR" on any extra bits.
413  */
414  linestatus |= readb(&ch->ch_neo_uart->lsr);
415 
416  /*
417  * If the chip tells us there is no more data pending to
418  * be read, we can then leave.
419  * But before we do, cache the linestatus, just in case.
420  */
421  if (!(linestatus & UART_LSR_DR)) {
422  ch->ch_cached_lsr = linestatus;
423  break;
424  }
425 
426  /* No need to store this bit */
427  linestatus &= ~UART_LSR_DR;
428 
429  /*
430  * Since we are grabbing the linestatus register, which
431  * will reset some bits after our read, we need to ensure
432  * we don't miss our TX FIFO emptys.
433  */
434  if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
435  linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
436  ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
437  }
438 
439  /*
440  * Discard character if we are ignoring the error mask.
441  */
442  if (linestatus & error_mask) {
443  u8 discard;
444  linestatus = 0;
445  memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
446  continue;
447  }
448 
449  /*
450  * If our queue is full, we have no choice but to drop some data.
451  * The assumption is that HWFLOW or SWFLOW should have stopped
452  * things way way before we got to this point.
453  *
454  * I decided that I wanted to ditch the oldest data first,
455  * I hope thats okay with everyone? Yes? Good.
456  */
457  while (qleft < 1) {
458  jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
459  "Queue full, dropping DATA:%x LSR:%x\n",
460  ch->ch_rqueue[tail], ch->ch_equeue[tail]);
461 
462  ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
463  ch->ch_err_overrun++;
464  qleft++;
465  }
466 
467  memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
468  ch->ch_equeue[head] = (u8) linestatus;
469 
470  jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
471  "DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]);
472 
473  /* Ditch any remaining linestatus value. */
474  linestatus = 0;
475 
476  /* Add to and flip head if needed */
477  head = (head + 1) & RQUEUEMASK;
478 
479  qleft--;
480  ch->ch_rxcount++;
481  }
482 
483  /*
484  * Write new final heads to channel structure.
485  */
486  ch->ch_r_head = head & RQUEUEMASK;
487  ch->ch_e_head = head & EQUEUEMASK;
488  jsm_input(ch);
489 }
490 
491 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
492 {
493  u16 head;
494  u16 tail;
495  int n;
496  int s;
497  int qlen;
498  u32 len_written = 0;
499  struct circ_buf *circ;
500 
501  if (!ch)
502  return;
503 
504  circ = &ch->uart_port.state->xmit;
505 
506  /* No data to write to the UART */
507  if (uart_circ_empty(circ))
508  return;
509 
510  /* If port is "stopped", don't send any data to the UART */
511  if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
512  return;
513  /*
514  * If FIFOs are disabled. Send data directly to txrx register
515  */
516  if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
517  u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
518 
519  ch->ch_cached_lsr |= lsrbits;
520  if (ch->ch_cached_lsr & UART_LSR_THRE) {
521  ch->ch_cached_lsr &= ~(UART_LSR_THRE);
522 
523  writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
524  jsm_printk(WRITE, INFO, &ch->ch_bd->pci_dev,
525  "Tx data: %x\n", circ->buf[circ->tail]);
526  circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1);
527  ch->ch_txcount++;
528  }
529  return;
530  }
531 
532  /*
533  * We have to do it this way, because of the EXAR TXFIFO count bug.
534  */
535  if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
536  return;
537 
538  n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
539 
540  /* cache head and tail of queue */
541  head = circ->head & (UART_XMIT_SIZE - 1);
542  tail = circ->tail & (UART_XMIT_SIZE - 1);
543  qlen = uart_circ_chars_pending(circ);
544 
545  /* Find minimum of the FIFO space, versus queue length */
546  n = min(n, qlen);
547 
548  while (n > 0) {
549 
550  s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
551  s = min(s, n);
552 
553  if (s <= 0)
554  break;
555 
556  memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
557  /* Add and flip queue if needed */
558  tail = (tail + s) & (UART_XMIT_SIZE - 1);
559  n -= s;
560  ch->ch_txcount += s;
561  len_written += s;
562  }
563 
564  /* Update the final tail */
565  circ->tail = tail & (UART_XMIT_SIZE - 1);
566 
567  if (len_written >= ch->ch_t_tlevel)
568  ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
569 
570  if (uart_circ_empty(circ))
571  uart_write_wakeup(&ch->uart_port);
572 }
573 
574 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
575 {
576  u8 msignals = signals;
577 
578  jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
579  "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals);
580 
581  /* Scrub off lower bits. They signify delta's, which I don't care about */
582  /* Keep DDCD and DDSR though */
583  msignals &= 0xf8;
584 
585  if (msignals & UART_MSR_DDCD)
586  uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
587  if (msignals & UART_MSR_DDSR)
588  uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
589  if (msignals & UART_MSR_DCD)
590  ch->ch_mistat |= UART_MSR_DCD;
591  else
592  ch->ch_mistat &= ~UART_MSR_DCD;
593 
594  if (msignals & UART_MSR_DSR)
595  ch->ch_mistat |= UART_MSR_DSR;
596  else
597  ch->ch_mistat &= ~UART_MSR_DSR;
598 
599  if (msignals & UART_MSR_RI)
600  ch->ch_mistat |= UART_MSR_RI;
601  else
602  ch->ch_mistat &= ~UART_MSR_RI;
603 
604  if (msignals & UART_MSR_CTS)
605  ch->ch_mistat |= UART_MSR_CTS;
606  else
607  ch->ch_mistat &= ~UART_MSR_CTS;
608 
609  jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
610  "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
611  ch->ch_portnum,
612  !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
613  !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
614  !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
615  !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
616  !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
617  !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
618 }
619 
620 /* Make the UART raise any of the output signals we want up */
621 static void neo_assert_modem_signals(struct jsm_channel *ch)
622 {
623  if (!ch)
624  return;
625 
626  writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
627 
628  /* flush write operation */
629  neo_pci_posting_flush(ch->ch_bd);
630 }
631 
632 /*
633  * Flush the WRITE FIFO on the Neo.
634  *
635  * NOTE: Channel lock MUST be held before calling this function!
636  */
637 static void neo_flush_uart_write(struct jsm_channel *ch)
638 {
639  u8 tmp = 0;
640  int i = 0;
641 
642  if (!ch)
643  return;
644 
645  writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
646 
647  for (i = 0; i < 10; i++) {
648 
649  /* Check to see if the UART feels it completely flushed the FIFO. */
650  tmp = readb(&ch->ch_neo_uart->isr_fcr);
651  if (tmp & 4) {
652  jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
653  "Still flushing TX UART... i: %d\n", i);
654  udelay(10);
655  }
656  else
657  break;
658  }
659 
660  ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
661 }
662 
663 
664 /*
665  * Flush the READ FIFO on the Neo.
666  *
667  * NOTE: Channel lock MUST be held before calling this function!
668  */
669 static void neo_flush_uart_read(struct jsm_channel *ch)
670 {
671  u8 tmp = 0;
672  int i = 0;
673 
674  if (!ch)
675  return;
676 
677  writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
678 
679  for (i = 0; i < 10; i++) {
680 
681  /* Check to see if the UART feels it completely flushed the FIFO. */
682  tmp = readb(&ch->ch_neo_uart->isr_fcr);
683  if (tmp & 2) {
684  jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
685  "Still flushing RX UART... i: %d\n", i);
686  udelay(10);
687  }
688  else
689  break;
690  }
691 }
692 
693 /*
694  * No locks are assumed to be held when calling this function.
695  */
696 static void neo_clear_break(struct jsm_channel *ch, int force)
697 {
698  unsigned long lock_flags;
699 
700  spin_lock_irqsave(&ch->ch_lock, lock_flags);
701 
702  /* Turn break off, and unset some variables */
703  if (ch->ch_flags & CH_BREAK_SENDING) {
704  u8 temp = readb(&ch->ch_neo_uart->lcr);
705  writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
706 
707  ch->ch_flags &= ~(CH_BREAK_SENDING);
708  jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
709  "clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies);
710 
711  /* flush write operation */
712  neo_pci_posting_flush(ch->ch_bd);
713  }
714  spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
715 }
716 
717 /*
718  * Parse the ISR register.
719  */
720 static inline void neo_parse_isr(struct jsm_board *brd, u32 port)
721 {
722  struct jsm_channel *ch;
723  u8 isr;
724  u8 cause;
725  unsigned long lock_flags;
726 
727  if (!brd)
728  return;
729 
730  if (port > brd->maxports)
731  return;
732 
733  ch = brd->channels[port];
734  if (!ch)
735  return;
736 
737  /* Here we try to figure out what caused the interrupt to happen */
738  while (1) {
739 
740  isr = readb(&ch->ch_neo_uart->isr_fcr);
741 
742  /* Bail if no pending interrupt */
743  if (isr & UART_IIR_NO_INT)
744  break;
745 
746  /*
747  * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
748  */
749  isr &= ~(UART_17158_IIR_FIFO_ENABLED);
750 
751  jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
752  "%s:%d isr: %x\n", __FILE__, __LINE__, isr);
753 
754  if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
755  /* Read data from uart -> queue */
756  neo_copy_data_from_uart_to_queue(ch);
757 
758  /* Call our tty layer to enforce queue flow control if needed. */
759  spin_lock_irqsave(&ch->ch_lock, lock_flags);
760  jsm_check_queue_flow_control(ch);
761  spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
762  }
763 
764  if (isr & UART_IIR_THRI) {
765  /* Transfer data (if any) from Write Queue -> UART. */
766  spin_lock_irqsave(&ch->ch_lock, lock_flags);
767  ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
768  spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
769  neo_copy_data_from_queue_to_uart(ch);
770  }
771 
772  if (isr & UART_17158_IIR_XONXOFF) {
773  cause = readb(&ch->ch_neo_uart->xoffchar1);
774 
775  jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
776  "Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause);
777 
778  /*
779  * Since the UART detected either an XON or
780  * XOFF match, we need to figure out which
781  * one it was, so we can suspend or resume data flow.
782  */
783  spin_lock_irqsave(&ch->ch_lock, lock_flags);
784  if (cause == UART_17158_XON_DETECT) {
785  /* Is output stopped right now, if so, resume it */
786  if (brd->channels[port]->ch_flags & CH_STOP) {
787  ch->ch_flags &= ~(CH_STOP);
788  }
789  jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
790  "Port %d. XON detected in incoming data\n", port);
791  }
792  else if (cause == UART_17158_XOFF_DETECT) {
793  if (!(brd->channels[port]->ch_flags & CH_STOP)) {
794  ch->ch_flags |= CH_STOP;
795  jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
796  "Setting CH_STOP\n");
797  }
798  jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
799  "Port: %d. XOFF detected in incoming data\n", port);
800  }
801  spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
802  }
803 
804  if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
805  /*
806  * If we get here, this means the hardware is doing auto flow control.
807  * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
808  */
809  cause = readb(&ch->ch_neo_uart->mcr);
810 
811  /* Which pin is doing auto flow? RTS or DTR? */
812  spin_lock_irqsave(&ch->ch_lock, lock_flags);
813  if ((cause & 0x4) == 0) {
814  if (cause & UART_MCR_RTS)
815  ch->ch_mostat |= UART_MCR_RTS;
816  else
817  ch->ch_mostat &= ~(UART_MCR_RTS);
818  } else {
819  if (cause & UART_MCR_DTR)
820  ch->ch_mostat |= UART_MCR_DTR;
821  else
822  ch->ch_mostat &= ~(UART_MCR_DTR);
823  }
824  spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
825  }
826 
827  /* Parse any modem signal changes */
828  jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
829  "MOD_STAT: sending to parse_modem_sigs\n");
830  neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
831  }
832 }
833 
834 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
835 {
836  struct jsm_channel *ch;
837  int linestatus;
838  unsigned long lock_flags;
839 
840  if (!brd)
841  return;
842 
843  if (port > brd->maxports)
844  return;
845 
846  ch = brd->channels[port];
847  if (!ch)
848  return;
849 
850  linestatus = readb(&ch->ch_neo_uart->lsr);
851 
852  jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
853  "%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus);
854 
855  ch->ch_cached_lsr |= linestatus;
856 
857  if (ch->ch_cached_lsr & UART_LSR_DR) {
858  /* Read data from uart -> queue */
859  neo_copy_data_from_uart_to_queue(ch);
860  spin_lock_irqsave(&ch->ch_lock, lock_flags);
861  jsm_check_queue_flow_control(ch);
862  spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
863  }
864 
865  /*
866  * This is a special flag. It indicates that at least 1
867  * RX error (parity, framing, or break) has happened.
868  * Mark this in our struct, which will tell me that I have
869  *to do the special RX+LSR read for this FIFO load.
870  */
871  if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
872  jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
873  "%s:%d Port: %d Got an RX error, need to parse LSR\n",
874  __FILE__, __LINE__, port);
875 
876  /*
877  * The next 3 tests should *NOT* happen, as the above test
878  * should encapsulate all 3... At least, thats what Exar says.
879  */
880 
881  if (linestatus & UART_LSR_PE) {
882  ch->ch_err_parity++;
883  jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
884  "%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port);
885  }
886 
887  if (linestatus & UART_LSR_FE) {
888  ch->ch_err_frame++;
889  jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
890  "%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port);
891  }
892 
893  if (linestatus & UART_LSR_BI) {
894  ch->ch_err_break++;
895  jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
896  "%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port);
897  }
898 
899  if (linestatus & UART_LSR_OE) {
900  /*
901  * Rx Oruns. Exar says that an orun will NOT corrupt
902  * the FIFO. It will just replace the holding register
903  * with this new data byte. So basically just ignore this.
904  * Probably we should eventually have an orun stat in our driver...
905  */
906  ch->ch_err_overrun++;
907  jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
908  "%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port);
909  }
910 
911  if (linestatus & UART_LSR_THRE) {
912  spin_lock_irqsave(&ch->ch_lock, lock_flags);
913  ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
914  spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
915 
916  /* Transfer data (if any) from Write Queue -> UART. */
917  neo_copy_data_from_queue_to_uart(ch);
918  }
919  else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
920  spin_lock_irqsave(&ch->ch_lock, lock_flags);
921  ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
922  spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
923 
924  /* Transfer data (if any) from Write Queue -> UART. */
925  neo_copy_data_from_queue_to_uart(ch);
926  }
927 }
928 
929 /*
930  * neo_param()
931  * Send any/all changes to the line to the UART.
932  */
933 static void neo_param(struct jsm_channel *ch)
934 {
935  u8 lcr = 0;
936  u8 uart_lcr, ier;
937  u32 baud;
938  int quot;
939  struct jsm_board *bd;
940 
941  bd = ch->ch_bd;
942  if (!bd)
943  return;
944 
945  /*
946  * If baud rate is zero, flush queues, and set mval to drop DTR.
947  */
948  if ((ch->ch_c_cflag & (CBAUD)) == 0) {
949  ch->ch_r_head = ch->ch_r_tail = 0;
950  ch->ch_e_head = ch->ch_e_tail = 0;
951 
952  neo_flush_uart_write(ch);
953  neo_flush_uart_read(ch);
954 
955  ch->ch_flags |= (CH_BAUD0);
956  ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
957  neo_assert_modem_signals(ch);
958  return;
959 
960  } else {
961  int i;
962  unsigned int cflag;
963  static struct {
964  unsigned int rate;
965  unsigned int cflag;
966  } baud_rates[] = {
967  { 921600, B921600 },
968  { 460800, B460800 },
969  { 230400, B230400 },
970  { 115200, B115200 },
971  { 57600, B57600 },
972  { 38400, B38400 },
973  { 19200, B19200 },
974  { 9600, B9600 },
975  { 4800, B4800 },
976  { 2400, B2400 },
977  { 1200, B1200 },
978  { 600, B600 },
979  { 300, B300 },
980  { 200, B200 },
981  { 150, B150 },
982  { 134, B134 },
983  { 110, B110 },
984  { 75, B75 },
985  { 50, B50 },
986  };
987 
988  cflag = C_BAUD(ch->uart_port.state->port.tty);
989  baud = 9600;
990  for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
991  if (baud_rates[i].cflag == cflag) {
992  baud = baud_rates[i].rate;
993  break;
994  }
995  }
996 
997  if (ch->ch_flags & CH_BAUD0)
998  ch->ch_flags &= ~(CH_BAUD0);
999  }
1000 
1001  if (ch->ch_c_cflag & PARENB)
1002  lcr |= UART_LCR_PARITY;
1003 
1004  if (!(ch->ch_c_cflag & PARODD))
1005  lcr |= UART_LCR_EPAR;
1006 
1007  /*
1008  * Not all platforms support mark/space parity,
1009  * so this will hide behind an ifdef.
1010  */
1011 #ifdef CMSPAR
1012  if (ch->ch_c_cflag & CMSPAR)
1013  lcr |= UART_LCR_SPAR;
1014 #endif
1015 
1016  if (ch->ch_c_cflag & CSTOPB)
1017  lcr |= UART_LCR_STOP;
1018 
1019  switch (ch->ch_c_cflag & CSIZE) {
1020  case CS5:
1021  lcr |= UART_LCR_WLEN5;
1022  break;
1023  case CS6:
1024  lcr |= UART_LCR_WLEN6;
1025  break;
1026  case CS7:
1027  lcr |= UART_LCR_WLEN7;
1028  break;
1029  case CS8:
1030  default:
1031  lcr |= UART_LCR_WLEN8;
1032  break;
1033  }
1034 
1035  ier = readb(&ch->ch_neo_uart->ier);
1036  uart_lcr = readb(&ch->ch_neo_uart->lcr);
1037 
1038  if (baud == 0)
1039  baud = 9600;
1040 
1041  quot = ch->ch_bd->bd_dividend / baud;
1042 
1043  if (quot != 0) {
1044  writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1045  writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1046  writeb((quot >> 8), &ch->ch_neo_uart->ier);
1047  writeb(lcr, &ch->ch_neo_uart->lcr);
1048  }
1049 
1050  if (uart_lcr != lcr)
1051  writeb(lcr, &ch->ch_neo_uart->lcr);
1052 
1053  if (ch->ch_c_cflag & CREAD)
1054  ier |= (UART_IER_RDI | UART_IER_RLSI);
1055 
1056  ier |= (UART_IER_THRI | UART_IER_MSI);
1057 
1058  writeb(ier, &ch->ch_neo_uart->ier);
1059 
1060  /* Set new start/stop chars */
1061  neo_set_new_start_stop_chars(ch);
1062 
1063  if (ch->ch_c_cflag & CRTSCTS)
1064  neo_set_cts_flow_control(ch);
1065  else if (ch->ch_c_iflag & IXON) {
1066  /* If start/stop is set to disable, then we should disable flow control */
1067  if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1068  neo_set_no_output_flow_control(ch);
1069  else
1070  neo_set_ixon_flow_control(ch);
1071  }
1072  else
1073  neo_set_no_output_flow_control(ch);
1074 
1075  if (ch->ch_c_cflag & CRTSCTS)
1076  neo_set_rts_flow_control(ch);
1077  else if (ch->ch_c_iflag & IXOFF) {
1078  /* If start/stop is set to disable, then we should disable flow control */
1079  if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1080  neo_set_no_input_flow_control(ch);
1081  else
1082  neo_set_ixoff_flow_control(ch);
1083  }
1084  else
1085  neo_set_no_input_flow_control(ch);
1086  /*
1087  * Adjust the RX FIFO Trigger level if baud is less than 9600.
1088  * Not exactly elegant, but this is needed because of the Exar chip's
1089  * delay on firing off the RX FIFO interrupt on slower baud rates.
1090  */
1091  if (baud < 9600) {
1092  writeb(1, &ch->ch_neo_uart->rfifo);
1093  ch->ch_r_tlevel = 1;
1094  }
1095 
1096  neo_assert_modem_signals(ch);
1097 
1098  /* Get current status of the modem signals now */
1099  neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1100  return;
1101 }
1102 
1103 /*
1104  * jsm_neo_intr()
1105  *
1106  * Neo specific interrupt handler.
1107  */
1108 static irqreturn_t neo_intr(int irq, void *voidbrd)
1109 {
1110  struct jsm_board *brd = voidbrd;
1111  struct jsm_channel *ch;
1112  int port = 0;
1113  int type = 0;
1114  int current_port;
1115  u32 tmp;
1116  u32 uart_poll;
1117  unsigned long lock_flags;
1118  unsigned long lock_flags2;
1119  int outofloop_count = 0;
1120 
1121  /* Lock out the slow poller from running on this board. */
1122  spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1123 
1124  /*
1125  * Read in "extended" IRQ information from the 32bit Neo register.
1126  * Bits 0-7: What port triggered the interrupt.
1127  * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1128  */
1129  uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1130 
1131  jsm_printk(INTR, INFO, &brd->pci_dev,
1132  "%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll);
1133 
1134  if (!uart_poll) {
1135  jsm_printk(INTR, INFO, &brd->pci_dev,
1136  "Kernel interrupted to me, but no pending interrupts...\n");
1137  spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1138  return IRQ_NONE;
1139  }
1140 
1141  /* At this point, we have at least SOMETHING to service, dig further... */
1142 
1143  current_port = 0;
1144 
1145  /* Loop on each port */
1146  while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1147 
1148  tmp = uart_poll;
1149  outofloop_count++;
1150 
1151  /* Check current port to see if it has interrupt pending */
1152  if ((tmp & jsm_offset_table[current_port]) != 0) {
1153  port = current_port;
1154  type = tmp >> (8 + (port * 3));
1155  type &= 0x7;
1156  } else {
1157  current_port++;
1158  continue;
1159  }
1160 
1161  jsm_printk(INTR, INFO, &brd->pci_dev,
1162  "%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type);
1163 
1164  /* Remove this port + type from uart_poll */
1165  uart_poll &= ~(jsm_offset_table[port]);
1166 
1167  if (!type) {
1168  /* If no type, just ignore it, and move onto next port */
1169  jsm_printk(INTR, ERR, &brd->pci_dev,
1170  "Interrupt with no type! port: %d\n", port);
1171  continue;
1172  }
1173 
1174  /* Switch on type of interrupt we have */
1175  switch (type) {
1176 
1177  case UART_17158_RXRDY_TIMEOUT:
1178  /*
1179  * RXRDY Time-out is cleared by reading data in the
1180  * RX FIFO until it falls below the trigger level.
1181  */
1182 
1183  /* Verify the port is in range. */
1184  if (port > brd->nasync)
1185  continue;
1186 
1187  ch = brd->channels[port];
1188  neo_copy_data_from_uart_to_queue(ch);
1189 
1190  /* Call our tty layer to enforce queue flow control if needed. */
1191  spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1192  jsm_check_queue_flow_control(ch);
1193  spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1194 
1195  continue;
1196 
1197  case UART_17158_RX_LINE_STATUS:
1198  /*
1199  * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1200  */
1201  neo_parse_lsr(brd, port);
1202  continue;
1203 
1204  case UART_17158_TXRDY:
1205  /*
1206  * TXRDY interrupt clears after reading ISR register for the UART channel.
1207  */
1208 
1209  /*
1210  * Yes, this is odd...
1211  * Why would I check EVERY possibility of type of
1212  * interrupt, when we know its TXRDY???
1213  * Becuz for some reason, even tho we got triggered for TXRDY,
1214  * it seems to be occasionally wrong. Instead of TX, which
1215  * it should be, I was getting things like RXDY too. Weird.
1216  */
1217  neo_parse_isr(brd, port);
1218  continue;
1219 
1220  case UART_17158_MSR:
1221  /*
1222  * MSR or flow control was seen.
1223  */
1224  neo_parse_isr(brd, port);
1225  continue;
1226 
1227  default:
1228  /*
1229  * The UART triggered us with a bogus interrupt type.
1230  * It appears the Exar chip, when REALLY bogged down, will throw
1231  * these once and awhile.
1232  * Its harmless, just ignore it and move on.
1233  */
1234  jsm_printk(INTR, ERR, &brd->pci_dev,
1235  "%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type);
1236  continue;
1237  }
1238  }
1239 
1240  spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1241 
1242  jsm_printk(INTR, INFO, &brd->pci_dev, "finish.\n");
1243  return IRQ_HANDLED;
1244 }
1245 
1246 /*
1247  * Neo specific way of turning off the receiver.
1248  * Used as a way to enforce queue flow control when in
1249  * hardware flow control mode.
1250  */
1251 static void neo_disable_receiver(struct jsm_channel *ch)
1252 {
1253  u8 tmp = readb(&ch->ch_neo_uart->ier);
1254  tmp &= ~(UART_IER_RDI);
1255  writeb(tmp, &ch->ch_neo_uart->ier);
1256 
1257  /* flush write operation */
1258  neo_pci_posting_flush(ch->ch_bd);
1259 }
1260 
1261 
1262 /*
1263  * Neo specific way of turning on the receiver.
1264  * Used as a way to un-enforce queue flow control when in
1265  * hardware flow control mode.
1266  */
1267 static void neo_enable_receiver(struct jsm_channel *ch)
1268 {
1269  u8 tmp = readb(&ch->ch_neo_uart->ier);
1270  tmp |= (UART_IER_RDI);
1271  writeb(tmp, &ch->ch_neo_uart->ier);
1272 
1273  /* flush write operation */
1274  neo_pci_posting_flush(ch->ch_bd);
1275 }
1276 
1277 static void neo_send_start_character(struct jsm_channel *ch)
1278 {
1279  if (!ch)
1280  return;
1281 
1282  if (ch->ch_startc != __DISABLED_CHAR) {
1283  ch->ch_xon_sends++;
1284  writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1285 
1286  /* flush write operation */
1287  neo_pci_posting_flush(ch->ch_bd);
1288  }
1289 }
1290 
1291 static void neo_send_stop_character(struct jsm_channel *ch)
1292 {
1293  if (!ch)
1294  return;
1295 
1296  if (ch->ch_stopc != __DISABLED_CHAR) {
1297  ch->ch_xoff_sends++;
1298  writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1299 
1300  /* flush write operation */
1301  neo_pci_posting_flush(ch->ch_bd);
1302  }
1303 }
1304 
1305 /*
1306  * neo_uart_init
1307  */
1308 static void neo_uart_init(struct jsm_channel *ch)
1309 {
1310  writeb(0, &ch->ch_neo_uart->ier);
1311  writeb(0, &ch->ch_neo_uart->efr);
1312  writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1313 
1314  /* Clear out UART and FIFO */
1315  readb(&ch->ch_neo_uart->txrx);
1316  writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1317  readb(&ch->ch_neo_uart->lsr);
1318  readb(&ch->ch_neo_uart->msr);
1319 
1320  ch->ch_flags |= CH_FIFO_ENABLED;
1321 
1322  /* Assert any signals we want up */
1323  writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1324 }
1325 
1326 /*
1327  * Make the UART completely turn off.
1328  */
1329 static void neo_uart_off(struct jsm_channel *ch)
1330 {
1331  /* Turn off UART enhanced bits */
1332  writeb(0, &ch->ch_neo_uart->efr);
1333 
1334  /* Stop all interrupts from occurring. */
1335  writeb(0, &ch->ch_neo_uart->ier);
1336 }
1337 
1338 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1339 {
1340  u8 left = 0;
1341  u8 lsr = readb(&ch->ch_neo_uart->lsr);
1342 
1343  /* We must cache the LSR as some of the bits get reset once read... */
1344  ch->ch_cached_lsr |= lsr;
1345 
1346  /* Determine whether the Transmitter is empty or not */
1347  if (!(lsr & UART_LSR_TEMT))
1348  left = 1;
1349  else {
1350  ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1351  left = 0;
1352  }
1353 
1354  return left;
1355 }
1356 
1357 /* Channel lock MUST be held by the calling function! */
1358 static void neo_send_break(struct jsm_channel *ch)
1359 {
1360  /*
1361  * Set the time we should stop sending the break.
1362  * If we are already sending a break, toss away the existing
1363  * time to stop, and use this new value instead.
1364  */
1365 
1366  /* Tell the UART to start sending the break */
1367  if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1368  u8 temp = readb(&ch->ch_neo_uart->lcr);
1369  writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1370  ch->ch_flags |= (CH_BREAK_SENDING);
1371 
1372  /* flush write operation */
1373  neo_pci_posting_flush(ch->ch_bd);
1374  }
1375 }
1376 
1377 /*
1378  * neo_send_immediate_char.
1379  *
1380  * Sends a specific character as soon as possible to the UART,
1381  * jumping over any bytes that might be in the write queue.
1382  *
1383  * The channel lock MUST be held by the calling function.
1384  */
1385 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1386 {
1387  if (!ch)
1388  return;
1389 
1390  writeb(c, &ch->ch_neo_uart->txrx);
1391 
1392  /* flush write operation */
1393  neo_pci_posting_flush(ch->ch_bd);
1394 }
1395 
1396 struct board_ops jsm_neo_ops = {
1397  .intr = neo_intr,
1398  .uart_init = neo_uart_init,
1399  .uart_off = neo_uart_off,
1400  .param = neo_param,
1401  .assert_modem_signals = neo_assert_modem_signals,
1402  .flush_uart_write = neo_flush_uart_write,
1403  .flush_uart_read = neo_flush_uart_read,
1404  .disable_receiver = neo_disable_receiver,
1405  .enable_receiver = neo_enable_receiver,
1406  .send_break = neo_send_break,
1407  .clear_break = neo_clear_break,
1408  .send_start_character = neo_send_start_character,
1409  .send_stop_character = neo_send_stop_character,
1410  .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
1411  .get_uart_bytes_left = neo_get_uart_bytes_left,
1412  .send_immediate_char = neo_send_immediate_char
1413 };
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