#include <linux/delay.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/pdc.h>
#include <asm/pdcpat.h>
#include <asm/page.h>
#include <asm/ropes.h>
#include <asm/hardware.h>
#include <asm/parisc-device.h>
#include <asm/io.h>

Macros
#define	DBG(x...)

#define	DBG_PORT(x...)

#define	DBG_CFG(x...)

#define	DBG_PAT(x...)

#define	MODULE_NAME "LBA"

#define	LBA_PORT_BASE (PCI_F_EXTEND \| 0xfee00000UL)

#define	LBA_FLAG_SKIP_PROBE 0x10

#define	LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)

#define	LBA_DEV(d) ((struct lba_device *) (d))

#define	LBA_MAX_NUM_BUSES 8

#define	READ_U8(addr) __raw_readb(addr)

#define	READ_U16(addr) __raw_readw(addr)

#define	READ_U32(addr) __raw_readl(addr)

#define	WRITE_U8(value, addr) __raw_writeb(value, addr)

#define	WRITE_U16(value, addr) __raw_writew(value, addr)

#define	WRITE_U32(value, addr) __raw_writel(value, addr)

#define	READ_REG8(addr) readb(addr)

#define	READ_REG16(addr) readw(addr)

#define	READ_REG32(addr) readl(addr)

#define	READ_REG64(addr) readq(addr)

#define	WRITE_REG8(value, addr) writeb(value, addr)

#define	WRITE_REG16(value, addr) writew(value, addr)

#define	WRITE_REG32(value, addr) writel(value, addr)

#define	LBA_CFG_TOK(bus, dfn) ((u32) ((bus)<<16 \| (dfn)<<8))

#define	LBA_CFG_BUS(tok) ((u8) ((tok)>>16))

#define	LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)

#define	LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)

#define	ROPES_PER_IOC 8

#define	LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))

#define	LBA_CFG_SETUP(d, tok)

#define	LBA_CFG_PROBE(d, tok)

#define	LBA_MASTER_ABORT_ERROR 0xc

#define	LBA_FATAL_ERROR 0x10

#define	LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error)

#define	LBA_CFG_TR4_ADDR_SETUP(d, addr) WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);

#define	LBA_CFG_ADDR_SETUP(d, addr)

#define	LBA_CFG_RESTORE(d, base)

#define	truncate_pat_collision(r, n) (0)

#define	LBA_PORT_IN(size, mask)

#define	LBA_PORT_OUT(size, mask)

#define	lba_pat_port_ops lba_astro_port_ops

#define	lba_pat_resources(pa_dev, lba_dev)

Functions
void	sba_distributed_lmmio (struct parisc_device , struct resource )

void	sba_directed_lmmio (struct parisc_device , struct resource )

void __init	lba_init (void)

void	lba_set_iregs (struct parisc_device *lba, u32 ibase, u32 imask)

Macro Definition Documentation

#define DBG ( x... )

Definition at line 63 of file lba_pci.c.

#define DBG_CFG ( x... )

Definition at line 75 of file lba_pci.c.

#define DBG_PAT ( x... )

Definition at line 81 of file lba_pci.c.

#define DBG_PORT ( x... )

Definition at line 69 of file lba_pci.c.

#define LBA_CFG_ADDR_SETUP	(	d,
		addr
	)

Value:

{                   \
    WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);  \
    /*                                  \
     * Read address register to ensure that LBA is the bus master,  \
     * which implies that DMA traffic has stopped when DMA arb is off.  \
     */                                 \
    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);    \
}

Definition at line 282 of file lba_pci.c.

#define LBA_CFG_BUS ( tok ) ((u8) ((tok)>>16))

Definition at line 146 of file lba_pci.c.

#define LBA_CFG_DEV ( tok ) ((u8) ((tok)>>11) & 0x1f)

Definition at line 147 of file lba_pci.c.

#define LBA_CFG_FUNC ( tok ) ((u8) ((tok)>>8 ) & 0x7)

Definition at line 148 of file lba_pci.c.

#define LBA_CFG_MASTER_ABORT_CHECK	(	d,
		base,
		tok,
		error
	)

Value:

{       \
    u32 error_status = 0;                       \
    /*                                  \
     * Set clear enable (CE) bit. Unset by HW when new          \
     * errors are logged -- LBA HW ERS section 14.3.3).     \
     */                                 \
    WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
    error_status = READ_REG32(base + LBA_ERROR_STATUS);     \
    if ((error_status & 0x1f) != 0) {                   \
    /*                              \
     * Fail the config read request.                \
     */                             \
    error = 1;                          \
    if ((error_status & LBA_FATAL_ERROR) == 0) {            \
        /*                              \
         * Clear error status (if fatal bit not set) by setting \
         * clear error log bit (CL).                \
         */                             \
        WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
    }                               \
    }                                   \
}

Definition at line 264 of file lba_pci.c.

#define LBA_CFG_PROBE	(	d,
		tok
	)

Value:

{               \
    /*                                  \
     * Setup Vendor ID write and read back the address register     \
     * to make sure that LBA is the bus master.             \
     */                                 \
    WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
    /*                                  \
     * Read address register to ensure that LBA is the bus master,  \
     * which implies that DMA traffic has stopped when DMA arb is off.  \
     */                                 \
    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);    \
    /*                                  \
     * Generate a cfg write cycle (will have no affect on       \
     * Vendor ID register since read-only).             \
     */                                 \
    WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA);     \
    /*                                  \
     * Make sure write has completed before proceeding further,     \
     * i.e. before setting clear enable.                \
     */                                 \
    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);    \
}

Definition at line 225 of file lba_pci.c.

#define LBA_CFG_RESTORE	(	d,
		base
	)

Value:

{                   \
    /*                                  \
     * Restore status control register (turn off clear enable).     \
     */                                 \
    WRITE_REG32(status_control, base + LBA_STAT_CTL);           \
    /*                                  \
     * Restore error config register (turn off smart mode).     \
     */                                 \
    WRITE_REG32(error_config, base + LBA_ERROR_CONFIG);         \
    /*                              \
     * Restore arb mask register (reenables DMA arbitration).   \
     */                             \
    WRITE_REG32(arb_mask, base + LBA_ARB_MASK);         \
}

Definition at line 289 of file lba_pci.c.

#define LBA_CFG_SETUP	(	d,
		tok
	)

Value:

{               \
    /* Save contents of error config register.  */          \
    error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);     \
\
    /* Save contents of status control register.  */            \
    status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);       \
\
    /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA      \
    ** arbitration for full bus walks.                  \
    */                                  \
    /* Save contents of arb mask register. */           \
    arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK);     \
\
    /*                              \
     * Turn off all device arbitration bits (i.e. everything    \
     * except arbitration enable bit).              \
     */                             \
    WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK);      \
\
    /*                                  \
     * Set the smart mode bit so that master aborts don't cause     \
     * LBA to go into PCI fatal mode (required).            \
     */                                 \
    WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG);    \
}

Definition at line 206 of file lba_pci.c.

#define LBA_CFG_TOK	(	bus,
		dfn
	)	((u32) ((bus)<<16 \| (dfn)<<8))

Definition at line 145 of file lba_pci.c.

#define LBA_CFG_TR4_ADDR_SETUP	(	d,
		addr
	)	WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);

Definition at line 279 of file lba_pci.c.

#define LBA_DEV ( d ) ((struct lba_device *) (d))

Definition at line 114 of file lba_pci.c.

#define LBA_FATAL_ERROR 0x10

Definition at line 262 of file lba_pci.c.

#define LBA_FLAG_SKIP_PROBE 0x10

Definition at line 108 of file lba_pci.c.

#define LBA_MASTER_ABORT_ERROR 0xc

Definition at line 261 of file lba_pci.c.

#define LBA_MAX_NUM_BUSES 8

Definition at line 121 of file lba_pci.c.

#define LBA_NUM ( x ) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))

Definition at line 156 of file lba_pci.c.

#define lba_pat_port_ops lba_astro_port_ops

Definition at line 1033 of file lba_pci.c.

#define lba_pat_resources	(	pa_dev,
		lba_dev
	)

Definition at line 1034 of file lba_pci.c.

#define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)

Definition at line 102 of file lba_pci.c.

#define LBA_PORT_IN	(	size,
		mask
	)

Value:

static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
{ \
    u##size t; \
    t = READ_REG##size(astro_iop_base + addr); \
    DBG_PORT(" 0x%x\n", t); \
    return (t); \
}

Definition at line 766 of file lba_pci.c.

#define LBA_PORT_OUT	(	size,
		mask
	)

Value:

static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
{ \
    DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \
    WRITE_REG##size(val, astro_iop_base + addr); \
    if (LBA_DEV(d)->hw_rev < 3) \
        lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
}

Definition at line 807 of file lba_pci.c.

#define LBA_SKIP_PROBE ( d ) ((d)->flags & LBA_FLAG_SKIP_PROBE)

Definition at line 110 of file lba_pci.c.

#define MODULE_NAME "LBA"

Definition at line 99 of file lba_pci.c.

#define READ_REG16 ( addr ) readw(addr)

Definition at line 137 of file lba_pci.c.

#define READ_REG32 ( addr ) readl(addr)

Definition at line 138 of file lba_pci.c.

#define READ_REG64 ( addr ) readq(addr)

Definition at line 139 of file lba_pci.c.

#define READ_REG8 ( addr ) readb(addr)

Definition at line 136 of file lba_pci.c.

#define READ_U16 ( addr ) __raw_readw(addr)

Definition at line 130 of file lba_pci.c.

#define READ_U32 ( addr ) __raw_readl(addr)

Definition at line 131 of file lba_pci.c.

#define READ_U8 ( addr ) __raw_readb(addr)

Definition at line 129 of file lba_pci.c.

#define ROPES_PER_IOC 8

Definition at line 155 of file lba_pci.c.

#define truncate_pat_collision	(	r,
		n
	)	(0)

Definition at line 580 of file lba_pci.c.

#define WRITE_REG16	(	value,
		addr
	)	writew(value, addr)

Definition at line 141 of file lba_pci.c.

#define WRITE_REG32	(	value,
		addr
	)	writel(value, addr)

Definition at line 142 of file lba_pci.c.

#define WRITE_REG8	(	value,
		addr
	)	writeb(value, addr)

Definition at line 140 of file lba_pci.c.

#define WRITE_U16	(	value,
		addr
	)	__raw_writew(value, addr)

Definition at line 133 of file lba_pci.c.

#define WRITE_U32	(	value,
		addr
	)	__raw_writel(value, addr)

Definition at line 134 of file lba_pci.c.

#define WRITE_U8	(	value,
		addr
	)	__raw_writeb(value, addr)

Definition at line 132 of file lba_pci.c.

Function Documentation

void __init lba_init ( void )

Definition at line 1534 of file lba_pci.c.

void lba_set_iregs	(	struct parisc_device *	lba,
		u32	ibase,
		u32	imask
	)

Definition at line 1544 of file lba_pci.c.

void sba_directed_lmmio	(	struct parisc_device *	pci_hba,
		struct resource *	r
	)

sba_directed_lmmio - return first directed LMMIO range routed to rope : The parisc device. : resource PCI host controller wants start/end fields assigned.

For the given parisc PCI controller, determine if any direct ranges are routed down the corresponding rope.

Definition at line 2033 of file sba_iommu.c.

void sba_distributed_lmmio	(	struct parisc_device *	pci_hba,
		struct resource *	r
	)

sba_distributed_lmmio - return portion of distributed LMMIO range : The parisc device. : resource PCI host controller wants start/end fields assigned.

For the given parisc PCI controller, return portion of distributed LMMIO range. The distributed LMMIO is always present and it's just a question of the base address and size of the range.

Definition at line 2076 of file sba_iommu.c.

Macros

Functions

Macro Definition Documentation

Function Documentation