#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_mtd.h>
#include <linux/of_gpio.h>
#include <linux/mtd/lpc32xx_slc.h>

Data Structures
struct	lpc32xx_nand_cfg_slc

struct	lpc32xx_nand_host

Macros
#define	LPC32XX_MODNAME "lpc32xx-nand"

#define	SLC_DATA(x) (x + 0x000)

#define	SLC_ADDR(x) (x + 0x004)

#define	SLC_CMD(x) (x + 0x008)

#define	SLC_STOP(x) (x + 0x00C)

#define	SLC_CTRL(x) (x + 0x010)

#define	SLC_CFG(x) (x + 0x014)

#define	SLC_STAT(x) (x + 0x018)

#define	SLC_INT_STAT(x) (x + 0x01C)

#define	SLC_IEN(x) (x + 0x020)

#define	SLC_ISR(x) (x + 0x024)

#define	SLC_ICR(x) (x + 0x028)

#define	SLC_TAC(x) (x + 0x02C)

#define	SLC_TC(x) (x + 0x030)

#define	SLC_ECC(x) (x + 0x034)

#define	SLC_DMA_DATA(x) (x + 0x038)

#define	SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */

#define	SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */

#define	SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */

#define	SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */

#define	SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */

#define	SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */

#define	SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */

#define	SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */

#define	SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */

#define	SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */

#define	SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */

#define	SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */

#define	SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */

#define	SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */

#define	SLCTAC_WDR(n) (((n) & 0xF) << 28)

#define	SLCTAC_WWIDTH(n) (((n) & 0xF) << 24)

#define	SLCTAC_WHOLD(n) (((n) & 0xF) << 20)

#define	SLCTAC_WSETUP(n) (((n) & 0xF) << 16)

#define	SLCTAC_RDR(n) (((n) & 0xF) << 12)

#define	SLCTAC_RWIDTH(n) (((n) & 0xF) << 8)

#define	SLCTAC_RHOLD(n) (((n) & 0xF) << 4)

#define	SLCTAC_RSETUP(n) (((n) & 0xF) << 0)

#define	SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF)

#define	SLCECC_TO_COLPAR(n) ((n) & 0x3F)

#define	LPC32XX_DMA_DATA_SIZE 4096

#define	LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4)

#define	LPC32XX_SLC_DEV_ECC_BYTES 3

#define	LPC32XX_DEF_BUS_RATE 133250000

#define	LPC32XX_DMA_TIMEOUT 100

#define	lpc32xx_nand_resume NULL

#define	lpc32xx_nand_suspend NULL

Functions
	MODULE_DEVICE_TABLE (of, lpc32xx_nand_match)

	module_platform_driver (lpc32xx_nand_driver)

	MODULE_LICENSE ("GPL")

	MODULE_AUTHOR ("Kevin Wells <[email protected]>")

	MODULE_AUTHOR ("Roland Stigge <[email protected]>")

	MODULE_DESCRIPTION ("NAND driver for the NXP LPC32XX SLC controller")

Macro Definition Documentation

#define LPC32XX_DEF_BUS_RATE 133250000

Definition at line 137 of file lpc32xx_slc.c.

#define LPC32XX_DMA_DATA_SIZE 4096

Definition at line 126 of file lpc32xx_slc.c.

#define LPC32XX_DMA_TIMEOUT 100

Definition at line 140 of file lpc32xx_slc.c.

#define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4)

Definition at line 127 of file lpc32xx_slc.c.

#define LPC32XX_MODNAME "lpc32xx-nand"

Definition at line 42 of file lpc32xx_slc.c.

#define lpc32xx_nand_resume NULL

Definition at line 1012 of file lpc32xx_slc.c.

#define lpc32xx_nand_suspend NULL

Definition at line 1013 of file lpc32xx_slc.c.

#define LPC32XX_SLC_DEV_ECC_BYTES 3

Definition at line 130 of file lpc32xx_slc.c.

#define SLC_ADDR ( x ) (x + 0x004)

Definition at line 49 of file lpc32xx_slc.c.

#define SLC_CFG ( x ) (x + 0x014)

Definition at line 53 of file lpc32xx_slc.c.

#define SLC_CMD ( x ) (x + 0x008)

Definition at line 50 of file lpc32xx_slc.c.

#define SLC_CTRL ( x ) (x + 0x010)

Definition at line 52 of file lpc32xx_slc.c.

#define SLC_DATA ( x ) (x + 0x000)

Definition at line 48 of file lpc32xx_slc.c.

#define SLC_DMA_DATA ( x ) (x + 0x038)

Definition at line 62 of file lpc32xx_slc.c.

#define SLC_ECC ( x ) (x + 0x034)

Definition at line 61 of file lpc32xx_slc.c.

#define SLC_ICR ( x ) (x + 0x028)

Definition at line 58 of file lpc32xx_slc.c.

#define SLC_IEN ( x ) (x + 0x020)

Definition at line 56 of file lpc32xx_slc.c.

#define SLC_INT_STAT ( x ) (x + 0x01C)

Definition at line 55 of file lpc32xx_slc.c.

#define SLC_ISR ( x ) (x + 0x024)

Definition at line 57 of file lpc32xx_slc.c.

#define SLC_STAT ( x ) (x + 0x018)

Definition at line 54 of file lpc32xx_slc.c.

#define SLC_STOP ( x ) (x + 0x00C)

Definition at line 51 of file lpc32xx_slc.c.

#define SLC_TAC ( x ) (x + 0x02C)

Definition at line 59 of file lpc32xx_slc.c.

#define SLC_TC ( x ) (x + 0x030)

Definition at line 60 of file lpc32xx_slc.c.

#define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */

Definition at line 74 of file lpc32xx_slc.c.

#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */

Definition at line 77 of file lpc32xx_slc.c.

#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */

Definition at line 78 of file lpc32xx_slc.c.

#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */

Definition at line 75 of file lpc32xx_slc.c.

#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */

Definition at line 76 of file lpc32xx_slc.c.

#define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */

Definition at line 79 of file lpc32xx_slc.c.

#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */

Definition at line 69 of file lpc32xx_slc.c.

#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */

Definition at line 68 of file lpc32xx_slc.c.

#define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */

Definition at line 67 of file lpc32xx_slc.c.

#define SLCECC_TO_COLPAR ( n ) ((n) & 0x3F)

Definition at line 119 of file lpc32xx_slc.c.

#define SLCECC_TO_LINEPAR ( n ) (((n) >> 6) & 0x7FFF)

Definition at line 118 of file lpc32xx_slc.c.

#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */

Definition at line 84 of file lpc32xx_slc.c.

#define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */

Definition at line 92 of file lpc32xx_slc.c.

#define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */

Definition at line 91 of file lpc32xx_slc.c.

#define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */

Definition at line 86 of file lpc32xx_slc.c.

#define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */

Definition at line 85 of file lpc32xx_slc.c.

#define SLCTAC_RDR ( n ) (((n) & 0xF) << 12)

Definition at line 106 of file lpc32xx_slc.c.

#define SLCTAC_RHOLD ( n ) (((n) & 0xF) << 4)

Definition at line 110 of file lpc32xx_slc.c.

#define SLCTAC_RSETUP ( n ) (((n) & 0xF) << 0)

Definition at line 112 of file lpc32xx_slc.c.

#define SLCTAC_RWIDTH ( n ) (((n) & 0xF) << 8)

Definition at line 108 of file lpc32xx_slc.c.

#define SLCTAC_WDR ( n ) (((n) & 0xF) << 28)

Definition at line 98 of file lpc32xx_slc.c.

#define SLCTAC_WHOLD ( n ) (((n) & 0xF) << 20)

Definition at line 102 of file lpc32xx_slc.c.

#define SLCTAC_WSETUP ( n ) (((n) & 0xF) << 16)

Definition at line 104 of file lpc32xx_slc.c.

#define SLCTAC_WWIDTH ( n ) (((n) & 0xF) << 24)

Definition at line 100 of file lpc32xx_slc.c.

Function Documentation

MODULE_AUTHOR ( "Kevin Wells <[email protected]>" )

MODULE_AUTHOR ( "Roland Stigge <[email protected]>" )

MODULE_DESCRIPTION ( "NAND driver for the NXP LPC32XX SLC controller" )

MODULE_DEVICE_TABLE	(	of	,
		lpc32xx_nand_match
	)

MODULE_LICENSE ( "GPL" )

module_platform_driver ( lpc32xx_nand_driver )

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation