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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <asm/m52xxacr.h>Go to the source code of this file.
Macros | |
| #define | CPU_NAME "COLDFIRE(m527x)" |
| #define | CPU_INSTR_PER_JIFFY 3 |
| #define | MCF_BUSCLK (MCF_CLK / 2) |
| #define | MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
| #define | MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ |
| #define | MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| #define | MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| #define | MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| #define | MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| #define | MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| #define | MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| #define | MCFINTC_IRLR 0x18 /* */ |
| #define | MCFINTC_IACKL 0x19 /* */ |
| #define | MCFINTC_ICR0 0x40 /* Base ICR register */ |
| #define | MCFINT_VECBASE 64 /* Vector base number */ |
| #define | MCFINT_UART0 13 /* Interrupt number for UART0 */ |
| #define | MCFINT_UART1 14 /* Interrupt number for UART1 */ |
| #define | MCFINT_UART2 15 /* Interrupt number for UART2 */ |
| #define | MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
| #define | MCFINT_FECRX0 23 /* Interrupt number for FEC0 */ |
| #define | MCFINT_FECTX0 27 /* Interrupt number for FEC0 */ |
| #define | MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */ |
| #define | MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
| #define | MCFINT2_VECBASE 128 /* Vector base number 2 */ |
| #define | MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */ |
| #define | MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */ |
| #define | MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */ |
| #define | MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
| #define | MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) |
| #define | MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) |
| #define | MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
| #define | MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) |
| #define | MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
| #define | MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1) |
| #define | MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) |
| #define | MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) |
| #define | MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| #define | MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
| #define | MCFDMA_BASE0 (MCF_IPSBAR + 0x100) |
| #define | MCFDMA_BASE1 (MCF_IPSBAR + 0x140) |
| #define | MCFDMA_BASE2 (MCF_IPSBAR + 0x180) |
| #define | MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) |
| #define | MCFUART_BASE0 (MCF_IPSBAR + 0x200) |
| #define | MCFUART_BASE1 (MCF_IPSBAR + 0x240) |
| #define | MCFUART_BASE2 (MCF_IPSBAR + 0x280) |
| #define | MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) |
| #define | MCFFEC_SIZE0 0x800 |
| #define | MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) |
| #define | MCFFEC_SIZE1 0x800 |
| #define | MCFQSPI_BASE (MCF_IPSBAR + 0x340) |
| #define | MCFQSPI_SIZE 0x40 |
| #define | MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) |
| #define | MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) |
| #define | MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) |
| #define | MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) |
| #define | MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) |
| #define | MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
| #define | MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) |
| #define | MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
| #define | MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) |
| #define | MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) |
| #define | MCF_RCR (MCF_IPSBAR + 0x110000) |
| #define | MCF_RSR (MCF_IPSBAR + 0x110001) |
| #define | MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
| #define | MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
| #define CPU_INSTR_PER_JIFFY 3 |
Definition at line 15 of file m527xsim.h.
| #define CPU_NAME "COLDFIRE(m527x)" |
Definition at line 14 of file m527xsim.h.
| #define MCF_BUSCLK (MCF_CLK / 2) |
Definition at line 16 of file m527xsim.h.
| #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
Definition at line 57 of file m527xsim.h.
| #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) |
Definition at line 60 of file m527xsim.h.
| #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
Definition at line 55 of file m527xsim.h.
| #define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1) |
Definition at line 58 of file m527xsim.h.
| #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) |
Definition at line 56 of file m527xsim.h.
| #define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) |
Definition at line 59 of file m527xsim.h.
| #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
Definition at line 63 of file m527xsim.h.
| #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
Definition at line 62 of file m527xsim.h.
| #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
Definition at line 51 of file m527xsim.h.
| #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) |
Definition at line 52 of file m527xsim.h.
| #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) |
Definition at line 53 of file m527xsim.h.
| #define MCF_RCR (MCF_IPSBAR + 0x110000) |
Definition at line 348 of file m527xsim.h.
| #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
Definition at line 352 of file m527xsim.h.
| #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
Definition at line 351 of file m527xsim.h.
| #define MCF_RSR (MCF_IPSBAR + 0x110001) |
Definition at line 349 of file m527xsim.h.
| #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) |
Definition at line 89 of file m527xsim.h.
| #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) |
Definition at line 90 of file m527xsim.h.
| #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) |
Definition at line 91 of file m527xsim.h.
| #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) |
Definition at line 92 of file m527xsim.h.
| #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
Definition at line 339 of file m527xsim.h.
| #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
Definition at line 341 of file m527xsim.h.
| #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) |
Definition at line 343 of file m527xsim.h.
| #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) |
Definition at line 340 of file m527xsim.h.
| #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) |
Definition at line 338 of file m527xsim.h.
| #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) |
Definition at line 342 of file m527xsim.h.
| #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) |
Definition at line 104 of file m527xsim.h.
| #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) |
Definition at line 106 of file m527xsim.h.
| #define MCFFEC_SIZE0 0x800 |
Definition at line 105 of file m527xsim.h.
| #define MCFFEC_SIZE1 0x800 |
Definition at line 107 of file m527xsim.h.
| #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
Definition at line 23 of file m527xsim.h.
| #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ |
Definition at line 24 of file m527xsim.h.
Definition at line 49 of file m527xsim.h.
Definition at line 47 of file m527xsim.h.
Definition at line 48 of file m527xsim.h.
Definition at line 46 of file m527xsim.h.
Definition at line 43 of file m527xsim.h.
Definition at line 41 of file m527xsim.h.
Definition at line 42 of file m527xsim.h.
Definition at line 44 of file m527xsim.h.
Definition at line 40 of file m527xsim.h.
Definition at line 37 of file m527xsim.h.
Definition at line 38 of file m527xsim.h.
Definition at line 39 of file m527xsim.h.
Definition at line 36 of file m527xsim.h.
| #define MCFINTC_IACKL 0x19 /* */ |
Definition at line 33 of file m527xsim.h.
| #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
Definition at line 34 of file m527xsim.h.
| #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
Definition at line 28 of file m527xsim.h.
| #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
Definition at line 29 of file m527xsim.h.
| #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
Definition at line 30 of file m527xsim.h.
| #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
Definition at line 31 of file m527xsim.h.
| #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
Definition at line 26 of file m527xsim.h.
| #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
Definition at line 27 of file m527xsim.h.
| #define MCFINTC_IRLR 0x18 /* */ |
Definition at line 32 of file m527xsim.h.
| #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) |
Definition at line 330 of file m527xsim.h.
| #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) |
Definition at line 331 of file m527xsim.h.
| #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) |
Definition at line 332 of file m527xsim.h.
| #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) |
Definition at line 333 of file m527xsim.h.
| #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) |
Definition at line 112 of file m527xsim.h.
| #define MCFQSPI_SIZE 0x40 |
Definition at line 113 of file m527xsim.h.
| #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) |
Definition at line 97 of file m527xsim.h.
| #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) |
Definition at line 98 of file m527xsim.h.
| #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) |
Definition at line 99 of file m527xsim.h.
1.8.2