37 #include <linux/module.h>
42 #include <linux/slab.h>
51 #include <linux/sched.h>
67 #define SND_ML403_AC97CR_DRIVER "ml403-ac97cr"
90 #ifdef CONFIG_SND_DEBUG
94 #define SND_PCM_INDIRECT2_STAT
105 #ifdef CONFIG_SND_DEBUG
107 #define UNKNOWN (1<<0)
108 #define CODEC_SUCCESS (1<<1)
109 #define CODEC_FAKE (1<<2)
110 #define INIT_INFO (1<<3)
111 #define INIT_FAILURE (1<<4)
112 #define WORK_INFO (1<<5)
113 #define WORK_FAILURE (1<<6)
115 #define PDEBUG_FACILITIES (UNKNOWN | INIT_FAILURE | WORK_FAILURE)
117 #define PDEBUG(fac, fmt, args...) do { \
118 if (fac & PDEBUG_FACILITIES) \
119 snd_printd(KERN_DEBUG SND_ML403_AC97CR_DRIVER ": " \
123 #define PDEBUG(fac, fmt, args...)
129 #define CODEC_TIMEOUT_ON_INIT 5
132 #ifndef CODEC_WRITE_CHECK_RAF
133 #define CODEC_WAIT_AFTER_WRITE 100
138 #define CODEC_TIMEOUT_AFTER_WRITE 5
142 #define CODEC_TIMEOUT_AFTER_READ 5
147 #define LM4550_REG_OK (1<<0)
148 #define LM4550_REG_DONEREAD (1<<1)
151 #define LM4550_REG_NOSAVE (1<<2)
154 #define LM4550_REG_NOSHADOW (1<<3)
157 #define LM4550_REG_READONLY (1<<4)
158 #define LM4550_REG_FAKEPROBE (1<<5)
161 #define LM4550_REG_FAKEREAD (1<<6)
164 #define LM4550_REG_ALLFAKE (LM4550_REG_FAKEREAD | LM4550_REG_FAKEPROBE)
272 #define LM4550_RF_OK(reg) (lm4550_regfile[reg / 2].flag & LM4550_REG_OK)
274 static void lm4550_regfile_init(
void)
277 for (i = 0; i < 64; i++)
279 lm4550_regfile[
i].
value = lm4550_regfile[
i].
def;
282 static void lm4550_regfile_write_values_after_init(
struct snd_ac97 *ac97)
285 for (i = 0; i < 64; i++)
287 (lm4550_regfile[i].
value != lm4550_regfile[i].
def)) {
288 PDEBUG(CODEC_FAKE,
"lm4550_regfile_write_values_after_"
289 "init(): reg=0x%x value=0x%x / %d is different "
290 "from def=0x%x / %d\n",
291 i, lm4550_regfile[i].
value,
292 lm4550_regfile[i].value, lm4550_regfile[i].def,
293 lm4550_regfile[i].def);
301 #define CR_REG(ml403_ac97cr, x) ((ml403_ac97cr)->port + CR_REG_##x)
303 #define CR_REG_PLAYFIFO 0x00
304 #define CR_PLAYDATA(a) ((a) & 0xFFFF)
306 #define CR_REG_RECFIFO 0x04
307 #define CR_RECDATA(a) ((a) & 0xFFFF)
309 #define CR_REG_STATUS 0x08
310 #define CR_RECOVER (1<<7)
311 #define CR_PLAYUNDER (1<<6)
312 #define CR_CODECREADY (1<<5)
313 #define CR_RAF (1<<4)
314 #define CR_RECEMPTY (1<<3)
315 #define CR_RECFULL (1<<2)
316 #define CR_PLAYHALF (1<<1)
317 #define CR_PLAYFULL (1<<0)
319 #define CR_REG_RESETFIFO 0x0C
320 #define CR_RECRESET (1<<1)
321 #define CR_PLAYRESET (1<<0)
323 #define CR_REG_CODEC_ADDR 0x10
330 #define CR_CODEC_ADDR(a) ((a) << 0)
331 #define CR_CODEC_READ (1<<7)
332 #define CR_CODEC_WRITE (0<<7)
334 #define CR_REG_CODEC_DATAREAD 0x14
335 #define CR_CODEC_DATAREAD(v) ((v) & 0xFFFF)
337 #define CR_REG_CODEC_DATAWRITE 0x18
338 #define CR_CODEC_DATAWRITE(v) ((v) & 0xFFFF)
340 #define CR_FIFO_SIZE 32
387 .buffer_bytes_max = (128*1024),
406 .buffer_bytes_max = (128*1024),
419 int copied_words = 0;
431 spin_unlock(&ml403_ac97cr->
reg_lock);
433 return (
size_t) (copied_words * 2);
443 int copied_words = 0;
451 CR_PLAYFULL)) != CR_PLAYFULL) && (bytes > 1)) {
457 if (full != CR_PLAYFULL)
461 spin_unlock(&ml403_ac97cr->
reg_lock);
463 return (
size_t) (copied_words * 2);
471 int copied_words = 0;
489 spin_unlock(&ml403_ac97cr->
reg_lock);
491 return (
size_t) (copied_words * 2);
500 int copied_words = 0;
508 CR_RECEMPTY)) != CR_RECEMPTY) && (bytes > 1)) {
514 if (empty != CR_RECEMPTY)
518 spin_unlock(&ml403_ac97cr->
reg_lock);
520 return (
size_t) (copied_words * 2);
532 ind2_rec = &ml403_ac97cr->
ind_rec;
536 if (ind2_rec !=
NULL)
552 PDEBUG(WORK_INFO,
"trigger(playback): START\n");
553 ml403_ac97cr->
ind_rec.hw_ready = 1;
563 PDEBUG(WORK_INFO,
"trigger(playback): STOP\n");
564 ml403_ac97cr->
ind_rec.hw_ready = 0;
565 #ifdef SND_PCM_INDIRECT2_STAT
566 snd_pcm_indirect2_stat(substream, &ml403_ac97cr->
ind_rec);
576 PDEBUG(WORK_INFO,
"trigger(playback): (done)\n");
591 PDEBUG(WORK_INFO,
"trigger(capture): START\n");
602 PDEBUG(WORK_INFO,
"trigger(capture): STOP\n");
604 #ifdef SND_PCM_INDIRECT2_STAT
605 snd_pcm_indirect2_stat(substream,
616 PDEBUG(WORK_INFO,
"trigger(capture): (done)\n");
630 "prepare(): period_bytes=%d, minperiod_bytes=%d\n",
636 PDEBUG(WORK_INFO,
"prepare(): rate=%d\n", runtime->
rate);
642 ml403_ac97cr->
ind_rec.sw_buffer_size =
643 snd_pcm_lib_buffer_bytes(substream);
644 ml403_ac97cr->
ind_rec.min_periods = -1;
645 ml403_ac97cr->
ind_rec.min_multiple =
646 snd_pcm_lib_period_bytes(substream) / (
CR_FIFO_SIZE / 2);
647 PDEBUG(WORK_INFO,
"prepare(): hw_buffer_size=%d, "
648 "sw_buffer_size=%d, min_multiple=%d\n",
650 ml403_ac97cr->
ind_rec.min_multiple);
664 "prepare(capture): period_bytes=%d, minperiod_bytes=%d\n",
670 PDEBUG(WORK_INFO,
"prepare(capture): rate=%d\n", runtime->
rate);
677 snd_pcm_lib_buffer_bytes(substream);
679 snd_pcm_lib_period_bytes(substream) / (
CR_FIFO_SIZE / 2);
680 PDEBUG(WORK_INFO,
"prepare(capture): hw_buffer_size=%d, "
689 PDEBUG(WORK_INFO,
"hw_free()\n");
697 PDEBUG(WORK_INFO,
"hw_params(): desired buffer bytes=%d, desired "
712 PDEBUG(WORK_INFO,
"open(playback)\n");
714 runtime->
hw = snd_ml403_ac97cr_playback;
730 PDEBUG(WORK_INFO,
"open(capture)\n");
732 runtime->
hw = snd_ml403_ac97cr_capture;
746 PDEBUG(WORK_INFO,
"close(playback)\n");
757 PDEBUG(WORK_INFO,
"close(capture)\n");
762 static struct snd_pcm_ops snd_ml403_ac97cr_playback_ops = {
763 .open = snd_ml403_ac97cr_playback_open,
764 .close = snd_ml403_ac97cr_playback_close,
766 .hw_params = snd_ml403_ac97cr_hw_params,
767 .hw_free = snd_ml403_ac97cr_hw_free,
768 .prepare = snd_ml403_ac97cr_pcm_playback_prepare,
769 .trigger = snd_ml403_ac97cr_pcm_playback_trigger,
770 .pointer = snd_ml403_ac97cr_pcm_pointer,
773 static struct snd_pcm_ops snd_ml403_ac97cr_capture_ops = {
774 .open = snd_ml403_ac97cr_capture_open,
775 .close = snd_ml403_ac97cr_capture_close,
777 .hw_params = snd_ml403_ac97cr_hw_params,
778 .hw_free = snd_ml403_ac97cr_hw_free,
779 .prepare = snd_ml403_ac97cr_pcm_capture_prepare,
780 .trigger = snd_ml403_ac97cr_pcm_capture_trigger,
781 .pointer = snd_ml403_ac97cr_pcm_pointer,
791 if (ml403_ac97cr ==
NULL)
794 pfdev = ml403_ac97cr->
pfdev;
798 if (irq == cmp_irq) {
803 snd_ml403_ac97cr_playback_ind2_copy,
804 snd_ml403_ac97cr_playback_ind2_zero);
810 if (irq == cmp_irq) {
815 snd_ml403_ac97cr_capture_ind2_copy,
816 snd_ml403_ac97cr_capture_ind2_null);
825 PDEBUG(INIT_INFO,
"irq(): irq %d is meant to be disabled! So, now try "
826 "to disable it _really_!\n", irq);
831 static unsigned short
832 snd_ml403_ac97cr_codec_read(
struct snd_ac97 *ac97,
unsigned short reg)
839 unsigned long end_time;
844 "access to unknown/unused codec register 0x%x "
849 if ((lm4550_regfile[reg / 2].
flag &
853 PDEBUG(CODEC_FAKE,
"codec_read(): faking read from "
854 "reg=0x%x, val=0x%x / %d\n",
855 reg, lm4550_regfile[reg / 2].def,
856 lm4550_regfile[reg / 2].def);
857 return lm4550_regfile[reg / 2].
def;
858 }
else if ((lm4550_regfile[reg / 2].
flag &
861 PDEBUG(CODEC_FAKE,
"codec_read(): faking read from "
862 "reg=0x%x, val=0x%x / %d (probe)\n",
863 reg, lm4550_regfile[reg / 2].value,
864 lm4550_regfile[reg / 2].value);
865 return lm4550_regfile[reg / 2].
value;
868 PDEBUG(CODEC_FAKE,
"codec_read(): read access "
869 "answered by shadow register 0x%x (value=0x%x "
870 "/ %d) (cw=%d cr=%d)\n",
871 reg, lm4550_regfile[reg / 2].value,
872 lm4550_regfile[reg / 2].value,
873 ml403_ac97cr->ac97_write,
874 ml403_ac97cr->ac97_read);
876 PDEBUG(CODEC_FAKE,
"codec_read(): read access "
877 "answered by shadow register 0x%x (value=0x%x "
879 reg, lm4550_regfile[reg / 2].value,
880 lm4550_regfile[reg / 2].value);
882 return lm4550_regfile[reg / 2].
value;
889 ml403_ac97cr->ac97_read++;
894 spin_unlock(&ml403_ac97cr->
reg_lock);
901 if ((stat &
CR_RAF) == CR_RAF) {
904 PDEBUG(CODEC_SUCCESS,
"codec_read(): (done) reg=0x%x, "
905 "value=0x%x / %d (STATUS=0x%x)\n",
906 reg, value, value, stat);
912 PDEBUG(CODEC_SUCCESS,
"codec_read(): (done) "
913 "reg=0x%x, value=0x%x / %d\n",
918 spin_unlock(&ml403_ac97cr->
reg_lock);
922 spin_unlock(&ml403_ac97cr->
reg_lock);
929 spin_unlock(&ml403_ac97cr->
reg_lock);
932 "timeout while codec read! "
933 "(reg=0x%x, last STATUS=0x%x, DATAREAD=0x%x / %d, %d) "
935 reg, stat, value, value, rafaccess,
936 ml403_ac97cr->ac97_write, ml403_ac97cr->ac97_read);
939 "timeout while codec read! "
940 "(reg=0x%x, DATAREAD=0x%x / %d)\n",
953 snd_ml403_ac97cr_codec_write(
struct snd_ac97 *ac97,
unsigned short reg,
962 #ifdef CODEC_WRITE_CHECK_RAF
963 unsigned long end_time;
968 "access to unknown/unused codec register 0x%x "
974 "write access to read only codec register 0x%x "
978 if ((val & lm4550_regfile[reg / 2].
wmask) != val) {
980 "write access to codec register 0x%x "
981 "with bad value 0x%x / %d!\n",
983 val = val & lm4550_regfile[reg / 2].
wmask;
987 !(lm4550_regfile[reg / 2].
flag & LM4550_REG_NOSHADOW)) {
988 PDEBUG(CODEC_FAKE,
"codec_write(): faking write to reg=0x%x, "
989 "val=0x%x / %d\n", reg, val, val);
990 lm4550_regfile[reg / 2].
value = (val &
991 lm4550_regfile[reg / 2].
wmask);
997 ml403_ac97cr->ac97_write++;
1004 spin_unlock(&ml403_ac97cr->
reg_lock);
1005 #ifdef CODEC_WRITE_CHECK_RAF
1009 end_time =
jiffies +
HZ / CODEC_TIMEOUT_AFTER_WRITE;
1011 spin_lock(&ml403_ac97cr->
reg_lock);
1015 if ((stat & CR_RAF) == CR_RAF) {
1018 CR_RAF) == CR_RAF) {
1020 PDEBUG(CODEC_SUCCESS,
"codec_write(): (done) "
1021 "reg=0x%x, value=%d / 0x%x\n",
1023 if (!(lm4550_regfile[reg / 2].
flag &
1024 LM4550_REG_NOSHADOW) &&
1025 !(lm4550_regfile[reg / 2].
flag &
1027 lm4550_regfile[reg / 2].
value =
val;
1029 spin_unlock(&ml403_ac97cr->
reg_lock);
1033 spin_unlock(&ml403_ac97cr->
reg_lock);
1038 "timeout while codec write "
1039 "(reg=0x%x, val=0x%x / %d, last STATUS=0x%x, %d) "
1041 reg, val, val, stat, rafaccess, ml403_ac97cr->ac97_write,
1042 ml403_ac97cr->ac97_read);
1045 "timeout while codec write (reg=0x%x, val=0x%x / %d)\n",
1049 #if CODEC_WAIT_AFTER_WRITE > 0
1058 PDEBUG(CODEC_SUCCESS,
"codec_write(): (done) "
1059 "reg=0x%x, value=%d / 0x%x (no RAF check)\n",
1069 unsigned long end_time;
1070 PDEBUG(INIT_INFO,
"chip_init():\n");
1077 PDEBUG(INIT_INFO,
"chip_init(): (done)\n");
1083 "timeout while waiting for codec, "
1090 PDEBUG(INIT_INFO,
"free():\n");
1092 if (ml403_ac97cr->
irq >= 0)
1099 kfree(ml403_ac97cr);
1100 PDEBUG(INIT_INFO,
"free(): (done)\n");
1104 static int snd_ml403_ac97cr_dev_free(
struct snd_device *snddev)
1107 PDEBUG(INIT_INFO,
"dev_free():\n");
1108 return snd_ml403_ac97cr_free(ml403_ac97cr);
1118 .dev_free = snd_ml403_ac97cr_dev_free,
1123 *rml403_ac97cr =
NULL;
1124 ml403_ac97cr = kzalloc(
sizeof(*ml403_ac97cr),
GFP_KERNEL);
1125 if (ml403_ac97cr ==
NULL)
1130 ml403_ac97cr->
pfdev = pfdev;
1131 ml403_ac97cr->
irq = -1;
1138 PDEBUG(INIT_INFO,
"Trying to reserve resources now ...\n");
1143 (resource->
start) + 1);
1146 "unable to remap memory region (%pR)\n",
1148 snd_ml403_ac97cr_free(ml403_ac97cr);
1152 "remap controller memory region to "
1153 "0x%x done\n", (
unsigned int)ml403_ac97cr->
port);
1157 dev_name(&pfdev->
dev), (
void *)ml403_ac97cr)) {
1159 "unable to grab IRQ %d\n",
1161 snd_ml403_ac97cr_free(ml403_ac97cr);
1164 ml403_ac97cr->
irq = irq;
1166 "request (playback) irq %d done\n",
1170 dev_name(&pfdev->
dev), (
void *)ml403_ac97cr)) {
1172 "unable to grab IRQ %d\n",
1174 snd_ml403_ac97cr_free(ml403_ac97cr);
1179 "request (capture) irq %d done\n",
1182 err = snd_ml403_ac97cr_chip_init(ml403_ac97cr);
1184 snd_ml403_ac97cr_free(ml403_ac97cr);
1190 PDEBUG(INIT_FAILURE,
"probe(): snd_device_new() failed!\n");
1191 snd_ml403_ac97cr_free(ml403_ac97cr);
1195 *rml403_ac97cr = ml403_ac97cr;
1199 static void snd_ml403_ac97cr_mixer_free(
struct snd_ac97 *ac97)
1202 PDEBUG(INIT_INFO,
"mixer_free():\n");
1204 PDEBUG(INIT_INFO,
"mixer_free(): (done)\n");
1214 .write = snd_ml403_ac97cr_codec_write,
1215 .read = snd_ml403_ac97cr_codec_read,
1217 PDEBUG(INIT_INFO,
"mixer():\n");
1222 memset(&ac97, 0,
sizeof(ac97));
1224 lm4550_regfile_init();
1226 ml403_ac97cr->ac97_read = 0;
1227 ml403_ac97cr->ac97_write = 0;
1235 lm4550_regfile_write_values_after_init(ml403_ac97cr->
ac97);
1236 PDEBUG(INIT_INFO,
"mixer(): (done) snd_ac97_mixer()=%d\n", err);
1254 &snd_ml403_ac97cr_playback_ops);
1256 &snd_ml403_ac97cr_capture_ops);
1260 ml403_ac97cr->
pcm = pcm;
1276 int dev = pfdev->
id;
1286 err = snd_ml403_ac97cr_create(card, pfdev, &ml403_ac97cr);
1288 PDEBUG(INIT_FAILURE,
"probe(): create failed!\n");
1292 PDEBUG(INIT_INFO,
"probe(): create done\n");
1294 err = snd_ml403_ac97cr_mixer(ml403_ac97cr);
1299 PDEBUG(INIT_INFO,
"probe(): mixer done\n");
1300 err = snd_ml403_ac97cr_pcm(ml403_ac97cr, 0,
NULL);
1305 PDEBUG(INIT_INFO,
"probe(): PCM done\n");
1310 (
unsigned long)ml403_ac97cr->
port, ml403_ac97cr->
irq,
1320 platform_set_drvdata(pfdev, card);
1321 PDEBUG(INIT_INFO,
"probe(): (done)\n");
1328 platform_set_drvdata(pfdev,
NULL);
1336 .probe = snd_ml403_ac97cr_probe,
1337 .remove = snd_ml403_ac97cr_remove,