#include <linux/module.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <linux/atomic.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/dma.h>
#include <linux/platform_data/msm_serial_hs.h>

Data Structures
struct	msm_hs_tx

struct	msm_hs_rx

struct	msm_hs_rx_wakeup

struct	msm_hs_port

Macros
#define	UARTDM_MR1_ADDR 0x0

#define	UARTDM_MR2_ADDR 0x4

#define	RSLT_FIFO_CNTR_BMSK (0xE << 28)

#define	RSLT_VLD BIT(1)

#define	UARTDM_CSR_ADDR 0x8

#define	UARTDM_CSR_115200 0xFF

#define	UARTDM_CSR_57600 0xEE

#define	UARTDM_CSR_38400 0xDD

#define	UARTDM_CSR_28800 0xCC

#define	UARTDM_CSR_19200 0xBB

#define	UARTDM_CSR_14400 0xAA

#define	UARTDM_CSR_9600 0x99

#define	UARTDM_CSR_7200 0x88

#define	UARTDM_CSR_4800 0x77

#define	UARTDM_CSR_3600 0x66

#define	UARTDM_CSR_2400 0x55

#define	UARTDM_CSR_1200 0x44

#define	UARTDM_CSR_600 0x33

#define	UARTDM_CSR_300 0x22

#define	UARTDM_CSR_150 0x11

#define	UARTDM_CSR_75 0x00

#define	UARTDM_TF_ADDR 0x70

#define	UARTDM_TF2_ADDR 0x74

#define	UARTDM_TF3_ADDR 0x78

#define	UARTDM_TF4_ADDR 0x7C

#define	UARTDM_CR_ADDR 0x10

#define	UARTDM_IMR_ADDR 0x14

#define	UARTDM_IPR_ADDR 0x18

#define	UARTDM_TFWR_ADDR 0x1c

#define	UARTDM_RFWR_ADDR 0x20

#define	UARTDM_HCR_ADDR 0x24

#define	UARTDM_DMRX_ADDR 0x34

#define	UARTDM_IRDA_ADDR 0x38

#define	UARTDM_DMEN_ADDR 0x3c

#define	UARTDM_NCF_TX_ADDR 0x40

#define	UARTDM_BADR_ADDR 0x44

#define	UARTDM_SIM_CFG_ADDR 0x80

#define	UARTDM_SR_ADDR 0x8

#define	UARTDM_RF_ADDR 0x70

#define	UARTDM_RF2_ADDR 0x74

#define	UARTDM_RF3_ADDR 0x78

#define	UARTDM_RF4_ADDR 0x7C

#define	UARTDM_MISR_ADDR 0x10

#define	UARTDM_ISR_ADDR 0x14

#define	UARTDM_RX_TOTAL_SNAP_ADDR 0x38

#define	UARTDM_RXFS_ADDR 0x50

#define	UARTDM_SR_PAR_FRAME_BMSK BIT(5)

#define	UARTDM_SR_OVERRUN_BMSK BIT(4)

#define	UARTDM_SR_TXEMT_BMSK BIT(3)

#define	UARTDM_SR_TXRDY_BMSK BIT(2)

#define	UARTDM_SR_RXRDY_BMSK BIT(0)

#define	UARTDM_CR_TX_DISABLE_BMSK BIT(3)

#define	UARTDM_CR_RX_DISABLE_BMSK BIT(1)

#define	UARTDM_CR_TX_EN_BMSK BIT(2)

#define	UARTDM_CR_RX_EN_BMSK BIT(0)

#define	RESET_RX 0x10

#define	RESET_TX 0x20

#define	RESET_ERROR_STATUS 0x30

#define	RESET_BREAK_INT 0x40

#define	START_BREAK 0x50

#define	STOP_BREAK 0x60

#define	RESET_CTS 0x70

#define	RESET_STALE_INT 0x80

#define	RFR_LOW 0xD0

#define	RFR_HIGH 0xE0

#define	CR_PROTECTION_EN 0x100

#define	STALE_EVENT_ENABLE 0x500

#define	STALE_EVENT_DISABLE 0x600

#define	FORCE_STALE_EVENT 0x400

#define	CLEAR_TX_READY 0x300

#define	RESET_TX_ERROR 0x800

#define	RESET_TX_DONE 0x810

#define	UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00

#define	UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f

#define	UARTDM_MR1_CTS_CTL_BMSK 0x40

#define	UARTDM_MR1_RX_RDY_CTL_BMSK 0x80

#define	UARTDM_MR2_ERROR_MODE_BMSK 0x40

#define	UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30

#define	FIVE_BPC (0 << 4)

#define	SIX_BPC (1 << 4)

#define	SEVEN_BPC (2 << 4)

#define	EIGHT_BPC (3 << 4)

#define	UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc

#define	STOP_BIT_ONE (1 << 2)

#define	STOP_BIT_TWO (3 << 2)

#define	UARTDM_MR2_PARITY_MODE_BMSK 0x3

#define	NO_PARITY 0x0

#define	EVEN_PARITY 0x1

#define	ODD_PARITY 0x2

#define	SPACE_PARITY 0x3

#define	UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80

#define	UARTDM_IPR_STALE_LSB_BMSK 0x1f

#define	UARTDM_ISR_TX_READY_BMSK BIT(7)

#define	UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)

#define	UARTDM_ISR_DELTA_CTS_BMSK BIT(5)

#define	UARTDM_ISR_RXLEV_BMSK BIT(4)

#define	UARTDM_ISR_RXSTALE_BMSK BIT(3)

#define	UARTDM_ISR_RXBREAK_BMSK BIT(2)

#define	UARTDM_ISR_RXHUNT_BMSK BIT(1)

#define	UARTDM_ISR_TXLEV_BMSK BIT(0)

#define	UARTDM_TX_DM_EN_BMSK 0x1

#define	UARTDM_RX_DM_EN_BMSK 0x2

#define	UART_FIFOSIZE 64

#define	UARTCLK 7372800

#define	MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */

#define	UARTDM_TX_BUF_SIZE UART_XMIT_SIZE

#define	UARTDM_RX_BUF_SIZE 512

#define	UARTDM_NR 2

#define	UARTDM_TO_MSM(uart_port) container_of((uart_port), struct msm_hs_port, uport)

#define	msm_hs_runtime_idle NULL

#define	msm_hs_runtime_resume NULL

#define	msm_hs_runtime_suspend NULL

Enumerations
enum	flush_reason { FLUSH_NONE, FLUSH_DATA_READY, FLUSH_DATA_INVALID, FLUSH_IGNORE = FLUSH_DATA_INVALID, FLUSH_STOP, FLUSH_SHUTDOWN }

enum	msm_hs_clk_states_e { MSM_HS_CLK_PORT_OFF, MSM_HS_CLK_OFF, MSM_HS_CLK_REQUEST_OFF, MSM_HS_CLK_ON }

enum	msm_hs_clk_req_off_state_e { CLK_REQ_OFF_START, CLK_REQ_OFF_RXSTALE_ISSUED, CLK_REQ_OFF_FLUSH_ISSUED, CLK_REQ_OFF_RXSTALE_FLUSHED }

Functions
void	msm_hs_request_clock_off_locked (struct uart_port *uport)

void	msm_hs_request_clock_off (struct uart_port *uport)

void	msm_hs_request_clock_on_locked (struct uart_port *uport)

void	msm_hs_request_clock_on (struct uart_port *uport)

	module_init (msm_serial_hs_init)

	module_exit (msm_serial_hs_exit)

	MODULE_DESCRIPTION ("High Speed UART Driver for the MSM chipset")

	MODULE_VERSION ("1.2")

	MODULE_LICENSE ("GPL v2")

Macro Definition Documentation

#define CLEAR_TX_READY 0x300

Definition at line 154 of file msm_serial_hs.c.

#define CR_PROTECTION_EN 0x100

Definition at line 150 of file msm_serial_hs.c.

#define EIGHT_BPC (3 << 4)

Definition at line 170 of file msm_serial_hs.c.

#define EVEN_PARITY 0x1

Definition at line 180 of file msm_serial_hs.c.

#define FIVE_BPC (0 << 4)

Definition at line 167 of file msm_serial_hs.c.

#define FORCE_STALE_EVENT 0x400

Definition at line 153 of file msm_serial_hs.c.

#define msm_hs_runtime_idle NULL

Definition at line 1828 of file msm_serial_hs.c.

#define msm_hs_runtime_resume NULL

Definition at line 1829 of file msm_serial_hs.c.

#define msm_hs_runtime_suspend NULL

Definition at line 1830 of file msm_serial_hs.c.

#define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */

Definition at line 355 of file msm_serial_hs.c.

#define NO_PARITY 0x0

Definition at line 179 of file msm_serial_hs.c.

#define ODD_PARITY 0x2

Definition at line 181 of file msm_serial_hs.c.

#define RESET_BREAK_INT 0x40

Definition at line 143 of file msm_serial_hs.c.

#define RESET_CTS 0x70

Definition at line 146 of file msm_serial_hs.c.

#define RESET_ERROR_STATUS 0x30

Definition at line 142 of file msm_serial_hs.c.

#define RESET_RX 0x10

Definition at line 140 of file msm_serial_hs.c.

#define RESET_STALE_INT 0x80

Definition at line 147 of file msm_serial_hs.c.

#define RESET_TX 0x20

Definition at line 141 of file msm_serial_hs.c.

#define RESET_TX_DONE 0x810

Definition at line 156 of file msm_serial_hs.c.

#define RESET_TX_ERROR 0x800

Definition at line 155 of file msm_serial_hs.c.

#define RFR_HIGH 0xE0

Definition at line 149 of file msm_serial_hs.c.

#define RFR_LOW 0xD0

Definition at line 148 of file msm_serial_hs.c.

#define RSLT_FIFO_CNTR_BMSK (0xE << 28)

Definition at line 63 of file msm_serial_hs.c.

#define RSLT_VLD BIT(1)

Definition at line 64 of file msm_serial_hs.c.

#define SEVEN_BPC (2 << 4)

Definition at line 169 of file msm_serial_hs.c.

#define SIX_BPC (1 << 4)

Definition at line 168 of file msm_serial_hs.c.

#define SPACE_PARITY 0x3

Definition at line 182 of file msm_serial_hs.c.

#define STALE_EVENT_DISABLE 0x600

Definition at line 152 of file msm_serial_hs.c.

#define STALE_EVENT_ENABLE 0x500

Definition at line 151 of file msm_serial_hs.c.

#define START_BREAK 0x50

Definition at line 144 of file msm_serial_hs.c.

#define STOP_BIT_ONE (1 << 2)

Definition at line 173 of file msm_serial_hs.c.

#define STOP_BIT_TWO (3 << 2)

Definition at line 174 of file msm_serial_hs.c.

#define STOP_BREAK 0x60

Definition at line 145 of file msm_serial_hs.c.

#define UART_FIFOSIZE 64

Definition at line 201 of file msm_serial_hs.c.

#define UARTCLK 7372800

Definition at line 202 of file msm_serial_hs.c.

#define UARTDM_BADR_ADDR 0x44

Definition at line 106 of file msm_serial_hs.c.

#define UARTDM_CR_ADDR 0x10

Definition at line 92 of file msm_serial_hs.c.

#define UARTDM_CR_RX_DISABLE_BMSK BIT(1)

Definition at line 135 of file msm_serial_hs.c.

#define UARTDM_CR_RX_EN_BMSK BIT(0)

Definition at line 137 of file msm_serial_hs.c.

#define UARTDM_CR_TX_DISABLE_BMSK BIT(3)

Definition at line 134 of file msm_serial_hs.c.

#define UARTDM_CR_TX_EN_BMSK BIT(2)

Definition at line 136 of file msm_serial_hs.c.

#define UARTDM_CSR_115200 0xFF

Definition at line 68 of file msm_serial_hs.c.

#define UARTDM_CSR_1200 0x44

Definition at line 79 of file msm_serial_hs.c.

#define UARTDM_CSR_14400 0xAA

Definition at line 73 of file msm_serial_hs.c.

#define UARTDM_CSR_150 0x11

Definition at line 82 of file msm_serial_hs.c.

#define UARTDM_CSR_19200 0xBB

Definition at line 72 of file msm_serial_hs.c.

#define UARTDM_CSR_2400 0x55

Definition at line 78 of file msm_serial_hs.c.

#define UARTDM_CSR_28800 0xCC

Definition at line 71 of file msm_serial_hs.c.

#define UARTDM_CSR_300 0x22

Definition at line 81 of file msm_serial_hs.c.

#define UARTDM_CSR_3600 0x66

Definition at line 77 of file msm_serial_hs.c.

#define UARTDM_CSR_38400 0xDD

Definition at line 70 of file msm_serial_hs.c.

#define UARTDM_CSR_4800 0x77

Definition at line 76 of file msm_serial_hs.c.

#define UARTDM_CSR_57600 0xEE

Definition at line 69 of file msm_serial_hs.c.

#define UARTDM_CSR_600 0x33

Definition at line 80 of file msm_serial_hs.c.

#define UARTDM_CSR_7200 0x88

Definition at line 75 of file msm_serial_hs.c.

#define UARTDM_CSR_75 0x00

Definition at line 83 of file msm_serial_hs.c.

#define UARTDM_CSR_9600 0x99

Definition at line 74 of file msm_serial_hs.c.

#define UARTDM_CSR_ADDR 0x8

Definition at line 67 of file msm_serial_hs.c.

#define UARTDM_DMEN_ADDR 0x3c

Definition at line 101 of file msm_serial_hs.c.

#define UARTDM_DMRX_ADDR 0x34

Definition at line 99 of file msm_serial_hs.c.

#define UARTDM_HCR_ADDR 0x24

Definition at line 98 of file msm_serial_hs.c.

#define UARTDM_IMR_ADDR 0x14

Definition at line 93 of file msm_serial_hs.c.

#define UARTDM_IPR_ADDR 0x18

Definition at line 95 of file msm_serial_hs.c.

#define UARTDM_IPR_STALE_LSB_BMSK 0x1f

Definition at line 185 of file msm_serial_hs.c.

#define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80

Definition at line 184 of file msm_serial_hs.c.

#define UARTDM_IRDA_ADDR 0x38

Definition at line 100 of file msm_serial_hs.c.

#define UARTDM_ISR_ADDR 0x14

Definition at line 122 of file msm_serial_hs.c.

#define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)

Definition at line 189 of file msm_serial_hs.c.

#define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)

Definition at line 190 of file msm_serial_hs.c.

#define UARTDM_ISR_RXBREAK_BMSK BIT(2)

Definition at line 193 of file msm_serial_hs.c.

#define UARTDM_ISR_RXHUNT_BMSK BIT(1)

Definition at line 194 of file msm_serial_hs.c.

#define UARTDM_ISR_RXLEV_BMSK BIT(4)

Definition at line 191 of file msm_serial_hs.c.

#define UARTDM_ISR_RXSTALE_BMSK BIT(3)

Definition at line 192 of file msm_serial_hs.c.

#define UARTDM_ISR_TX_READY_BMSK BIT(7)

Definition at line 188 of file msm_serial_hs.c.

#define UARTDM_ISR_TXLEV_BMSK BIT(0)

Definition at line 195 of file msm_serial_hs.c.

#define UARTDM_MISR_ADDR 0x10

Definition at line 119 of file msm_serial_hs.c.

#define UARTDM_MR1_ADDR 0x0

Definition at line 59 of file msm_serial_hs.c.

#define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f

Definition at line 159 of file msm_serial_hs.c.

#define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00

Definition at line 158 of file msm_serial_hs.c.

#define UARTDM_MR1_CTS_CTL_BMSK 0x40

Definition at line 160 of file msm_serial_hs.c.

#define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80

Definition at line 161 of file msm_serial_hs.c.

#define UARTDM_MR2_ADDR 0x4

Definition at line 60 of file msm_serial_hs.c.

#define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30

Definition at line 164 of file msm_serial_hs.c.

#define UARTDM_MR2_ERROR_MODE_BMSK 0x40

Definition at line 163 of file msm_serial_hs.c.

#define UARTDM_MR2_PARITY_MODE_BMSK 0x3

Definition at line 176 of file msm_serial_hs.c.

#define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc

Definition at line 172 of file msm_serial_hs.c.

#define UARTDM_NCF_TX_ADDR 0x40

Definition at line 104 of file msm_serial_hs.c.

#define UARTDM_NR 2

Definition at line 359 of file msm_serial_hs.c.

#define UARTDM_RF2_ADDR 0x74

Definition at line 114 of file msm_serial_hs.c.

#define UARTDM_RF3_ADDR 0x78

Definition at line 115 of file msm_serial_hs.c.

#define UARTDM_RF4_ADDR 0x7C

Definition at line 116 of file msm_serial_hs.c.

#define UARTDM_RF_ADDR 0x70

Definition at line 113 of file msm_serial_hs.c.

#define UARTDM_RFWR_ADDR 0x20

Definition at line 97 of file msm_serial_hs.c.

#define UARTDM_RX_BUF_SIZE 512

Definition at line 357 of file msm_serial_hs.c.

#define UARTDM_RX_DM_EN_BMSK 0x2

Definition at line 199 of file msm_serial_hs.c.

#define UARTDM_RX_TOTAL_SNAP_ADDR 0x38

Definition at line 123 of file msm_serial_hs.c.

#define UARTDM_RXFS_ADDR 0x50

Definition at line 125 of file msm_serial_hs.c.

#define UARTDM_SIM_CFG_ADDR 0x80

Definition at line 108 of file msm_serial_hs.c.

#define UARTDM_SR_ADDR 0x8

Definition at line 110 of file msm_serial_hs.c.

#define UARTDM_SR_OVERRUN_BMSK BIT(4)

Definition at line 129 of file msm_serial_hs.c.

#define UARTDM_SR_PAR_FRAME_BMSK BIT(5)

Definition at line 128 of file msm_serial_hs.c.

#define UARTDM_SR_RXRDY_BMSK BIT(0)

Definition at line 132 of file msm_serial_hs.c.

#define UARTDM_SR_TXEMT_BMSK BIT(3)

Definition at line 130 of file msm_serial_hs.c.

#define UARTDM_SR_TXRDY_BMSK BIT(2)

Definition at line 131 of file msm_serial_hs.c.

#define UARTDM_TF2_ADDR 0x74

Definition at line 87 of file msm_serial_hs.c.

#define UARTDM_TF3_ADDR 0x78

Definition at line 88 of file msm_serial_hs.c.

#define UARTDM_TF4_ADDR 0x7C

Definition at line 89 of file msm_serial_hs.c.

#define UARTDM_TF_ADDR 0x70

Definition at line 86 of file msm_serial_hs.c.

#define UARTDM_TFWR_ADDR 0x1c

Definition at line 96 of file msm_serial_hs.c.

#define UARTDM_TO_MSM ( uart_port ) container_of((uart_port), struct msm_hs_port, uport)

Definition at line 367 of file msm_serial_hs.c.

#define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE

Definition at line 356 of file msm_serial_hs.c.

#define UARTDM_TX_DM_EN_BMSK 0x1

Definition at line 198 of file msm_serial_hs.c.

Enumeration Type Documentation

enum flush_reason

Enumerator:

FLUSH_NONE
FLUSH_DATA_READY
FLUSH_DATA_INVALID
FLUSH_IGNORE
FLUSH_STOP
FLUSH_SHUTDOWN

Definition at line 205 of file msm_serial_hs.c.

enum msm_hs_clk_req_off_state_e

Enumerator:

CLK_REQ_OFF_START
CLK_REQ_OFF_RXSTALE_ISSUED
CLK_REQ_OFF_FLUSH_ISSUED
CLK_REQ_OFF_RXSTALE_FLUSHED

Definition at line 224 of file msm_serial_hs.c.

enum msm_hs_clk_states_e

Enumerator:

MSM_HS_CLK_PORT_OFF
MSM_HS_CLK_OFF
MSM_HS_CLK_REQUEST_OFF
MSM_HS_CLK_ON

Definition at line 215 of file msm_serial_hs.c.

Function Documentation

MODULE_DESCRIPTION ( "High Speed UART Driver for the MSM chipset" )

module_exit ( msm_serial_hs_exit )

module_init ( msm_serial_hs_init )

MODULE_LICENSE ( "GPL v2" )

MODULE_VERSION ( "1.2" )

void msm_hs_request_clock_off ( struct uart_port * uport )

msm_hs_request_clock_off - request to (i.e. asynchronously) turn off uart clock once pending TX is flushed and Rx DMA command is terminated. : uart_port structure for the device instance.

This functions puts the device into a partially active low power mode. It waits to complete all pending tx transactions, flushes ongoing Rx DMA command and terminates UART side Rx transaction, puts UART HW in non DMA mode and then clocks off the device. A client calls this when no UART data is expected. msm_request_clock_on() must be called before any further UART can be sent or received.

Definition at line 1280 of file msm_serial_hs.c.

void msm_hs_request_clock_off_locked ( struct uart_port * uport )

Definition at line 1254 of file msm_serial_hs.c.

void msm_hs_request_clock_on ( struct uart_port * uport )

msm_hs_request_clock_on - Switch the device from partially active low power mode to fully active (i.e. clock on) mode. : uart_port structure for the device.

This function switches on the input clock, puts UART HW into DMA mode and enqueues an Rx DMA command if the device was in partially active mode. It has no effect if called with the device in inactive state.

Definition at line 1332 of file msm_serial_hs.c.

void msm_hs_request_clock_on_locked ( struct uart_port * uport )

Definition at line 1289 of file msm_serial_hs.c.

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation