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msm_serial_hs.c
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1 /*
2  * MSM 7k/8k High speed uart driver
3  *
4  * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
5  * Copyright (c) 2008 Google Inc.
6  * Modified: Nick Pelly <[email protected]>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15  * See the GNU General Public License for more details.
16  *
17  * Has optional support for uart power management independent of linux
18  * suspend/resume:
19  *
20  * RX wakeup.
21  * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
22  * UART RX pin). This should only be used if there is not a wakeup
23  * GPIO on the UART CTS, and the first RX byte is known (for example, with the
24  * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
25  * always be lost. RTS will be asserted even while the UART is off in this mode
26  * of operation. See msm_serial_hs_platform_data.rx_wakeup_irq.
27  */
28 
29 #include <linux/module.h>
30 
31 #include <linux/serial.h>
32 #include <linux/serial_core.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/slab.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/irq.h>
39 #include <linux/io.h>
40 #include <linux/ioport.h>
41 #include <linux/kernel.h>
42 #include <linux/timer.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/dmapool.h>
48 #include <linux/wait.h>
49 #include <linux/workqueue.h>
50 
51 #include <linux/atomic.h>
52 #include <asm/irq.h>
53 
54 #include <mach/hardware.h>
55 #include <mach/dma.h>
57 
58 /* HSUART Registers */
59 #define UARTDM_MR1_ADDR 0x0
60 #define UARTDM_MR2_ADDR 0x4
61 
62 /* Data Mover result codes */
63 #define RSLT_FIFO_CNTR_BMSK (0xE << 28)
64 #define RSLT_VLD BIT(1)
65 
66 /* write only register */
67 #define UARTDM_CSR_ADDR 0x8
68 #define UARTDM_CSR_115200 0xFF
69 #define UARTDM_CSR_57600 0xEE
70 #define UARTDM_CSR_38400 0xDD
71 #define UARTDM_CSR_28800 0xCC
72 #define UARTDM_CSR_19200 0xBB
73 #define UARTDM_CSR_14400 0xAA
74 #define UARTDM_CSR_9600 0x99
75 #define UARTDM_CSR_7200 0x88
76 #define UARTDM_CSR_4800 0x77
77 #define UARTDM_CSR_3600 0x66
78 #define UARTDM_CSR_2400 0x55
79 #define UARTDM_CSR_1200 0x44
80 #define UARTDM_CSR_600 0x33
81 #define UARTDM_CSR_300 0x22
82 #define UARTDM_CSR_150 0x11
83 #define UARTDM_CSR_75 0x00
84 
85 /* write only register */
86 #define UARTDM_TF_ADDR 0x70
87 #define UARTDM_TF2_ADDR 0x74
88 #define UARTDM_TF3_ADDR 0x78
89 #define UARTDM_TF4_ADDR 0x7C
90 
91 /* write only register */
92 #define UARTDM_CR_ADDR 0x10
93 #define UARTDM_IMR_ADDR 0x14
94 
95 #define UARTDM_IPR_ADDR 0x18
96 #define UARTDM_TFWR_ADDR 0x1c
97 #define UARTDM_RFWR_ADDR 0x20
98 #define UARTDM_HCR_ADDR 0x24
99 #define UARTDM_DMRX_ADDR 0x34
100 #define UARTDM_IRDA_ADDR 0x38
101 #define UARTDM_DMEN_ADDR 0x3c
102 
103 /* UART_DM_NO_CHARS_FOR_TX */
104 #define UARTDM_NCF_TX_ADDR 0x40
105 
106 #define UARTDM_BADR_ADDR 0x44
107 
108 #define UARTDM_SIM_CFG_ADDR 0x80
109 /* Read Only register */
110 #define UARTDM_SR_ADDR 0x8
111 
112 /* Read Only register */
113 #define UARTDM_RF_ADDR 0x70
114 #define UARTDM_RF2_ADDR 0x74
115 #define UARTDM_RF3_ADDR 0x78
116 #define UARTDM_RF4_ADDR 0x7C
117 
118 /* Read Only register */
119 #define UARTDM_MISR_ADDR 0x10
120 
121 /* Read Only register */
122 #define UARTDM_ISR_ADDR 0x14
123 #define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
124 
125 #define UARTDM_RXFS_ADDR 0x50
126 
127 /* Register field Mask Mapping */
128 #define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
129 #define UARTDM_SR_OVERRUN_BMSK BIT(4)
130 #define UARTDM_SR_TXEMT_BMSK BIT(3)
131 #define UARTDM_SR_TXRDY_BMSK BIT(2)
132 #define UARTDM_SR_RXRDY_BMSK BIT(0)
133 
134 #define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
135 #define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
136 #define UARTDM_CR_TX_EN_BMSK BIT(2)
137 #define UARTDM_CR_RX_EN_BMSK BIT(0)
138 
139 /* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
140 #define RESET_RX 0x10
141 #define RESET_TX 0x20
142 #define RESET_ERROR_STATUS 0x30
143 #define RESET_BREAK_INT 0x40
144 #define START_BREAK 0x50
145 #define STOP_BREAK 0x60
146 #define RESET_CTS 0x70
147 #define RESET_STALE_INT 0x80
148 #define RFR_LOW 0xD0
149 #define RFR_HIGH 0xE0
150 #define CR_PROTECTION_EN 0x100
151 #define STALE_EVENT_ENABLE 0x500
152 #define STALE_EVENT_DISABLE 0x600
153 #define FORCE_STALE_EVENT 0x400
154 #define CLEAR_TX_READY 0x300
155 #define RESET_TX_ERROR 0x800
156 #define RESET_TX_DONE 0x810
157 
158 #define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
159 #define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
160 #define UARTDM_MR1_CTS_CTL_BMSK 0x40
161 #define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
162 
163 #define UARTDM_MR2_ERROR_MODE_BMSK 0x40
164 #define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
165 
166 /* bits per character configuration */
167 #define FIVE_BPC (0 << 4)
168 #define SIX_BPC (1 << 4)
169 #define SEVEN_BPC (2 << 4)
170 #define EIGHT_BPC (3 << 4)
171 
172 #define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
173 #define STOP_BIT_ONE (1 << 2)
174 #define STOP_BIT_TWO (3 << 2)
175 
176 #define UARTDM_MR2_PARITY_MODE_BMSK 0x3
177 
178 /* Parity configuration */
179 #define NO_PARITY 0x0
180 #define EVEN_PARITY 0x1
181 #define ODD_PARITY 0x2
182 #define SPACE_PARITY 0x3
183 
184 #define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
185 #define UARTDM_IPR_STALE_LSB_BMSK 0x1f
186 
187 /* These can be used for both ISR and IMR register */
188 #define UARTDM_ISR_TX_READY_BMSK BIT(7)
189 #define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
190 #define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
191 #define UARTDM_ISR_RXLEV_BMSK BIT(4)
192 #define UARTDM_ISR_RXSTALE_BMSK BIT(3)
193 #define UARTDM_ISR_RXBREAK_BMSK BIT(2)
194 #define UARTDM_ISR_RXHUNT_BMSK BIT(1)
195 #define UARTDM_ISR_TXLEV_BMSK BIT(0)
196 
197 /* Field definitions for UART_DM_DMEN*/
198 #define UARTDM_TX_DM_EN_BMSK 0x1
199 #define UARTDM_RX_DM_EN_BMSK 0x2
200 
201 #define UART_FIFOSIZE 64
202 #define UARTCLK 7372800
203 
204 /* Rx DMA request states */
208  FLUSH_DATA_INVALID, /* values after this indicate invalid data */
212 };
213 
214 /* UART clock states */
216  MSM_HS_CLK_PORT_OFF, /* port not in use */
217  MSM_HS_CLK_OFF, /* clock disabled */
218  MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */
219  MSM_HS_CLK_ON, /* clock enabled */
220 };
221 
222 /* Track the forced RXSTALE flush during clock off sequence.
223  * These states are only valid during MSM_HS_CLK_REQUEST_OFF */
229 };
230 
249 struct msm_hs_tx {
250  unsigned int tx_ready_int_en;
251  unsigned int dma_in_flight;
257  int tx_count;
259 };
260 
278 struct msm_hs_rx {
287  unsigned char *buffer;
288  struct dma_pool *pool;
290 };
291 
308  int irq; /* < 0 indicates low power wakeup disabled */
309  unsigned char ignore;
310  unsigned char inject_rx;
312 };
313 
334 struct msm_hs_port {
335  struct uart_port uport;
336  unsigned long imr_reg;
337  struct clk *clk;
338  struct msm_hs_tx tx;
339  struct msm_hs_rx rx;
340 
345 
350 
352  void (*exit_lpm_cb)(struct uart_port *);
353 };
354 
355 #define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */
356 #define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE
357 #define UARTDM_RX_BUF_SIZE 512
358 
359 #define UARTDM_NR 2
360 
361 static struct msm_hs_port q_uart_port[UARTDM_NR];
362 static struct platform_driver msm_serial_hs_platform_driver;
363 static struct uart_driver msm_hs_driver;
364 static struct uart_ops msm_hs_ops;
365 static struct workqueue_struct *msm_hs_workqueue;
366 
367 #define UARTDM_TO_MSM(uart_port) \
368  container_of((uart_port), struct msm_hs_port, uport)
369 
370 static unsigned int use_low_power_rx_wakeup(struct msm_hs_port
371  *msm_uport)
372 {
373  return (msm_uport->rx_wakeup.irq >= 0);
374 }
375 
376 static unsigned int msm_hs_read(struct uart_port *uport,
377  unsigned int offset)
378 {
379  return ioread32(uport->membase + offset);
380 }
381 
382 static void msm_hs_write(struct uart_port *uport, unsigned int offset,
383  unsigned int value)
384 {
385  iowrite32(value, uport->membase + offset);
386 }
387 
388 static void msm_hs_release_port(struct uart_port *port)
389 {
390  iounmap(port->membase);
391 }
392 
393 static int msm_hs_request_port(struct uart_port *port)
394 {
395  port->membase = ioremap(port->mapbase, PAGE_SIZE);
396  if (unlikely(!port->membase))
397  return -ENOMEM;
398 
399  /* configure the CR Protection to Enable */
400  msm_hs_write(port, UARTDM_CR_ADDR, CR_PROTECTION_EN);
401  return 0;
402 }
403 
404 static int __devexit msm_hs_remove(struct platform_device *pdev)
405 {
406 
407  struct msm_hs_port *msm_uport;
408  struct device *dev;
409 
410  if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
411  printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
412  return -EINVAL;
413  }
414 
415  msm_uport = &q_uart_port[pdev->id];
416  dev = msm_uport->uport.dev;
417 
418  dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box),
419  DMA_TO_DEVICE);
420  dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
421  msm_uport->rx.rbuffer);
422  dma_pool_destroy(msm_uport->rx.pool);
423 
424  dma_unmap_single(dev, msm_uport->rx.cmdptr_dmaaddr, sizeof(u32),
425  DMA_TO_DEVICE);
426  dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr_ptr, sizeof(u32),
427  DMA_TO_DEVICE);
428  dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box),
429  DMA_TO_DEVICE);
430 
431  uart_remove_one_port(&msm_hs_driver, &msm_uport->uport);
432  clk_put(msm_uport->clk);
433 
434  /* Free the tx resources */
435  kfree(msm_uport->tx.command_ptr);
436  kfree(msm_uport->tx.command_ptr_ptr);
437 
438  /* Free the rx resources */
439  kfree(msm_uport->rx.command_ptr);
440  kfree(msm_uport->rx.command_ptr_ptr);
441 
442  iounmap(msm_uport->uport.membase);
443 
444  return 0;
445 }
446 
447 static int msm_hs_init_clk_locked(struct uart_port *uport)
448 {
449  int ret;
450  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
451 
452  ret = clk_enable(msm_uport->clk);
453  if (ret) {
454  printk(KERN_ERR "Error could not turn on UART clk\n");
455  return ret;
456  }
457 
458  /* Set up the MREG/NREG/DREG/MNDREG */
459  ret = clk_set_rate(msm_uport->clk, uport->uartclk);
460  if (ret) {
461  printk(KERN_WARNING "Error setting clock rate on UART\n");
462  clk_disable(msm_uport->clk);
463  return ret;
464  }
465 
466  msm_uport->clk_state = MSM_HS_CLK_ON;
467  return 0;
468 }
469 
470 /* Enable and Disable clocks (Used for power management) */
471 static void msm_hs_pm(struct uart_port *uport, unsigned int state,
472  unsigned int oldstate)
473 {
474  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
475 
476  if (use_low_power_rx_wakeup(msm_uport) ||
477  msm_uport->exit_lpm_cb)
478  return; /* ignore linux PM states,
479  use msm_hs_request_clock API */
480 
481  switch (state) {
482  case 0:
483  clk_enable(msm_uport->clk);
484  break;
485  case 3:
486  clk_disable(msm_uport->clk);
487  break;
488  default:
489  dev_err(uport->dev, "msm_serial: Unknown PM state %d\n",
490  state);
491  }
492 }
493 
494 /*
495  * programs the UARTDM_CSR register with correct bit rates
496  *
497  * Interrupts should be disabled before we are called, as
498  * we modify Set Baud rate
499  * Set receive stale interrupt level, dependent on Bit Rate
500  * Goal is to have around 8 ms before indicate stale.
501  * roundup (((Bit Rate * .008) / 10) + 1
502  */
503 static void msm_hs_set_bps_locked(struct uart_port *uport,
504  unsigned int bps)
505 {
506  unsigned long rxstale;
507  unsigned long data;
508  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
509 
510  switch (bps) {
511  case 300:
512  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_75);
513  rxstale = 1;
514  break;
515  case 600:
516  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_150);
517  rxstale = 1;
518  break;
519  case 1200:
520  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_300);
521  rxstale = 1;
522  break;
523  case 2400:
524  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_600);
525  rxstale = 1;
526  break;
527  case 4800:
528  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_1200);
529  rxstale = 1;
530  break;
531  case 9600:
532  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
533  rxstale = 2;
534  break;
535  case 14400:
536  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_3600);
537  rxstale = 3;
538  break;
539  case 19200:
540  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_4800);
541  rxstale = 4;
542  break;
543  case 28800:
544  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_7200);
545  rxstale = 6;
546  break;
547  case 38400:
548  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_9600);
549  rxstale = 8;
550  break;
551  case 57600:
552  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_14400);
553  rxstale = 16;
554  break;
555  case 76800:
556  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_19200);
557  rxstale = 16;
558  break;
559  case 115200:
560  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_28800);
561  rxstale = 31;
562  break;
563  case 230400:
564  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_57600);
565  rxstale = 31;
566  break;
567  case 460800:
568  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
569  rxstale = 31;
570  break;
571  case 4000000:
572  case 3686400:
573  case 3200000:
574  case 3500000:
575  case 3000000:
576  case 2500000:
577  case 1500000:
578  case 1152000:
579  case 1000000:
580  case 921600:
581  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
582  rxstale = 31;
583  break;
584  default:
585  msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
586  /* default to 9600 */
587  bps = 9600;
588  rxstale = 2;
589  break;
590  }
591  if (bps > 460800)
592  uport->uartclk = bps * 16;
593  else
594  uport->uartclk = UARTCLK;
595 
596  if (clk_set_rate(msm_uport->clk, uport->uartclk)) {
597  printk(KERN_WARNING "Error setting clock rate on UART\n");
598  return;
599  }
600 
601  data = rxstale & UARTDM_IPR_STALE_LSB_BMSK;
602  data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
603 
604  msm_hs_write(uport, UARTDM_IPR_ADDR, data);
605 }
606 
607 /*
608  * termios : new ktermios
609  * oldtermios: old ktermios previous setting
610  *
611  * Configure the serial port
612  */
613 static void msm_hs_set_termios(struct uart_port *uport,
614  struct ktermios *termios,
615  struct ktermios *oldtermios)
616 {
617  unsigned int bps;
618  unsigned long data;
619  unsigned long flags;
620  unsigned int c_cflag = termios->c_cflag;
621  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
622 
623  spin_lock_irqsave(&uport->lock, flags);
624  clk_enable(msm_uport->clk);
625 
626  /* 300 is the minimum baud support by the driver */
627  bps = uart_get_baud_rate(uport, termios, oldtermios, 200, 4000000);
628 
629  /* Temporary remapping 200 BAUD to 3.2 mbps */
630  if (bps == 200)
631  bps = 3200000;
632 
633  msm_hs_set_bps_locked(uport, bps);
634 
635  data = msm_hs_read(uport, UARTDM_MR2_ADDR);
637  /* set parity */
638  if (PARENB == (c_cflag & PARENB)) {
639  if (PARODD == (c_cflag & PARODD))
640  data |= ODD_PARITY;
641  else if (CMSPAR == (c_cflag & CMSPAR))
642  data |= SPACE_PARITY;
643  else
644  data |= EVEN_PARITY;
645  }
646 
647  /* Set bits per char */
649 
650  switch (c_cflag & CSIZE) {
651  case CS5:
652  data |= FIVE_BPC;
653  break;
654  case CS6:
655  data |= SIX_BPC;
656  break;
657  case CS7:
658  data |= SEVEN_BPC;
659  break;
660  default:
661  data |= EIGHT_BPC;
662  break;
663  }
664  /* stop bits */
665  if (c_cflag & CSTOPB) {
666  data |= STOP_BIT_TWO;
667  } else {
668  /* otherwise 1 stop bit */
669  data |= STOP_BIT_ONE;
670  }
672  /* write parity/bits per char/stop bit configuration */
673  msm_hs_write(uport, UARTDM_MR2_ADDR, data);
674 
675  /* Configure HW flow control */
676  data = msm_hs_read(uport, UARTDM_MR1_ADDR);
677 
679 
680  if (c_cflag & CRTSCTS) {
681  data |= UARTDM_MR1_CTS_CTL_BMSK;
683  }
684 
685  msm_hs_write(uport, UARTDM_MR1_ADDR, data);
686 
687  uport->ignore_status_mask = termios->c_iflag & INPCK;
688  uport->ignore_status_mask |= termios->c_iflag & IGNPAR;
689  uport->read_status_mask = (termios->c_cflag & CREAD);
690 
691  msm_hs_write(uport, UARTDM_IMR_ADDR, 0);
692 
693  /* Set Transmit software time out */
694  uart_update_timeout(uport, c_cflag, bps);
695 
696  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
697  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
698 
699  if (msm_uport->rx.flush == FLUSH_NONE) {
700  msm_uport->rx.flush = FLUSH_IGNORE;
701  msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
702  }
703 
704  msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
705 
706  clk_disable(msm_uport->clk);
707  spin_unlock_irqrestore(&uport->lock, flags);
708 }
709 
710 /*
711  * Standard API, Transmitter
712  * Any character in the transmit shift register is sent
713  */
714 static unsigned int msm_hs_tx_empty(struct uart_port *uport)
715 {
716  unsigned int data;
717  unsigned int ret = 0;
718  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
719 
720  clk_enable(msm_uport->clk);
721 
722  data = msm_hs_read(uport, UARTDM_SR_ADDR);
723  if (data & UARTDM_SR_TXEMT_BMSK)
724  ret = TIOCSER_TEMT;
725 
726  clk_disable(msm_uport->clk);
727 
728  return ret;
729 }
730 
731 /*
732  * Standard API, Stop transmitter.
733  * Any character in the transmit shift register is sent as
734  * well as the current data mover transfer .
735  */
736 static void msm_hs_stop_tx_locked(struct uart_port *uport)
737 {
738  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
739 
740  msm_uport->tx.tx_ready_int_en = 0;
741 }
742 
743 /*
744  * Standard API, Stop receiver as soon as possible.
745  *
746  * Function immediately terminates the operation of the
747  * channel receiver and any incoming characters are lost. None
748  * of the receiver status bits are affected by this command and
749  * characters that are already in the receive FIFO there.
750  */
751 static void msm_hs_stop_rx_locked(struct uart_port *uport)
752 {
753  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
754  unsigned int data;
755 
756  clk_enable(msm_uport->clk);
757 
758  /* disable dlink */
759  data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
760  data &= ~UARTDM_RX_DM_EN_BMSK;
761  msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
762 
763  /* Disable the receiver */
764  if (msm_uport->rx.flush == FLUSH_NONE)
765  msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
766 
767  if (msm_uport->rx.flush != FLUSH_SHUTDOWN)
768  msm_uport->rx.flush = FLUSH_STOP;
769 
770  clk_disable(msm_uport->clk);
771 }
772 
773 /* Transmit the next chunk of data */
774 static void msm_hs_submit_tx_locked(struct uart_port *uport)
775 {
776  int left;
777  int tx_count;
779  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
780  struct msm_hs_tx *tx = &msm_uport->tx;
781  struct circ_buf *tx_buf = &msm_uport->uport.state->xmit;
782 
783  if (uart_circ_empty(tx_buf) || uport->state->port.tty->stopped) {
784  msm_hs_stop_tx_locked(uport);
785  return;
786  }
787 
788  tx->dma_in_flight = 1;
789 
790  tx_count = uart_circ_chars_pending(tx_buf);
791 
792  if (UARTDM_TX_BUF_SIZE < tx_count)
793  tx_count = UARTDM_TX_BUF_SIZE;
794 
795  left = UART_XMIT_SIZE - tx_buf->tail;
796 
797  if (tx_count > left)
798  tx_count = left;
799 
800  src_addr = tx->dma_base + tx_buf->tail;
801  dma_sync_single_for_device(uport->dev, src_addr, tx_count,
802  DMA_TO_DEVICE);
803 
804  tx->command_ptr->num_rows = (((tx_count + 15) >> 4) << 16) |
805  ((tx_count + 15) >> 4);
807 
809  sizeof(dmov_box), DMA_TO_DEVICE);
810 
812 
814  sizeof(u32), DMA_TO_DEVICE);
815 
816  /* Save tx_count to use in Callback */
817  tx->tx_count = tx_count;
818  msm_hs_write(uport, UARTDM_NCF_TX_ADDR, tx_count);
819 
820  /* Disable the tx_ready interrupt */
821  msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK;
822  msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
823  msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer);
824 }
825 
826 /* Start to receive the next chunk of data */
827 static void msm_hs_start_rx_locked(struct uart_port *uport)
828 {
829  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
830 
831  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
832  msm_hs_write(uport, UARTDM_DMRX_ADDR, UARTDM_RX_BUF_SIZE);
833  msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_ENABLE);
834  msm_uport->imr_reg |= UARTDM_ISR_RXLEV_BMSK;
835  msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
836 
837  msm_uport->rx.flush = FLUSH_NONE;
838  msm_dmov_enqueue_cmd(msm_uport->dma_rx_channel, &msm_uport->rx.xfer);
839 
840  /* might have finished RX and be ready to clock off */
841  hrtimer_start(&msm_uport->clk_off_timer, msm_uport->clk_off_delay,
843 }
844 
845 /* Enable the transmitter Interrupt */
846 static void msm_hs_start_tx_locked(struct uart_port *uport)
847 {
848  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
849 
850  clk_enable(msm_uport->clk);
851 
852  if (msm_uport->exit_lpm_cb)
853  msm_uport->exit_lpm_cb(uport);
854 
855  if (msm_uport->tx.tx_ready_int_en == 0) {
856  msm_uport->tx.tx_ready_int_en = 1;
857  msm_hs_submit_tx_locked(uport);
858  }
859 
860  clk_disable(msm_uport->clk);
861 }
862 
863 /*
864  * This routine is called when we are done with a DMA transfer
865  *
866  * This routine is registered with Data mover when we set
867  * up a Data Mover transfer. It is called from Data mover ISR
868  * when the DMA transfer is done.
869  */
870 static void msm_hs_dmov_tx_callback(struct msm_dmov_cmd *cmd_ptr,
871  unsigned int result,
872  struct msm_dmov_errdata *err)
873 {
874  unsigned long flags;
875  struct msm_hs_port *msm_uport;
876 
877  /* DMA did not finish properly */
878  WARN_ON((((result & RSLT_FIFO_CNTR_BMSK) >> 28) == 1) &&
879  !(result & RSLT_VLD));
880 
881  msm_uport = container_of(cmd_ptr, struct msm_hs_port, tx.xfer);
882 
883  spin_lock_irqsave(&msm_uport->uport.lock, flags);
884  clk_enable(msm_uport->clk);
885 
886  msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK;
887  msm_hs_write(&msm_uport->uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
888 
889  clk_disable(msm_uport->clk);
890  spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
891 }
892 
893 /*
894  * This routine is called when we are done with a DMA transfer or the
895  * a flush has been sent to the data mover driver.
896  *
897  * This routine is registered with Data mover when we set up a Data Mover
898  * transfer. It is called from Data mover ISR when the DMA transfer is done.
899  */
900 static void msm_hs_dmov_rx_callback(struct msm_dmov_cmd *cmd_ptr,
901  unsigned int result,
902  struct msm_dmov_errdata *err)
903 {
904  int retval;
905  int rx_count;
906  unsigned long status;
907  unsigned int error_f = 0;
908  unsigned long flags;
909  unsigned int flush;
910  struct tty_struct *tty;
911  struct uart_port *uport;
912  struct msm_hs_port *msm_uport;
913 
914  msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer);
915  uport = &msm_uport->uport;
916 
917  spin_lock_irqsave(&uport->lock, flags);
918  clk_enable(msm_uport->clk);
919 
920  tty = uport->state->port.tty;
921 
922  msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
923 
924  status = msm_hs_read(uport, UARTDM_SR_ADDR);
925 
926  /* overflow is not connect to data in a FIFO */
927  if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) &&
928  (uport->read_status_mask & CREAD))) {
929  tty_insert_flip_char(tty, 0, TTY_OVERRUN);
930  uport->icount.buf_overrun++;
931  error_f = 1;
932  }
933 
934  if (!(uport->ignore_status_mask & INPCK))
935  status = status & ~(UARTDM_SR_PAR_FRAME_BMSK);
936 
937  if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) {
938  /* Can not tell difference between parity & frame error */
939  uport->icount.parity++;
940  error_f = 1;
941  if (uport->ignore_status_mask & IGNPAR)
942  tty_insert_flip_char(tty, 0, TTY_PARITY);
943  }
944 
945  if (error_f)
946  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
947 
950 
951  flush = msm_uport->rx.flush;
952  if (flush == FLUSH_IGNORE)
953  msm_hs_start_rx_locked(uport);
954  if (flush == FLUSH_STOP)
955  msm_uport->rx.flush = FLUSH_SHUTDOWN;
956  if (flush >= FLUSH_DATA_INVALID)
957  goto out;
958 
959  rx_count = msm_hs_read(uport, UARTDM_RX_TOTAL_SNAP_ADDR);
960 
961  if (0 != (uport->read_status_mask & CREAD)) {
962  retval = tty_insert_flip_string(tty, msm_uport->rx.buffer,
963  rx_count);
964  BUG_ON(retval != rx_count);
965  }
966 
967  msm_hs_start_rx_locked(uport);
968 
969 out:
970  clk_disable(msm_uport->clk);
971 
972  spin_unlock_irqrestore(&uport->lock, flags);
973 
974  if (flush < FLUSH_DATA_INVALID)
975  queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
976 }
977 
978 static void msm_hs_tty_flip_buffer_work(struct work_struct *work)
979 {
980  struct msm_hs_port *msm_uport =
981  container_of(work, struct msm_hs_port, rx.tty_work);
982  struct tty_struct *tty = msm_uport->uport.state->port.tty;
983 
985 }
986 
987 /*
988  * Standard API, Current states of modem control inputs
989  *
990  * Since CTS can be handled entirely by HARDWARE we always
991  * indicate clear to send and count on the TX FIFO to block when
992  * it fills up.
993  *
994  * - TIOCM_DCD
995  * - TIOCM_CTS
996  * - TIOCM_DSR
997  * - TIOCM_RI
998  * (Unsupported) DCD and DSR will return them high. RI will return low.
999  */
1000 static unsigned int msm_hs_get_mctrl_locked(struct uart_port *uport)
1001 {
1002  return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
1003 }
1004 
1005 /*
1006  * True enables UART auto RFR, which indicates we are ready for data if the RX
1007  * buffer is not full. False disables auto RFR, and deasserts RFR to indicate
1008  * we are not ready for data. Must be called with UART clock on.
1009  */
1010 static void set_rfr_locked(struct uart_port *uport, int auto_rfr)
1011 {
1012  unsigned int data;
1013 
1014  data = msm_hs_read(uport, UARTDM_MR1_ADDR);
1015 
1016  if (auto_rfr) {
1017  /* enable auto ready-for-receiving */
1019  msm_hs_write(uport, UARTDM_MR1_ADDR, data);
1020  } else {
1021  /* disable auto ready-for-receiving */
1022  data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
1023  msm_hs_write(uport, UARTDM_MR1_ADDR, data);
1024  /* RFR is active low, set high */
1025  msm_hs_write(uport, UARTDM_CR_ADDR, RFR_HIGH);
1026  }
1027 }
1028 
1029 /*
1030  * Standard API, used to set or clear RFR
1031  */
1032 static void msm_hs_set_mctrl_locked(struct uart_port *uport,
1033  unsigned int mctrl)
1034 {
1035  unsigned int auto_rfr;
1036  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1037 
1038  clk_enable(msm_uport->clk);
1039 
1040  auto_rfr = TIOCM_RTS & mctrl ? 1 : 0;
1041  set_rfr_locked(uport, auto_rfr);
1042 
1043  clk_disable(msm_uport->clk);
1044 }
1045 
1046 /* Standard API, Enable modem status (CTS) interrupt */
1047 static void msm_hs_enable_ms_locked(struct uart_port *uport)
1048 {
1049  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1050 
1051  clk_enable(msm_uport->clk);
1052 
1053  /* Enable DELTA_CTS Interrupt */
1054  msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK;
1055  msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1056 
1057  clk_disable(msm_uport->clk);
1058 
1059 }
1060 
1061 /*
1062  * Standard API, Break Signal
1063  *
1064  * Control the transmission of a break signal. ctl eq 0 => break
1065  * signal terminate ctl ne 0 => start break signal
1066  */
1067 static void msm_hs_break_ctl(struct uart_port *uport, int ctl)
1068 {
1069  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1070 
1071  clk_enable(msm_uport->clk);
1072  msm_hs_write(uport, UARTDM_CR_ADDR, ctl ? START_BREAK : STOP_BREAK);
1073  clk_disable(msm_uport->clk);
1074 }
1075 
1076 static void msm_hs_config_port(struct uart_port *uport, int cfg_flags)
1077 {
1078  unsigned long flags;
1079 
1080  spin_lock_irqsave(&uport->lock, flags);
1081  if (cfg_flags & UART_CONFIG_TYPE) {
1082  uport->type = PORT_MSM;
1083  msm_hs_request_port(uport);
1084  }
1085  spin_unlock_irqrestore(&uport->lock, flags);
1086 }
1087 
1088 /* Handle CTS changes (Called from interrupt handler) */
1089 static void msm_hs_handle_delta_cts_locked(struct uart_port *uport)
1090 {
1091  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1092 
1093  clk_enable(msm_uport->clk);
1094 
1095  /* clear interrupt */
1096  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS);
1097  uport->icount.cts++;
1098 
1099  clk_disable(msm_uport->clk);
1100 
1101  /* clear the IOCTL TIOCMIWAIT if called */
1102  wake_up_interruptible(&uport->state->port.delta_msr_wait);
1103 }
1104 
1105 /* check if the TX path is flushed, and if so clock off
1106  * returns 0 did not clock off, need to retry (still sending final byte)
1107  * -1 did not clock off, do not retry
1108  * 1 if we clocked off
1109  */
1110 static int msm_hs_check_clock_off_locked(struct uart_port *uport)
1111 {
1112  unsigned long sr_status;
1113  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1114  struct circ_buf *tx_buf = &uport->state->xmit;
1115 
1116  /* Cancel if tx tty buffer is not empty, dma is in flight,
1117  * or tx fifo is not empty, or rx fifo is not empty */
1118  if (msm_uport->clk_state != MSM_HS_CLK_REQUEST_OFF ||
1119  !uart_circ_empty(tx_buf) || msm_uport->tx.dma_in_flight ||
1120  (msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) ||
1121  !(msm_uport->imr_reg & UARTDM_ISR_RXLEV_BMSK)) {
1122  return -1;
1123  }
1124 
1125  /* Make sure the uart is finished with the last byte */
1126  sr_status = msm_hs_read(uport, UARTDM_SR_ADDR);
1127  if (!(sr_status & UARTDM_SR_TXEMT_BMSK))
1128  return 0; /* retry */
1129 
1130  /* Make sure forced RXSTALE flush complete */
1131  switch (msm_uport->clk_req_off_state) {
1132  case CLK_REQ_OFF_START:
1134  msm_hs_write(uport, UARTDM_CR_ADDR, FORCE_STALE_EVENT);
1135  return 0; /* RXSTALE flush not complete - retry */
1138  return 0; /* RXSTALE flush not complete - retry */
1140  break; /* continue */
1141  }
1142 
1143  if (msm_uport->rx.flush != FLUSH_SHUTDOWN) {
1144  if (msm_uport->rx.flush == FLUSH_NONE)
1145  msm_hs_stop_rx_locked(uport);
1146  return 0; /* come back later to really clock off */
1147  }
1148 
1149  /* we really want to clock off */
1150  clk_disable(msm_uport->clk);
1151  msm_uport->clk_state = MSM_HS_CLK_OFF;
1152 
1153  if (use_low_power_rx_wakeup(msm_uport)) {
1154  msm_uport->rx_wakeup.ignore = 1;
1155  enable_irq(msm_uport->rx_wakeup.irq);
1156  }
1157  return 1;
1158 }
1159 
1160 static enum hrtimer_restart msm_hs_clk_off_retry(struct hrtimer *timer)
1161 {
1162  unsigned long flags;
1163  int ret = HRTIMER_NORESTART;
1164  struct msm_hs_port *msm_uport = container_of(timer, struct msm_hs_port,
1165  clk_off_timer);
1166  struct uart_port *uport = &msm_uport->uport;
1167 
1168  spin_lock_irqsave(&uport->lock, flags);
1169 
1170  if (!msm_hs_check_clock_off_locked(uport)) {
1171  hrtimer_forward_now(timer, msm_uport->clk_off_delay);
1172  ret = HRTIMER_RESTART;
1173  }
1174 
1175  spin_unlock_irqrestore(&uport->lock, flags);
1176 
1177  return ret;
1178 }
1179 
1180 static irqreturn_t msm_hs_isr(int irq, void *dev)
1181 {
1182  unsigned long flags;
1183  unsigned long isr_status;
1184  struct msm_hs_port *msm_uport = dev;
1185  struct uart_port *uport = &msm_uport->uport;
1186  struct circ_buf *tx_buf = &uport->state->xmit;
1187  struct msm_hs_tx *tx = &msm_uport->tx;
1188  struct msm_hs_rx *rx = &msm_uport->rx;
1189 
1190  spin_lock_irqsave(&uport->lock, flags);
1191 
1192  isr_status = msm_hs_read(uport, UARTDM_MISR_ADDR);
1193 
1194  /* Uart RX starting */
1195  if (isr_status & UARTDM_ISR_RXLEV_BMSK) {
1196  msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK;
1197  msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1198  }
1199  /* Stale rx interrupt */
1200  if (isr_status & UARTDM_ISR_RXSTALE_BMSK) {
1201  msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
1202  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
1203 
1205  msm_uport->clk_req_off_state =
1207  if (rx->flush == FLUSH_NONE) {
1208  rx->flush = FLUSH_DATA_READY;
1209  msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
1210  }
1211  }
1212  /* tx ready interrupt */
1213  if (isr_status & UARTDM_ISR_TX_READY_BMSK) {
1214  /* Clear TX Ready */
1215  msm_hs_write(uport, UARTDM_CR_ADDR, CLEAR_TX_READY);
1216 
1217  if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) {
1218  msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
1219  msm_hs_write(uport, UARTDM_IMR_ADDR,
1220  msm_uport->imr_reg);
1221  }
1222 
1223  /* Complete DMA TX transactions and submit new transactions */
1224  tx_buf->tail = (tx_buf->tail + tx->tx_count) & ~UART_XMIT_SIZE;
1225 
1226  tx->dma_in_flight = 0;
1227 
1228  uport->icount.tx += tx->tx_count;
1229  if (tx->tx_ready_int_en)
1230  msm_hs_submit_tx_locked(uport);
1231 
1232  if (uart_circ_chars_pending(tx_buf) < WAKEUP_CHARS)
1233  uart_write_wakeup(uport);
1234  }
1235  if (isr_status & UARTDM_ISR_TXLEV_BMSK) {
1236  /* TX FIFO is empty */
1237  msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK;
1238  msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1239  if (!msm_hs_check_clock_off_locked(uport))
1240  hrtimer_start(&msm_uport->clk_off_timer,
1241  msm_uport->clk_off_delay,
1243  }
1244 
1245  /* Change in CTS interrupt */
1246  if (isr_status & UARTDM_ISR_DELTA_CTS_BMSK)
1247  msm_hs_handle_delta_cts_locked(uport);
1248 
1249  spin_unlock_irqrestore(&uport->lock, flags);
1250 
1251  return IRQ_HANDLED;
1252 }
1253 
1255 {
1256  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1257 
1258  if (msm_uport->clk_state == MSM_HS_CLK_ON) {
1259  msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF;
1260  msm_uport->clk_req_off_state = CLK_REQ_OFF_START;
1261  if (!use_low_power_rx_wakeup(msm_uport))
1262  set_rfr_locked(uport, 0);
1263  msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
1264  msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1265  }
1266 }
1267 
1281 {
1282  unsigned long flags;
1283 
1284  spin_lock_irqsave(&uport->lock, flags);
1286  spin_unlock_irqrestore(&uport->lock, flags);
1287 }
1288 
1290 {
1291  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1292  unsigned int data;
1293 
1294  switch (msm_uport->clk_state) {
1295  case MSM_HS_CLK_OFF:
1296  clk_enable(msm_uport->clk);
1297  disable_irq_nosync(msm_uport->rx_wakeup.irq);
1298  /* fall-through */
1300  if (msm_uport->rx.flush == FLUSH_STOP ||
1301  msm_uport->rx.flush == FLUSH_SHUTDOWN) {
1302  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
1303  data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
1304  data |= UARTDM_RX_DM_EN_BMSK;
1305  msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
1306  }
1307  hrtimer_try_to_cancel(&msm_uport->clk_off_timer);
1308  if (msm_uport->rx.flush == FLUSH_SHUTDOWN)
1309  msm_hs_start_rx_locked(uport);
1310  if (!use_low_power_rx_wakeup(msm_uport))
1311  set_rfr_locked(uport, 1);
1312  if (msm_uport->rx.flush == FLUSH_STOP)
1313  msm_uport->rx.flush = FLUSH_IGNORE;
1314  msm_uport->clk_state = MSM_HS_CLK_ON;
1315  break;
1316  case MSM_HS_CLK_ON:
1317  break;
1318  case MSM_HS_CLK_PORT_OFF:
1319  break;
1320  }
1321 }
1322 
1333 {
1334  unsigned long flags;
1335 
1336  spin_lock_irqsave(&uport->lock, flags);
1338  spin_unlock_irqrestore(&uport->lock, flags);
1339 }
1340 
1341 static irqreturn_t msm_hs_rx_wakeup_isr(int irq, void *dev)
1342 {
1343  unsigned int wakeup = 0;
1344  unsigned long flags;
1345  struct msm_hs_port *msm_uport = dev;
1346  struct uart_port *uport = &msm_uport->uport;
1347  struct tty_struct *tty = NULL;
1348 
1349  spin_lock_irqsave(&uport->lock, flags);
1350  if (msm_uport->clk_state == MSM_HS_CLK_OFF) {
1351  /* ignore the first irq - it is a pending irq that occurred
1352  * before enable_irq() */
1353  if (msm_uport->rx_wakeup.ignore)
1354  msm_uport->rx_wakeup.ignore = 0;
1355  else
1356  wakeup = 1;
1357  }
1358 
1359  if (wakeup) {
1360  /* the uart was clocked off during an rx, wake up and
1361  * optionally inject char into tty rx */
1363  if (msm_uport->rx_wakeup.inject_rx) {
1364  tty = uport->state->port.tty;
1365  tty_insert_flip_char(tty,
1366  msm_uport->rx_wakeup.rx_to_inject,
1367  TTY_NORMAL);
1368  queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
1369  }
1370  }
1371 
1372  spin_unlock_irqrestore(&uport->lock, flags);
1373 
1374  return IRQ_HANDLED;
1375 }
1376 
1377 static const char *msm_hs_type(struct uart_port *port)
1378 {
1379  return (port->type == PORT_MSM) ? "MSM_HS_UART" : NULL;
1380 }
1381 
1382 /* Called when port is opened */
1383 static int msm_hs_startup(struct uart_port *uport)
1384 {
1385  int ret;
1386  int rfr_level;
1387  unsigned long flags;
1388  unsigned int data;
1389  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1390  struct circ_buf *tx_buf = &uport->state->xmit;
1391  struct msm_hs_tx *tx = &msm_uport->tx;
1392  struct msm_hs_rx *rx = &msm_uport->rx;
1393 
1394  rfr_level = uport->fifosize;
1395  if (rfr_level > 16)
1396  rfr_level -= 16;
1397 
1398  tx->dma_base = dma_map_single(uport->dev, tx_buf->buf, UART_XMIT_SIZE,
1399  DMA_TO_DEVICE);
1400 
1401  /* do not let tty layer execute RX in global workqueue, use a
1402  * dedicated workqueue managed by this driver */
1403  uport->state->port.tty->low_latency = 1;
1404 
1405  /* turn on uart clk */
1406  ret = msm_hs_init_clk_locked(uport);
1407  if (unlikely(ret)) {
1408  printk(KERN_ERR "Turning uartclk failed!\n");
1409  goto err_msm_hs_init_clk;
1410  }
1411 
1412  /* Set auto RFR Level */
1413  data = msm_hs_read(uport, UARTDM_MR1_ADDR);
1416  data |= (UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2));
1417  data |= (UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level);
1418  msm_hs_write(uport, UARTDM_MR1_ADDR, data);
1419 
1420  /* Make sure RXSTALE count is non-zero */
1421  data = msm_hs_read(uport, UARTDM_IPR_ADDR);
1422  if (!data) {
1423  data |= 0x1f & UARTDM_IPR_STALE_LSB_BMSK;
1424  msm_hs_write(uport, UARTDM_IPR_ADDR, data);
1425  }
1426 
1427  /* Enable Data Mover Mode */
1429  msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
1430 
1431  /* Reset TX */
1432  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
1433  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
1434  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
1435  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_BREAK_INT);
1436  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
1437  msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS);
1438  msm_hs_write(uport, UARTDM_CR_ADDR, RFR_LOW);
1439  /* Turn on Uart Receiver */
1440  msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_EN_BMSK);
1441 
1442  /* Turn on Uart Transmitter */
1443  msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_EN_BMSK);
1444 
1445  /* Initialize the tx */
1446  tx->tx_ready_int_en = 0;
1447  tx->dma_in_flight = 0;
1448 
1449  tx->xfer.complete_func = msm_hs_dmov_tx_callback;
1450  tx->xfer.execute_func = NULL;
1451 
1452  tx->command_ptr->cmd = CMD_LC |
1453  CMD_DST_CRCI(msm_uport->dma_tx_crci) | CMD_MODE_BOX;
1454 
1457 
1459 
1460  tx->command_ptr->dst_row_addr =
1461  msm_uport->uport.mapbase + UARTDM_TF_ADDR;
1462 
1463 
1464  /* Turn on Uart Receive */
1465  rx->xfer.complete_func = msm_hs_dmov_rx_callback;
1466  rx->xfer.execute_func = NULL;
1467 
1468  rx->command_ptr->cmd = CMD_LC |
1469  CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX;
1470 
1475 
1476 
1477  msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK;
1478  /* Enable reading the current CTS, no harm even if CTS is ignored */
1479  msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK;
1480 
1481  msm_hs_write(uport, UARTDM_TFWR_ADDR, 0); /* TXLEV on empty TX fifo */
1482 
1483 
1484  ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH,
1485  "msm_hs_uart", msm_uport);
1486  if (unlikely(ret)) {
1487  printk(KERN_ERR "Request msm_hs_uart IRQ failed!\n");
1488  goto err_request_irq;
1489  }
1490  if (use_low_power_rx_wakeup(msm_uport)) {
1491  ret = request_irq(msm_uport->rx_wakeup.irq,
1492  msm_hs_rx_wakeup_isr,
1494  "msm_hs_rx_wakeup", msm_uport);
1495  if (unlikely(ret)) {
1496  printk(KERN_ERR "Request msm_hs_rx_wakeup IRQ failed!\n");
1497  free_irq(uport->irq, msm_uport);
1498  goto err_request_irq;
1499  }
1500  disable_irq(msm_uport->rx_wakeup.irq);
1501  }
1502 
1503  spin_lock_irqsave(&uport->lock, flags);
1504 
1505  msm_hs_write(uport, UARTDM_RFWR_ADDR, 0);
1506  msm_hs_start_rx_locked(uport);
1507 
1508  spin_unlock_irqrestore(&uport->lock, flags);
1509  ret = pm_runtime_set_active(uport->dev);
1510  if (ret)
1511  dev_err(uport->dev, "set active error:%d\n", ret);
1512  pm_runtime_enable(uport->dev);
1513 
1514  return 0;
1515 
1516 err_request_irq:
1517 err_msm_hs_init_clk:
1518  dma_unmap_single(uport->dev, tx->dma_base,
1520  return ret;
1521 }
1522 
1523 /* Initialize tx and rx data structures */
1524 static int __devinit uartdm_init_port(struct uart_port *uport)
1525 {
1526  int ret = 0;
1527  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1528  struct msm_hs_tx *tx = &msm_uport->tx;
1529  struct msm_hs_rx *rx = &msm_uport->rx;
1530 
1531  /* Allocate the command pointer. Needs to be 64 bit aligned */
1532  tx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
1533  if (!tx->command_ptr)
1534  return -ENOMEM;
1535 
1536  tx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA);
1537  if (!tx->command_ptr_ptr) {
1538  ret = -ENOMEM;
1539  goto err_tx_command_ptr_ptr;
1540  }
1541 
1542  tx->mapped_cmd_ptr = dma_map_single(uport->dev, tx->command_ptr,
1543  sizeof(dmov_box), DMA_TO_DEVICE);
1544  tx->mapped_cmd_ptr_ptr = dma_map_single(uport->dev,
1545  tx->command_ptr_ptr,
1546  sizeof(u32), DMA_TO_DEVICE);
1547  tx->xfer.cmdptr = DMOV_CMD_ADDR(tx->mapped_cmd_ptr_ptr);
1548 
1549  init_waitqueue_head(&rx->wait);
1550 
1551  rx->pool = dma_pool_create("rx_buffer_pool", uport->dev,
1552  UARTDM_RX_BUF_SIZE, 16, 0);
1553  if (!rx->pool) {
1554  pr_err("%s(): cannot allocate rx_buffer_pool", __func__);
1555  ret = -ENOMEM;
1556  goto err_dma_pool_create;
1557  }
1558 
1559  rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer);
1560  if (!rx->buffer) {
1561  pr_err("%s(): cannot allocate rx->buffer", __func__);
1562  ret = -ENOMEM;
1563  goto err_dma_pool_alloc;
1564  }
1565 
1566  /* Allocate the command pointer. Needs to be 64 bit aligned */
1567  rx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
1568  if (!rx->command_ptr) {
1569  pr_err("%s(): cannot allocate rx->command_ptr", __func__);
1570  ret = -ENOMEM;
1571  goto err_rx_command_ptr;
1572  }
1573 
1574  rx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA);
1575  if (!rx->command_ptr_ptr) {
1576  pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__);
1577  ret = -ENOMEM;
1578  goto err_rx_command_ptr_ptr;
1579  }
1580 
1581  rx->command_ptr->num_rows = ((UARTDM_RX_BUF_SIZE >> 4) << 16) |
1582  (UARTDM_RX_BUF_SIZE >> 4);
1583 
1584  rx->command_ptr->dst_row_addr = rx->rbuffer;
1585 
1586  rx->mapped_cmd_ptr = dma_map_single(uport->dev, rx->command_ptr,
1587  sizeof(dmov_box), DMA_TO_DEVICE);
1588 
1590 
1592  sizeof(u32), DMA_TO_DEVICE);
1593  rx->xfer.cmdptr = DMOV_CMD_ADDR(rx->cmdptr_dmaaddr);
1594 
1595  INIT_WORK(&rx->tty_work, msm_hs_tty_flip_buffer_work);
1596 
1597  return ret;
1598 
1599 err_rx_command_ptr_ptr:
1600  kfree(rx->command_ptr);
1601 err_rx_command_ptr:
1602  dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
1603  msm_uport->rx.rbuffer);
1604 err_dma_pool_alloc:
1605  dma_pool_destroy(msm_uport->rx.pool);
1606 err_dma_pool_create:
1607  dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr_ptr,
1608  sizeof(u32), DMA_TO_DEVICE);
1609  dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr,
1610  sizeof(dmov_box), DMA_TO_DEVICE);
1611  kfree(msm_uport->tx.command_ptr_ptr);
1612 err_tx_command_ptr_ptr:
1613  kfree(msm_uport->tx.command_ptr);
1614  return ret;
1615 }
1616 
1617 static int __devinit msm_hs_probe(struct platform_device *pdev)
1618 {
1619  int ret;
1620  struct uart_port *uport;
1621  struct msm_hs_port *msm_uport;
1622  struct resource *resource;
1623  const struct msm_serial_hs_platform_data *pdata =
1624  pdev->dev.platform_data;
1625 
1626  if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
1627  printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
1628  return -EINVAL;
1629  }
1630 
1631  msm_uport = &q_uart_port[pdev->id];
1632  uport = &msm_uport->uport;
1633 
1634  uport->dev = &pdev->dev;
1635 
1636  resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1637  if (unlikely(!resource))
1638  return -ENXIO;
1639 
1640  uport->mapbase = resource->start;
1641  uport->irq = platform_get_irq(pdev, 0);
1642  if (unlikely(uport->irq < 0))
1643  return -ENXIO;
1644 
1645  if (unlikely(irq_set_irq_wake(uport->irq, 1)))
1646  return -ENXIO;
1647 
1648  if (pdata == NULL || pdata->rx_wakeup_irq < 0)
1649  msm_uport->rx_wakeup.irq = -1;
1650  else {
1651  msm_uport->rx_wakeup.irq = pdata->rx_wakeup_irq;
1652  msm_uport->rx_wakeup.ignore = 1;
1653  msm_uport->rx_wakeup.inject_rx = pdata->inject_rx_on_wakeup;
1654  msm_uport->rx_wakeup.rx_to_inject = pdata->rx_to_inject;
1655 
1656  if (unlikely(msm_uport->rx_wakeup.irq < 0))
1657  return -ENXIO;
1658 
1659  if (unlikely(irq_set_irq_wake(msm_uport->rx_wakeup.irq, 1)))
1660  return -ENXIO;
1661  }
1662 
1663  if (pdata == NULL)
1664  msm_uport->exit_lpm_cb = NULL;
1665  else
1666  msm_uport->exit_lpm_cb = pdata->exit_lpm_cb;
1667 
1669  "uartdm_channels");
1670  if (unlikely(!resource))
1671  return -ENXIO;
1672 
1673  msm_uport->dma_tx_channel = resource->start;
1674  msm_uport->dma_rx_channel = resource->end;
1675 
1677  "uartdm_crci");
1678  if (unlikely(!resource))
1679  return -ENXIO;
1680 
1681  msm_uport->dma_tx_crci = resource->start;
1682  msm_uport->dma_rx_crci = resource->end;
1683 
1684  uport->iotype = UPIO_MEM;
1685  uport->fifosize = UART_FIFOSIZE;
1686  uport->ops = &msm_hs_ops;
1687  uport->flags = UPF_BOOT_AUTOCONF;
1688  uport->uartclk = UARTCLK;
1689  msm_uport->imr_reg = 0x0;
1690  msm_uport->clk = clk_get(&pdev->dev, "uartdm_clk");
1691  if (IS_ERR(msm_uport->clk))
1692  return PTR_ERR(msm_uport->clk);
1693 
1694  ret = uartdm_init_port(uport);
1695  if (unlikely(ret))
1696  return ret;
1697 
1698  msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
1701  msm_uport->clk_off_timer.function = msm_hs_clk_off_retry;
1702  msm_uport->clk_off_delay = ktime_set(0, 1000000); /* 1ms */
1703 
1704  uport->line = pdev->id;
1705  return uart_add_one_port(&msm_hs_driver, uport);
1706 }
1707 
1708 static int __init msm_serial_hs_init(void)
1709 {
1710  int ret, i;
1711 
1712  /* Init all UARTS as non-configured */
1713  for (i = 0; i < UARTDM_NR; i++)
1714  q_uart_port[i].uport.type = PORT_UNKNOWN;
1715 
1716  msm_hs_workqueue = create_singlethread_workqueue("msm_serial_hs");
1717  if (unlikely(!msm_hs_workqueue))
1718  return -ENOMEM;
1719 
1720  ret = uart_register_driver(&msm_hs_driver);
1721  if (unlikely(ret)) {
1722  printk(KERN_ERR "%s failed to load\n", __func__);
1723  goto err_uart_register_driver;
1724  }
1725 
1726  ret = platform_driver_register(&msm_serial_hs_platform_driver);
1727  if (ret) {
1728  printk(KERN_ERR "%s failed to load\n", __func__);
1729  goto err_platform_driver_register;
1730  }
1731 
1732  return ret;
1733 
1734 err_platform_driver_register:
1735  uart_unregister_driver(&msm_hs_driver);
1736 err_uart_register_driver:
1737  destroy_workqueue(msm_hs_workqueue);
1738  return ret;
1739 }
1740 module_init(msm_serial_hs_init);
1741 
1742 /*
1743  * Called by the upper layer when port is closed.
1744  * - Disables the port
1745  * - Unhook the ISR
1746  */
1747 static void msm_hs_shutdown(struct uart_port *uport)
1748 {
1749  unsigned long flags;
1750  struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1751 
1752  BUG_ON(msm_uport->rx.flush < FLUSH_STOP);
1753 
1754  spin_lock_irqsave(&uport->lock, flags);
1755  clk_enable(msm_uport->clk);
1756 
1757  /* Disable the transmitter */
1758  msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_DISABLE_BMSK);
1759  /* Disable the receiver */
1760  msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_DISABLE_BMSK);
1761 
1762  pm_runtime_disable(uport->dev);
1763  pm_runtime_set_suspended(uport->dev);
1764 
1765  /* Free the interrupt */
1766  free_irq(uport->irq, msm_uport);
1767  if (use_low_power_rx_wakeup(msm_uport))
1768  free_irq(msm_uport->rx_wakeup.irq, msm_uport);
1769 
1770  msm_uport->imr_reg = 0;
1771  msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1772 
1773  wait_event(msm_uport->rx.wait, msm_uport->rx.flush == FLUSH_SHUTDOWN);
1774 
1775  clk_disable(msm_uport->clk); /* to balance local clk_enable() */
1776  if (msm_uport->clk_state != MSM_HS_CLK_OFF)
1777  clk_disable(msm_uport->clk); /* to balance clk_state */
1778  msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
1779 
1780  dma_unmap_single(uport->dev, msm_uport->tx.dma_base,
1782 
1783  spin_unlock_irqrestore(&uport->lock, flags);
1784 
1785  if (cancel_work_sync(&msm_uport->rx.tty_work))
1786  msm_hs_tty_flip_buffer_work(&msm_uport->rx.tty_work);
1787 }
1788 
1789 static void __exit msm_serial_hs_exit(void)
1790 {
1791  flush_workqueue(msm_hs_workqueue);
1792  destroy_workqueue(msm_hs_workqueue);
1793  platform_driver_unregister(&msm_serial_hs_platform_driver);
1794  uart_unregister_driver(&msm_hs_driver);
1795 }
1796 module_exit(msm_serial_hs_exit);
1797 
1798 #ifdef CONFIG_PM_RUNTIME
1799 static int msm_hs_runtime_idle(struct device *dev)
1800 {
1801  /*
1802  * returning success from idle results in runtime suspend to be
1803  * called
1804  */
1805  return 0;
1806 }
1807 
1808 static int msm_hs_runtime_resume(struct device *dev)
1809 {
1810  struct platform_device *pdev = container_of(dev, struct
1811  platform_device, dev);
1812  struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
1813 
1814  msm_hs_request_clock_on(&msm_uport->uport);
1815  return 0;
1816 }
1817 
1818 static int msm_hs_runtime_suspend(struct device *dev)
1819 {
1820  struct platform_device *pdev = container_of(dev, struct
1821  platform_device, dev);
1822  struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
1823 
1824  msm_hs_request_clock_off(&msm_uport->uport);
1825  return 0;
1826 }
1827 #else
1828 #define msm_hs_runtime_idle NULL
1829 #define msm_hs_runtime_resume NULL
1830 #define msm_hs_runtime_suspend NULL
1831 #endif
1832 
1833 static const struct dev_pm_ops msm_hs_dev_pm_ops = {
1834  .runtime_suspend = msm_hs_runtime_suspend,
1835  .runtime_resume = msm_hs_runtime_resume,
1836  .runtime_idle = msm_hs_runtime_idle,
1837 };
1838 
1839 static struct platform_driver msm_serial_hs_platform_driver = {
1840  .probe = msm_hs_probe,
1841  .remove = __devexit_p(msm_hs_remove),
1842  .driver = {
1843  .name = "msm_serial_hs",
1844  .owner = THIS_MODULE,
1845  .pm = &msm_hs_dev_pm_ops,
1846  },
1847 };
1848 
1849 static struct uart_driver msm_hs_driver = {
1850  .owner = THIS_MODULE,
1851  .driver_name = "msm_serial_hs",
1852  .dev_name = "ttyHS",
1853  .nr = UARTDM_NR,
1854  .cons = 0,
1855 };
1856 
1857 static struct uart_ops msm_hs_ops = {
1858  .tx_empty = msm_hs_tx_empty,
1859  .set_mctrl = msm_hs_set_mctrl_locked,
1860  .get_mctrl = msm_hs_get_mctrl_locked,
1861  .stop_tx = msm_hs_stop_tx_locked,
1862  .start_tx = msm_hs_start_tx_locked,
1863  .stop_rx = msm_hs_stop_rx_locked,
1864  .enable_ms = msm_hs_enable_ms_locked,
1865  .break_ctl = msm_hs_break_ctl,
1866  .startup = msm_hs_startup,
1867  .shutdown = msm_hs_shutdown,
1868  .set_termios = msm_hs_set_termios,
1869  .pm = msm_hs_pm,
1870  .type = msm_hs_type,
1871  .config_port = msm_hs_config_port,
1872  .release_port = msm_hs_release_port,
1873  .request_port = msm_hs_request_port,
1874 };
1875 
1876 MODULE_DESCRIPTION("High Speed UART Driver for the MSM chipset");
1877 MODULE_VERSION("1.2");
1878 MODULE_LICENSE("GPL v2");