mthca_cmd.c File Reference

#include <linux/completion.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <rdma/ib_mad.h>
#include "mthca_dev.h"
#include "mthca_config_reg.h"
#include "mthca_cmd.h"
#include "mthca_memfree.h"

Go to the source code of this file.

Data Structures
struct	mthca_cmd_context

Macros
#define	CMD_POLL_TOKEN   0xffff
#define	QUERY_FW_OUT_SIZE   0x100
#define	QUERY_FW_VER_OFFSET   0x00
#define	QUERY_FW_MAX_CMD_OFFSET   0x0f
#define	QUERY_FW_ERR_START_OFFSET   0x30
#define	QUERY_FW_ERR_SIZE_OFFSET   0x38
#define	QUERY_FW_CMD_DB_EN_OFFSET   0x10
#define	QUERY_FW_CMD_DB_OFFSET   0x50
#define	QUERY_FW_CMD_DB_BASE   0x60
#define	QUERY_FW_START_OFFSET   0x20
#define	QUERY_FW_END_OFFSET   0x28
#define	QUERY_FW_SIZE_OFFSET   0x00
#define	QUERY_FW_CLR_INT_BASE_OFFSET   0x20
#define	QUERY_FW_EQ_ARM_BASE_OFFSET   0x40
#define	QUERY_FW_EQ_SET_CI_BASE_OFFSET   0x48
#define	ENABLE_LAM_OUT_SIZE   0x100
#define	ENABLE_LAM_START_OFFSET   0x00
#define	ENABLE_LAM_END_OFFSET   0x08
#define	ENABLE_LAM_INFO_OFFSET   0x13
#define	ENABLE_LAM_INFO_HIDDEN_FLAG   (1 << 4)
#define	ENABLE_LAM_INFO_ECC_MASK   0x3
#define	QUERY_DDR_OUT_SIZE   0x100
#define	QUERY_DDR_START_OFFSET   0x00
#define	QUERY_DDR_END_OFFSET   0x08
#define	QUERY_DDR_INFO_OFFSET   0x13
#define	QUERY_DDR_INFO_HIDDEN_FLAG   (1 << 4)
#define	QUERY_DDR_INFO_ECC_MASK   0x3
#define	QUERY_DEV_LIM_OUT_SIZE   0x100
#define	QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET   0x10
#define	QUERY_DEV_LIM_MAX_QP_SZ_OFFSET   0x11
#define	QUERY_DEV_LIM_RSVD_QP_OFFSET   0x12
#define	QUERY_DEV_LIM_MAX_QP_OFFSET   0x13
#define	QUERY_DEV_LIM_RSVD_SRQ_OFFSET   0x14
#define	QUERY_DEV_LIM_MAX_SRQ_OFFSET   0x15
#define	QUERY_DEV_LIM_RSVD_EEC_OFFSET   0x16
#define	QUERY_DEV_LIM_MAX_EEC_OFFSET   0x17
#define	QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET   0x19
#define	QUERY_DEV_LIM_RSVD_CQ_OFFSET   0x1a
#define	QUERY_DEV_LIM_MAX_CQ_OFFSET   0x1b
#define	QUERY_DEV_LIM_MAX_MPT_OFFSET   0x1d
#define	QUERY_DEV_LIM_RSVD_EQ_OFFSET   0x1e
#define	QUERY_DEV_LIM_MAX_EQ_OFFSET   0x1f
#define	QUERY_DEV_LIM_RSVD_MTT_OFFSET   0x20
#define	QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET   0x21
#define	QUERY_DEV_LIM_RSVD_MRW_OFFSET   0x22
#define	QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET   0x23
#define	QUERY_DEV_LIM_MAX_AV_OFFSET   0x27
#define	QUERY_DEV_LIM_MAX_REQ_QP_OFFSET   0x29
#define	QUERY_DEV_LIM_MAX_RES_QP_OFFSET   0x2b
#define	QUERY_DEV_LIM_MAX_RDMA_OFFSET   0x2f
#define	QUERY_DEV_LIM_RSZ_SRQ_OFFSET   0x33
#define	QUERY_DEV_LIM_ACK_DELAY_OFFSET   0x35
#define	QUERY_DEV_LIM_MTU_WIDTH_OFFSET   0x36
#define	QUERY_DEV_LIM_VL_PORT_OFFSET   0x37
#define	QUERY_DEV_LIM_MAX_GID_OFFSET   0x3b
#define	QUERY_DEV_LIM_RATE_SUPPORT_OFFSET   0x3c
#define	QUERY_DEV_LIM_MAX_PKEY_OFFSET   0x3f
#define	QUERY_DEV_LIM_FLAGS_OFFSET   0x44
#define	QUERY_DEV_LIM_RSVD_UAR_OFFSET   0x48
#define	QUERY_DEV_LIM_UAR_SZ_OFFSET   0x49
#define	QUERY_DEV_LIM_PAGE_SZ_OFFSET   0x4b
#define	QUERY_DEV_LIM_MAX_SG_OFFSET   0x51
#define	QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET   0x52
#define	QUERY_DEV_LIM_MAX_SG_RQ_OFFSET   0x55
#define	QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET   0x56
#define	QUERY_DEV_LIM_MAX_QP_MCG_OFFSET   0x61
#define	QUERY_DEV_LIM_RSVD_MCG_OFFSET   0x62
#define	QUERY_DEV_LIM_MAX_MCG_OFFSET   0x63
#define	QUERY_DEV_LIM_RSVD_PD_OFFSET   0x64
#define	QUERY_DEV_LIM_MAX_PD_OFFSET   0x65
#define	QUERY_DEV_LIM_RSVD_RDD_OFFSET   0x66
#define	QUERY_DEV_LIM_MAX_RDD_OFFSET   0x67
#define	QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80
#define	QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82
#define	QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET   0x84
#define	QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET   0x86
#define	QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88
#define	QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a
#define	QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c
#define	QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e
#define	QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90
#define	QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92
#define	QUERY_DEV_LIM_PBL_SZ_OFFSET   0x96
#define	QUERY_DEV_LIM_BMME_FLAGS_OFFSET   0x97
#define	QUERY_DEV_LIM_RSVD_LKEY_OFFSET   0x98
#define	QUERY_DEV_LIM_LAMR_OFFSET   0x9f
#define	QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET   0xa0
#define	VSD_OFFSET_SIG1   0x00
#define	VSD_OFFSET_SIG2   0xde
#define	VSD_OFFSET_MLX_BOARD_ID   0xd0
#define	VSD_OFFSET_TS_BOARD_ID   0x20
#define	VSD_SIGNATURE_TOPSPIN   0x5ad
#define	QUERY_ADAPTER_OUT_SIZE   0x100
#define	QUERY_ADAPTER_VENDOR_ID_OFFSET   0x00
#define	QUERY_ADAPTER_DEVICE_ID_OFFSET   0x04
#define	QUERY_ADAPTER_REVISION_ID_OFFSET   0x08
#define	QUERY_ADAPTER_INTA_PIN_OFFSET   0x10
#define	QUERY_ADAPTER_VSD_OFFSET   0x20
#define	INIT_HCA_IN_SIZE   0x200
#define	INIT_HCA_FLAGS1_OFFSET   0x00c
#define	INIT_HCA_FLAGS2_OFFSET   0x014
#define	INIT_HCA_QPC_OFFSET   0x020
#define	INIT_HCA_QPC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x10)
#define	INIT_HCA_LOG_QP_OFFSET   (INIT_HCA_QPC_OFFSET + 0x17)
#define	INIT_HCA_EEC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x20)
#define	INIT_HCA_LOG_EEC_OFFSET   (INIT_HCA_QPC_OFFSET + 0x27)
#define	INIT_HCA_SRQC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x28)
#define	INIT_HCA_LOG_SRQ_OFFSET   (INIT_HCA_QPC_OFFSET + 0x2f)
#define	INIT_HCA_CQC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x30)
#define	INIT_HCA_LOG_CQ_OFFSET   (INIT_HCA_QPC_OFFSET + 0x37)
#define	INIT_HCA_EQPC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x40)
#define	INIT_HCA_EEEC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x50)
#define	INIT_HCA_EQC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x60)
#define	INIT_HCA_LOG_EQ_OFFSET   (INIT_HCA_QPC_OFFSET + 0x67)
#define	INIT_HCA_RDB_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x70)
#define	INIT_HCA_UDAV_OFFSET   0x0b0
#define	INIT_HCA_UDAV_LKEY_OFFSET   (INIT_HCA_UDAV_OFFSET + 0x0)
#define	INIT_HCA_UDAV_PD_OFFSET   (INIT_HCA_UDAV_OFFSET + 0x4)
#define	INIT_HCA_MCAST_OFFSET   0x0c0
#define	INIT_HCA_MC_BASE_OFFSET   (INIT_HCA_MCAST_OFFSET + 0x00)
#define	INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET   (INIT_HCA_MCAST_OFFSET + 0x12)
#define	INIT_HCA_MC_HASH_SZ_OFFSET   (INIT_HCA_MCAST_OFFSET + 0x16)
#define	INIT_HCA_LOG_MC_TABLE_SZ_OFFSET   (INIT_HCA_MCAST_OFFSET + 0x1b)
#define	INIT_HCA_TPT_OFFSET   0x0f0
#define	INIT_HCA_MPT_BASE_OFFSET   (INIT_HCA_TPT_OFFSET + 0x00)
#define	INIT_HCA_MTT_SEG_SZ_OFFSET   (INIT_HCA_TPT_OFFSET + 0x09)
#define	INIT_HCA_LOG_MPT_SZ_OFFSET   (INIT_HCA_TPT_OFFSET + 0x0b)
#define	INIT_HCA_MTT_BASE_OFFSET   (INIT_HCA_TPT_OFFSET + 0x10)
#define	INIT_HCA_UAR_OFFSET   0x120
#define	INIT_HCA_UAR_BASE_OFFSET   (INIT_HCA_UAR_OFFSET + 0x00)
#define	INIT_HCA_UARC_SZ_OFFSET   (INIT_HCA_UAR_OFFSET + 0x09)
#define	INIT_HCA_LOG_UAR_SZ_OFFSET   (INIT_HCA_UAR_OFFSET + 0x0a)
#define	INIT_HCA_UAR_PAGE_SZ_OFFSET   (INIT_HCA_UAR_OFFSET + 0x0b)
#define	INIT_HCA_UAR_SCATCH_BASE_OFFSET   (INIT_HCA_UAR_OFFSET + 0x10)
#define	INIT_HCA_UAR_CTX_BASE_OFFSET   (INIT_HCA_UAR_OFFSET + 0x18)
#define	INIT_IB_IN_SIZE   56
#define	INIT_IB_FLAGS_OFFSET   0x00
#define	INIT_IB_FLAG_SIG   (1 << 18)
#define	INIT_IB_FLAG_NG   (1 << 17)
#define	INIT_IB_FLAG_G0   (1 << 16)
#define	INIT_IB_VL_SHIFT   4
#define	INIT_IB_PORT_WIDTH_SHIFT   8
#define	INIT_IB_MTU_SHIFT   12
#define	INIT_IB_MAX_GID_OFFSET   0x06
#define	INIT_IB_MAX_PKEY_OFFSET   0x0a
#define	INIT_IB_GUID0_OFFSET   0x10
#define	INIT_IB_NODE_GUID_OFFSET   0x18
#define	INIT_IB_SI_GUID_OFFSET   0x20
#define	SET_IB_IN_SIZE   0x40
#define	SET_IB_FLAGS_OFFSET   0x00
#define	SET_IB_FLAG_SIG   (1 << 18)
#define	SET_IB_FLAG_RQK   (1 << 0)
#define	SET_IB_CAP_MASK_OFFSET   0x04
#define	SET_IB_SI_GUID_OFFSET   0x08
#define	RESIZE_CQ_IN_SIZE   0x40
#define	RESIZE_CQ_LOG_SIZE_OFFSET   0x0c
#define	RESIZE_CQ_LKEY_OFFSET   0x1c
#define	MAD_IFC_BOX_SIZE   0x400
#define	MAD_IFC_MY_QPN_OFFSET   0x100
#define	MAD_IFC_RQPN_OFFSET   0x108
#define	MAD_IFC_SL_OFFSET   0x10c
#define	MAD_IFC_G_PATH_OFFSET   0x10d
#define	MAD_IFC_RLID_OFFSET   0x10e
#define	MAD_IFC_PKEY_OFFSET   0x112
#define	MAD_IFC_GRH_OFFSET   0x140

Enumerations
enum	{   HCR_IN_PARAM_OFFSET = 0x00, HCR_IN_MODIFIER_OFFSET = 0x08, HCR_OUT_PARAM_OFFSET = 0x0c, HCR_TOKEN_OFFSET = 0x14,   HCR_STATUS_OFFSET = 0x18, HCR_OPMOD_SHIFT = 12, HCA_E_BIT = 22, HCR_GO_BIT = 23 }
enum	{   CMD_SYS_EN = 0x1, CMD_SYS_DIS = 0x2, CMD_MAP_FA = 0xfff, CMD_UNMAP_FA = 0xffe,   CMD_RUN_FW = 0xff6, CMD_MOD_STAT_CFG = 0x34, CMD_QUERY_DEV_LIM = 0x3, CMD_QUERY_FW = 0x4,   CMD_ENABLE_LAM = 0xff8, CMD_DISABLE_LAM = 0xff7, CMD_QUERY_DDR = 0x5, CMD_QUERY_ADAPTER = 0x6,   CMD_INIT_HCA = 0x7, CMD_CLOSE_HCA = 0x8, CMD_INIT_IB = 0x9, CMD_CLOSE_IB = 0xa,   CMD_QUERY_HCA = 0xb, CMD_SET_IB = 0xc, CMD_ACCESS_DDR = 0x2e, CMD_MAP_ICM = 0xffa,   CMD_UNMAP_ICM = 0xff9, CMD_MAP_ICM_AUX = 0xffc, CMD_UNMAP_ICM_AUX = 0xffb, CMD_SET_ICM_SIZE = 0xffd,   CMD_SW2HW_MPT = 0xd, CMD_QUERY_MPT = 0xe, CMD_HW2SW_MPT = 0xf, CMD_READ_MTT = 0x10,   CMD_WRITE_MTT = 0x11, CMD_SYNC_TPT = 0x2f, CMD_MAP_EQ = 0x12, CMD_SW2HW_EQ = 0x13,   CMD_HW2SW_EQ = 0x14, CMD_QUERY_EQ = 0x15, CMD_SW2HW_CQ = 0x16, CMD_HW2SW_CQ = 0x17,   CMD_QUERY_CQ = 0x18, CMD_RESIZE_CQ = 0x2c, CMD_SW2HW_SRQ = 0x35, CMD_HW2SW_SRQ = 0x36,   CMD_QUERY_SRQ = 0x37, CMD_ARM_SRQ = 0x40, CMD_RST2INIT_QPEE = 0x19, CMD_INIT2RTR_QPEE = 0x1a,   CMD_RTR2RTS_QPEE = 0x1b, CMD_RTS2RTS_QPEE = 0x1c, CMD_SQERR2RTS_QPEE = 0x1d, CMD_2ERR_QPEE = 0x1e,   CMD_RTS2SQD_QPEE = 0x1f, CMD_SQD2SQD_QPEE = 0x38, CMD_SQD2RTS_QPEE = 0x20, CMD_ERR2RST_QPEE = 0x21,   CMD_QUERY_QPEE = 0x22, CMD_INIT2INIT_QPEE = 0x2d, CMD_SUSPEND_QPEE = 0x32, CMD_UNSUSPEND_QPEE = 0x33,   CMD_CONF_SPECIAL_QP = 0x23, CMD_MAD_IFC = 0x24, CMD_READ_MGM = 0x25, CMD_WRITE_MGM = 0x26,   CMD_MGID_HASH = 0x27, CMD_DIAG_RPRT = 0x30, CMD_NOP = 0x31, CMD_QUERY_DEBUG_MSG = 0x2a,   CMD_SET_DEBUG_MSG = 0x2b }
enum	{ CMD_TIME_CLASS_A = 60 * HZ, CMD_TIME_CLASS_B = 60 * HZ, CMD_TIME_CLASS_C = 60 * HZ, CMD_TIME_CLASS_D = 60 * HZ }
enum	{ GO_BIT_TIMEOUT = HZ * 10 }

Functions
	module_param (fw_cmd_doorbell, int, 0644)
	MODULE_PARM_DESC (fw_cmd_doorbell,"post FW commands through doorbell page if nonzero ""(and supported by FW)")
void	mthca_cmd_event (struct mthca_dev *dev, u16 token, u8 status, u64 out_param)
int	mthca_cmd_init (struct mthca_dev *dev)
void	mthca_cmd_cleanup (struct mthca_dev *dev)
int	mthca_cmd_use_events (struct mthca_dev *dev)
void	mthca_cmd_use_polling (struct mthca_dev *dev)
struct mthca_mailbox *	mthca_alloc_mailbox (struct mthca_dev *dev, gfp_t gfp_mask)
void	mthca_free_mailbox (struct mthca_dev *dev, struct mthca_mailbox *mailbox)
int	mthca_SYS_EN (struct mthca_dev *dev)
int	mthca_SYS_DIS (struct mthca_dev *dev)
int	mthca_MAP_FA (struct mthca_dev *dev, struct mthca_icm *icm)
int	mthca_UNMAP_FA (struct mthca_dev *dev)
int	mthca_RUN_FW (struct mthca_dev *dev)
int	mthca_QUERY_FW (struct mthca_dev *dev)
int	mthca_ENABLE_LAM (struct mthca_dev *dev)
int	mthca_DISABLE_LAM (struct mthca_dev *dev)
int	mthca_QUERY_DDR (struct mthca_dev *dev)
int	mthca_QUERY_DEV_LIM (struct mthca_dev *dev, struct mthca_dev_lim *dev_lim)
int	mthca_QUERY_ADAPTER (struct mthca_dev *dev, struct mthca_adapter *adapter)
int	mthca_INIT_HCA (struct mthca_dev *dev, struct mthca_init_hca_param *param)
int	mthca_INIT_IB (struct mthca_dev *dev, struct mthca_init_ib_param *param, int port)
int	mthca_CLOSE_IB (struct mthca_dev *dev, int port)
int	mthca_CLOSE_HCA (struct mthca_dev *dev, int panic)
int	mthca_SET_IB (struct mthca_dev *dev, struct mthca_set_ib_param *param, int port)
int	mthca_MAP_ICM (struct mthca_dev *dev, struct mthca_icm *icm, u64 virt)
int	mthca_MAP_ICM_page (struct mthca_dev *dev, u64 dma_addr, u64 virt)
int	mthca_UNMAP_ICM (struct mthca_dev *dev, u64 virt, u32 page_count)
int	mthca_MAP_ICM_AUX (struct mthca_dev *dev, struct mthca_icm *icm)
int	mthca_UNMAP_ICM_AUX (struct mthca_dev *dev)
int	mthca_SET_ICM_SIZE (struct mthca_dev *dev, u64 icm_size, u64 *aux_pages)
int	mthca_SW2HW_MPT (struct mthca_dev *dev, struct mthca_mailbox *mailbox, int mpt_index)
int	mthca_HW2SW_MPT (struct mthca_dev *dev, struct mthca_mailbox *mailbox, int mpt_index)
int	mthca_WRITE_MTT (struct mthca_dev *dev, struct mthca_mailbox *mailbox, int num_mtt)
int	mthca_SYNC_TPT (struct mthca_dev *dev)
int	mthca_MAP_EQ (struct mthca_dev *dev, u64 event_mask, int unmap, int eq_num)
int	mthca_SW2HW_EQ (struct mthca_dev *dev, struct mthca_mailbox *mailbox, int eq_num)
int	mthca_HW2SW_EQ (struct mthca_dev *dev, struct mthca_mailbox *mailbox, int eq_num)
int	mthca_SW2HW_CQ (struct mthca_dev *dev, struct mthca_mailbox *mailbox, int cq_num)
int	mthca_HW2SW_CQ (struct mthca_dev *dev, struct mthca_mailbox *mailbox, int cq_num)
int	mthca_RESIZE_CQ (struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size)
int	mthca_SW2HW_SRQ (struct mthca_dev *dev, struct mthca_mailbox *mailbox, int srq_num)
int	mthca_HW2SW_SRQ (struct mthca_dev *dev, struct mthca_mailbox *mailbox, int srq_num)
int	mthca_QUERY_SRQ (struct mthca_dev *dev, u32 num, struct mthca_mailbox *mailbox)
int	mthca_ARM_SRQ (struct mthca_dev *dev, int srq_num, int limit)
int	mthca_MODIFY_QP (struct mthca_dev *dev, enum ib_qp_state cur, enum ib_qp_state next, u32 num, int is_ee, struct mthca_mailbox *mailbox, u32 optmask)
int	mthca_QUERY_QP (struct mthca_dev *dev, u32 num, int is_ee, struct mthca_mailbox *mailbox)
int	mthca_CONF_SPECIAL_QP (struct mthca_dev *dev, int type, u32 qpn)
int	mthca_MAD_IFC (struct mthca_dev *dev, int ignore_mkey, int ignore_bkey, int port, struct ib_wc *in_wc, struct ib_grh *in_grh, void *in_mad, void *response_mad)
int	mthca_READ_MGM (struct mthca_dev *dev, int index, struct mthca_mailbox *mailbox)
int	mthca_WRITE_MGM (struct mthca_dev *dev, int index, struct mthca_mailbox *mailbox)
int	mthca_MGID_HASH (struct mthca_dev *dev, struct mthca_mailbox *mailbox, u16 *hash)
int	mthca_NOP (struct mthca_dev *dev)

Macro Definition Documentation

#define CMD_POLL_TOKEN   0xffff

Definition at line 49 of file mthca_cmd.c.

#define ENABLE_LAM_END_OFFSET   0x08

#define ENABLE_LAM_INFO_ECC_MASK   0x3

#define ENABLE_LAM_INFO_HIDDEN_FLAG   (1 << 4)

#define ENABLE_LAM_INFO_OFFSET   0x13

#define ENABLE_LAM_OUT_SIZE   0x100

#define ENABLE_LAM_START_OFFSET   0x00

#define INIT_HCA_CQC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x30)

#define INIT_HCA_EEC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x20)

#define INIT_HCA_EEEC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x50)

#define INIT_HCA_EQC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x60)

#define INIT_HCA_EQPC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x40)

#define INIT_HCA_FLAGS1_OFFSET   0x00c

#define INIT_HCA_FLAGS2_OFFSET   0x014

#define INIT_HCA_IN_SIZE   0x200

#define INIT_HCA_LOG_CQ_OFFSET   (INIT_HCA_QPC_OFFSET + 0x37)

#define INIT_HCA_LOG_EEC_OFFSET   (INIT_HCA_QPC_OFFSET + 0x27)

#define INIT_HCA_LOG_EQ_OFFSET   (INIT_HCA_QPC_OFFSET + 0x67)

#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET   (INIT_HCA_MCAST_OFFSET + 0x12)

#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET   (INIT_HCA_MCAST_OFFSET + 0x1b)

#define INIT_HCA_LOG_MPT_SZ_OFFSET   (INIT_HCA_TPT_OFFSET + 0x0b)

#define INIT_HCA_LOG_QP_OFFSET   (INIT_HCA_QPC_OFFSET + 0x17)

#define INIT_HCA_LOG_SRQ_OFFSET   (INIT_HCA_QPC_OFFSET + 0x2f)

#define INIT_HCA_LOG_UAR_SZ_OFFSET   (INIT_HCA_UAR_OFFSET + 0x0a)

#define INIT_HCA_MC_BASE_OFFSET   (INIT_HCA_MCAST_OFFSET + 0x00)

#define INIT_HCA_MC_HASH_SZ_OFFSET   (INIT_HCA_MCAST_OFFSET + 0x16)

#define INIT_HCA_MCAST_OFFSET   0x0c0

#define INIT_HCA_MPT_BASE_OFFSET   (INIT_HCA_TPT_OFFSET + 0x00)

#define INIT_HCA_MTT_BASE_OFFSET   (INIT_HCA_TPT_OFFSET + 0x10)

#define INIT_HCA_MTT_SEG_SZ_OFFSET   (INIT_HCA_TPT_OFFSET + 0x09)

#define INIT_HCA_QPC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x10)

#define INIT_HCA_QPC_OFFSET   0x020

#define INIT_HCA_RDB_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x70)

#define INIT_HCA_SRQC_BASE_OFFSET   (INIT_HCA_QPC_OFFSET + 0x28)

#define INIT_HCA_TPT_OFFSET   0x0f0

#define INIT_HCA_UAR_BASE_OFFSET   (INIT_HCA_UAR_OFFSET + 0x00)

#define INIT_HCA_UAR_CTX_BASE_OFFSET   (INIT_HCA_UAR_OFFSET + 0x18)

#define INIT_HCA_UAR_OFFSET   0x120

#define INIT_HCA_UAR_PAGE_SZ_OFFSET   (INIT_HCA_UAR_OFFSET + 0x0b)

#define INIT_HCA_UAR_SCATCH_BASE_OFFSET   (INIT_HCA_UAR_OFFSET + 0x10)

#define INIT_HCA_UARC_SZ_OFFSET   (INIT_HCA_UAR_OFFSET + 0x09)

#define INIT_HCA_UDAV_LKEY_OFFSET   (INIT_HCA_UDAV_OFFSET + 0x0)

#define INIT_HCA_UDAV_OFFSET   0x0b0

#define INIT_HCA_UDAV_PD_OFFSET   (INIT_HCA_UDAV_OFFSET + 0x4)

#define INIT_IB_FLAG_G0   (1 << 16)

#define INIT_IB_FLAG_NG   (1 << 17)

#define INIT_IB_FLAG_SIG   (1 << 18)

#define INIT_IB_FLAGS_OFFSET   0x00

#define INIT_IB_GUID0_OFFSET   0x10

#define INIT_IB_IN_SIZE   56

#define INIT_IB_MAX_GID_OFFSET   0x06

#define INIT_IB_MAX_PKEY_OFFSET   0x0a

#define INIT_IB_MTU_SHIFT   12

#define INIT_IB_NODE_GUID_OFFSET   0x18

#define INIT_IB_PORT_WIDTH_SHIFT   8

#define INIT_IB_SI_GUID_OFFSET   0x20

#define INIT_IB_VL_SHIFT   4

#define MAD_IFC_BOX_SIZE   0x400

#define MAD_IFC_G_PATH_OFFSET   0x10d

#define MAD_IFC_GRH_OFFSET   0x140

#define MAD_IFC_MY_QPN_OFFSET   0x100

#define MAD_IFC_PKEY_OFFSET   0x112

#define MAD_IFC_RLID_OFFSET   0x10e

#define MAD_IFC_RQPN_OFFSET   0x108

#define MAD_IFC_SL_OFFSET   0x10c

#define QUERY_ADAPTER_DEVICE_ID_OFFSET   0x04

#define QUERY_ADAPTER_INTA_PIN_OFFSET   0x10

#define QUERY_ADAPTER_OUT_SIZE   0x100

#define QUERY_ADAPTER_REVISION_ID_OFFSET   0x08

#define QUERY_ADAPTER_VENDOR_ID_OFFSET   0x00

#define QUERY_ADAPTER_VSD_OFFSET   0x20

#define QUERY_DDR_END_OFFSET   0x08

#define QUERY_DDR_INFO_ECC_MASK   0x3

#define QUERY_DDR_INFO_HIDDEN_FLAG   (1 << 4)

#define QUERY_DDR_INFO_OFFSET   0x13

#define QUERY_DDR_OUT_SIZE   0x100

#define QUERY_DDR_START_OFFSET   0x00

#define QUERY_DEV_LIM_ACK_DELAY_OFFSET   0x35

#define QUERY_DEV_LIM_BMME_FLAGS_OFFSET   0x97

#define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a

#define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80

#define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET   0x84

#define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88

#define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET   0x86

#define QUERY_DEV_LIM_FLAGS_OFFSET   0x44

#define QUERY_DEV_LIM_LAMR_OFFSET   0x9f

#define QUERY_DEV_LIM_MAX_AV_OFFSET   0x27

#define QUERY_DEV_LIM_MAX_CQ_OFFSET   0x1b

#define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET   0x19

#define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET   0x52

#define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET   0x56

#define QUERY_DEV_LIM_MAX_EEC_OFFSET   0x17

#define QUERY_DEV_LIM_MAX_EQ_OFFSET   0x1f

#define QUERY_DEV_LIM_MAX_GID_OFFSET   0x3b

#define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET   0xa0

#define QUERY_DEV_LIM_MAX_MCG_OFFSET   0x63

#define QUERY_DEV_LIM_MAX_MPT_OFFSET   0x1d

#define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET   0x21

#define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET   0x23

#define QUERY_DEV_LIM_MAX_PD_OFFSET   0x65

#define QUERY_DEV_LIM_MAX_PKEY_OFFSET   0x3f

#define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET   0x61

#define QUERY_DEV_LIM_MAX_QP_OFFSET   0x13

#define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET   0x11

#define QUERY_DEV_LIM_MAX_RDD_OFFSET   0x67

#define QUERY_DEV_LIM_MAX_RDMA_OFFSET   0x2f

#define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET   0x29

#define QUERY_DEV_LIM_MAX_RES_QP_OFFSET   0x2b

#define QUERY_DEV_LIM_MAX_SG_OFFSET   0x51

#define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET   0x55

#define QUERY_DEV_LIM_MAX_SRQ_OFFSET   0x15

#define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET   0x10

#define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92

#define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90

#define QUERY_DEV_LIM_MTU_WIDTH_OFFSET   0x36

#define QUERY_DEV_LIM_OUT_SIZE   0x100

#define QUERY_DEV_LIM_PAGE_SZ_OFFSET   0x4b

#define QUERY_DEV_LIM_PBL_SZ_OFFSET   0x96

#define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82

#define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET   0x3c

#define QUERY_DEV_LIM_RSVD_CQ_OFFSET   0x1a

#define QUERY_DEV_LIM_RSVD_EEC_OFFSET   0x16

#define QUERY_DEV_LIM_RSVD_EQ_OFFSET   0x1e

#define QUERY_DEV_LIM_RSVD_LKEY_OFFSET   0x98

#define QUERY_DEV_LIM_RSVD_MCG_OFFSET   0x62

#define QUERY_DEV_LIM_RSVD_MRW_OFFSET   0x22

#define QUERY_DEV_LIM_RSVD_MTT_OFFSET   0x20

#define QUERY_DEV_LIM_RSVD_PD_OFFSET   0x64

#define QUERY_DEV_LIM_RSVD_QP_OFFSET   0x12

#define QUERY_DEV_LIM_RSVD_RDD_OFFSET   0x66

#define QUERY_DEV_LIM_RSVD_SRQ_OFFSET   0x14

#define QUERY_DEV_LIM_RSVD_UAR_OFFSET   0x48

#define QUERY_DEV_LIM_RSZ_SRQ_OFFSET   0x33

#define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c

#define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e

#define QUERY_DEV_LIM_UAR_SZ_OFFSET   0x49

#define QUERY_DEV_LIM_VL_PORT_OFFSET   0x37

#define QUERY_FW_CLR_INT_BASE_OFFSET   0x20

#define QUERY_FW_CMD_DB_BASE   0x60

#define QUERY_FW_CMD_DB_EN_OFFSET   0x10

#define QUERY_FW_CMD_DB_OFFSET   0x50

#define QUERY_FW_END_OFFSET   0x28

#define QUERY_FW_EQ_ARM_BASE_OFFSET   0x40

#define QUERY_FW_EQ_SET_CI_BASE_OFFSET   0x48

#define QUERY_FW_ERR_SIZE_OFFSET   0x38

#define QUERY_FW_ERR_START_OFFSET   0x30

#define QUERY_FW_MAX_CMD_OFFSET   0x0f

#define QUERY_FW_OUT_SIZE   0x100

#define QUERY_FW_SIZE_OFFSET   0x00

#define QUERY_FW_START_OFFSET   0x20

#define QUERY_FW_VER_OFFSET   0x00

#define RESIZE_CQ_IN_SIZE   0x40

#define RESIZE_CQ_LKEY_OFFSET   0x1c

#define RESIZE_CQ_LOG_SIZE_OFFSET   0x0c

#define SET_IB_CAP_MASK_OFFSET   0x04

#define SET_IB_FLAG_RQK   (1 << 0)

#define SET_IB_FLAG_SIG   (1 << 18)

#define SET_IB_FLAGS_OFFSET   0x00

#define SET_IB_IN_SIZE   0x40

#define SET_IB_SI_GUID_OFFSET   0x08

#define VSD_OFFSET_MLX_BOARD_ID   0xd0

#define VSD_OFFSET_SIG1   0x00

#define VSD_OFFSET_SIG2   0xde

#define VSD_OFFSET_TS_BOARD_ID   0x20

#define VSD_SIGNATURE_TOPSPIN   0x5ad

Enumeration Type Documentation

anonymous enum

Enumerator:

HCR_IN_PARAM_OFFSET
HCR_IN_MODIFIER_OFFSET
HCR_OUT_PARAM_OFFSET
HCR_TOKEN_OFFSET
HCR_STATUS_OFFSET
HCR_OPMOD_SHIFT
HCA_E_BIT
HCR_GO_BIT

Definition at line 51 of file mthca_cmd.c.

anonymous enum

Enumerator:

CMD_SYS_EN
CMD_SYS_DIS
CMD_MAP_FA
CMD_UNMAP_FA
CMD_RUN_FW
CMD_MOD_STAT_CFG
CMD_QUERY_DEV_LIM
CMD_QUERY_FW
CMD_ENABLE_LAM
CMD_DISABLE_LAM
CMD_QUERY_DDR
CMD_QUERY_ADAPTER
CMD_INIT_HCA
CMD_CLOSE_HCA
CMD_INIT_IB
CMD_CLOSE_IB
CMD_QUERY_HCA
CMD_SET_IB
CMD_ACCESS_DDR
CMD_MAP_ICM
CMD_UNMAP_ICM
CMD_MAP_ICM_AUX
CMD_UNMAP_ICM_AUX
CMD_SET_ICM_SIZE
CMD_SW2HW_MPT
CMD_QUERY_MPT
CMD_HW2SW_MPT
CMD_READ_MTT
CMD_WRITE_MTT
CMD_SYNC_TPT
CMD_MAP_EQ
CMD_SW2HW_EQ
CMD_HW2SW_EQ
CMD_QUERY_EQ
CMD_SW2HW_CQ
CMD_HW2SW_CQ
CMD_QUERY_CQ
CMD_RESIZE_CQ
CMD_SW2HW_SRQ
CMD_HW2SW_SRQ
CMD_QUERY_SRQ
CMD_ARM_SRQ
CMD_RST2INIT_QPEE
CMD_INIT2RTR_QPEE
CMD_RTR2RTS_QPEE
CMD_RTS2RTS_QPEE
CMD_SQERR2RTS_QPEE
CMD_2ERR_QPEE
CMD_RTS2SQD_QPEE
CMD_SQD2SQD_QPEE
CMD_SQD2RTS_QPEE
CMD_ERR2RST_QPEE
CMD_QUERY_QPEE
CMD_INIT2INIT_QPEE
CMD_SUSPEND_QPEE
CMD_UNSUSPEND_QPEE
CMD_CONF_SPECIAL_QP
CMD_MAD_IFC
CMD_READ_MGM
CMD_WRITE_MGM
CMD_MGID_HASH
CMD_DIAG_RPRT
CMD_NOP
CMD_QUERY_DEBUG_MSG
CMD_SET_DEBUG_MSG

Definition at line 63 of file mthca_cmd.c.

anonymous enum

Enumerator:

CMD_TIME_CLASS_A
CMD_TIME_CLASS_B
CMD_TIME_CLASS_C
CMD_TIME_CLASS_D

Definition at line 166 of file mthca_cmd.c.

anonymous enum

Enumerator:

GO_BIT_TIMEOUT

Definition at line 174 of file mthca_cmd.c.

Function Documentation

module_param	(	fw_cmd_doorbell	,
		int	,
		0644
	)

MODULE_PARM_DESC	(	fw_cmd_doorbell	,
		"post FW commands through doorbell page if nonzero ""(and supported by FW)"
	)

struct mthca_mailbox* mthca_alloc_mailbox ( struct mthca_dev *  dev, gfp_t  gfp_mask  )

read

Definition at line 607 of file mthca_cmd.c.

int mthca_ARM_SRQ	(	struct mthca_dev *	dev,
		int	srq_num,
		int	limit
	)

Definition at line 1719 of file mthca_cmd.c.

int mthca_CLOSE_HCA	(	struct mthca_dev *	dev,
		int	panic
	)

Definition at line 1491 of file mthca_cmd.c.

int mthca_CLOSE_IB	(	struct mthca_dev *	dev,
		int	port
	)

Definition at line 1486 of file mthca_cmd.c.

void mthca_cmd_cleanup

(

struct mthca_dev *

dev

)

Definition at line 544 of file mthca_cmd.c.

void mthca_cmd_event	(	struct mthca_dev *	dev,
		u16	token,
		u8	status,
		u64	out_param
	)

Definition at line 389 of file mthca_cmd.c.

int mthca_cmd_init

(

struct mthca_dev *

dev

)

Definition at line 520 of file mthca_cmd.c.

int mthca_cmd_use_events

(

struct mthca_dev *

dev

)

Definition at line 556 of file mthca_cmd.c.

void mthca_cmd_use_polling

(

struct mthca_dev *

dev

)

Definition at line 593 of file mthca_cmd.c.

int mthca_CONF_SPECIAL_QP	(	struct mthca_dev *	dev,
		int	type,
		u32	qpn
	)

Definition at line 1835 of file mthca_cmd.c.

int mthca_DISABLE_LAM

(

struct mthca_dev *

dev

)

Definition at line 931 of file mthca_cmd.c.

int mthca_ENABLE_LAM

(

struct mthca_dev *

dev

)

Definition at line 881 of file mthca_cmd.c.

void mthca_free_mailbox	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox
	)

Definition at line 625 of file mthca_cmd.c.

int mthca_HW2SW_CQ	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		int	cq_num
	)

Definition at line 1659 of file mthca_cmd.c.

int mthca_HW2SW_EQ	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		int	eq_num
	)

Definition at line 1644 of file mthca_cmd.c.

int mthca_HW2SW_MPT	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		int	mpt_index
	)

Definition at line 1607 of file mthca_cmd.c.

int mthca_HW2SW_SRQ	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		int	srq_num
	)

Definition at line 1704 of file mthca_cmd.c.

int mthca_INIT_HCA	(	struct mthca_dev *	dev,
		struct mthca_init_hca_param *	param
	)

Definition at line 1309 of file mthca_cmd.c.

int mthca_INIT_IB	(	struct mthca_dev *	dev,
		struct mthca_init_ib_param *	param,
		int	port
	)

Definition at line 1434 of file mthca_cmd.c.

int mthca_MAD_IFC	(	struct mthca_dev *	dev,
		int	ignore_mkey,
		int	ignore_bkey,
		int	port,
		struct ib_wc *	in_wc,
		struct ib_grh *	in_grh,
		void *	in_mad,
		void *	response_mad
	)

Definition at line 1860 of file mthca_cmd.c.

int mthca_MAP_EQ	(	struct mthca_dev *	dev,
		u64	event_mask,
		int	unmap,
		int	eq_num
	)

Definition at line 1627 of file mthca_cmd.c.

int mthca_MAP_FA	(	struct mthca_dev *	dev,
		struct mthca_icm *	icm
	)

Definition at line 734 of file mthca_cmd.c.

int mthca_MAP_ICM	(	struct mthca_dev *	dev,
		struct mthca_icm *	icm,
		u64	virt
	)

Definition at line 1532 of file mthca_cmd.c.

int mthca_MAP_ICM_AUX	(	struct mthca_dev *	dev,
		struct mthca_icm *	icm
	)

Definition at line 1572 of file mthca_cmd.c.

int mthca_MAP_ICM_page	(	struct mthca_dev *	dev,
		u64	dma_addr,
		u64	virt
	)

Definition at line 1537 of file mthca_cmd.c.

int mthca_MGID_HASH	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		u16 *	hash
	)

Definition at line 1953 of file mthca_cmd.c.

int mthca_MODIFY_QP	(	struct mthca_dev *	dev,
		enum ib_qp_state	cur,
		enum ib_qp_state	next,
		u32	num,
		int	is_ee,
		struct mthca_mailbox *	mailbox,
		u32	optmask
	)

Definition at line 1725 of file mthca_cmd.c.

int mthca_NOP

(

struct mthca_dev *

dev

)

Definition at line 1966 of file mthca_cmd.c.

int mthca_QUERY_ADAPTER	(	struct mthca_dev *	dev,
		struct mthca_adapter *	adapter
	)

Definition at line 1266 of file mthca_cmd.c.

int mthca_QUERY_DDR

(

struct mthca_dev *

dev

)

Definition at line 936 of file mthca_cmd.c.

int mthca_QUERY_DEV_LIM	(	struct mthca_dev *	dev,
		struct mthca_dev_lim *	dev_lim
	)

Definition at line 986 of file mthca_cmd.c.

int mthca_QUERY_FW

(

struct mthca_dev *

dev

)

Definition at line 775 of file mthca_cmd.c.

int mthca_QUERY_QP	(	struct mthca_dev *	dev,
		u32	num,
		int	is_ee,
		struct mthca_mailbox *	mailbox
	)

Definition at line 1828 of file mthca_cmd.c.

int mthca_QUERY_SRQ	(	struct mthca_dev *	dev,
		u32	num,
		struct mthca_mailbox *	mailbox
	)

Definition at line 1712 of file mthca_cmd.c.

int mthca_READ_MGM	(	struct mthca_dev *	dev,
		int	index,
		struct mthca_mailbox *	mailbox
	)

Definition at line 1939 of file mthca_cmd.c.

int mthca_RESIZE_CQ	(	struct mthca_dev *	dev,
		int	cq_num,
		u32	lkey,
		u8	log_size
	)

Definition at line 1667 of file mthca_cmd.c.

int mthca_RUN_FW

(

struct mthca_dev *

dev

)

Definition at line 744 of file mthca_cmd.c.

int mthca_SET_IB	(	struct mthca_dev *	dev,
		struct mthca_set_ib_param *	param,
		int	port
	)

Definition at line 1496 of file mthca_cmd.c.

int mthca_SET_ICM_SIZE	(	struct mthca_dev *	dev,
		u64	icm_size,
		u64 *	aux_pages
	)

Definition at line 1582 of file mthca_cmd.c.

int mthca_SW2HW_CQ	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		int	cq_num
	)

Definition at line 1652 of file mthca_cmd.c.

int mthca_SW2HW_EQ	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		int	eq_num
	)

Definition at line 1637 of file mthca_cmd.c.

int mthca_SW2HW_MPT	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		int	mpt_index
	)

Definition at line 1600 of file mthca_cmd.c.

int mthca_SW2HW_SRQ	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		int	srq_num
	)

Definition at line 1697 of file mthca_cmd.c.

int mthca_SYNC_TPT

(

struct mthca_dev *

dev

)

Definition at line 1622 of file mthca_cmd.c.

int mthca_SYS_DIS

(

struct mthca_dev *

dev

)

Definition at line 650 of file mthca_cmd.c.

int mthca_SYS_EN

(

struct mthca_dev *

dev

)

Definition at line 634 of file mthca_cmd.c.

int mthca_UNMAP_FA

(

struct mthca_dev *

dev

)

Definition at line 739 of file mthca_cmd.c.

int mthca_UNMAP_ICM	(	struct mthca_dev *	dev,
		u64	virt,
		u32	page_count
	)

Definition at line 1563 of file mthca_cmd.c.

int mthca_UNMAP_ICM_AUX

(

struct mthca_dev *

dev

)

Definition at line 1577 of file mthca_cmd.c.

int mthca_WRITE_MGM	(	struct mthca_dev *	dev,
		int	index,
		struct mthca_mailbox *	mailbox
	)

Definition at line 1946 of file mthca_cmd.c.

int mthca_WRITE_MTT	(	struct mthca_dev *	dev,
		struct mthca_mailbox *	mailbox,
		int	num_mtt
	)

Definition at line 1615 of file mthca_cmd.c.