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phy.c
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1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2012 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <[email protected]>
24  e1000-devel Mailing List <[email protected]>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #include "e1000.h"
30 
31 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
32 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
33 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
34 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
35 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
36 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
37  u16 *data, bool read, bool page_set);
38 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
39 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
40  u16 *data, bool read);
41 
42 /* Cable length tables */
43 static const u16 e1000_m88_cable_length_table[] = {
44  0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
45 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
46  ARRAY_SIZE(e1000_m88_cable_length_table)
47 
48 static const u16 e1000_igp_2_cable_length_table[] = {
49  0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
50  6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
51  26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
52  44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
53  66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
54  87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
55  100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
56  124};
57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58  ARRAY_SIZE(e1000_igp_2_cable_length_table)
59 
60 #define BM_PHY_REG_PAGE(offset) \
61  ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
62 #define BM_PHY_REG_NUM(offset) \
63  ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
64  (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
65  ~MAX_PHY_REG_ADDRESS)))
66 
67 #define HV_INTC_FC_PAGE_START 768
68 #define I82578_ADDR_REG 29
69 #define I82577_ADDR_REG 16
70 #define I82577_CFG_REG 22
71 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73 #define I82577_CTRL_REG 23
74 
75 /* 82577 specific PHY registers */
76 #define I82577_PHY_CTRL_2 18
77 #define I82577_PHY_STATUS_2 26
78 #define I82577_PHY_DIAG_STATUS 31
79 
80 /* I82577 PHY Status 2 */
81 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
82 #define I82577_PHY_STATUS2_MDIX 0x0800
83 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
84 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
85 
86 /* I82577 PHY Control 2 */
87 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
88 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
89 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
90 
91 /* I82577 PHY Diagnostics Status */
92 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
93 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
94 
95 /* BM PHY Copper Specific Control 1 */
96 #define BM_CS_CTRL1 16
97 
98 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
99 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
100 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
101 
110 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
111 {
112  u32 manc;
113 
114  manc = er32(MANC);
115 
116  return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
117  E1000_BLK_PHY_RESET : 0;
118 }
119 
127 s32 e1000e_get_phy_id(struct e1000_hw *hw)
128 {
129  struct e1000_phy_info *phy = &hw->phy;
130  s32 ret_val = 0;
131  u16 phy_id;
132  u16 retry_count = 0;
133 
134  if (!phy->ops.read_reg)
135  return 0;
136 
137  while (retry_count < 2) {
138  ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
139  if (ret_val)
140  return ret_val;
141 
142  phy->id = (u32)(phy_id << 16);
143  udelay(20);
144  ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
145  if (ret_val)
146  return ret_val;
147 
148  phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
149  phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
150 
151  if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
152  return 0;
153 
154  retry_count++;
155  }
156 
157  return 0;
158 }
159 
166 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
167 {
168  s32 ret_val;
169 
170  ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
171  if (ret_val)
172  return ret_val;
173 
174  return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
175 }
176 
186 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
187 {
188  struct e1000_phy_info *phy = &hw->phy;
189  u32 i, mdic = 0;
190 
191  if (offset > MAX_PHY_REG_ADDRESS) {
192  e_dbg("PHY Address %d is out of range\n", offset);
193  return -E1000_ERR_PARAM;
194  }
195 
196  /*
197  * Set up Op-code, Phy Address, and register offset in the MDI
198  * Control register. The MAC will take care of interfacing with the
199  * PHY to retrieve the desired data.
200  */
201  mdic = ((offset << E1000_MDIC_REG_SHIFT) |
202  (phy->addr << E1000_MDIC_PHY_SHIFT) |
203  (E1000_MDIC_OP_READ));
204 
205  ew32(MDIC, mdic);
206 
207  /*
208  * Poll the ready bit to see if the MDI read completed
209  * Increasing the time out as testing showed failures with
210  * the lower time out
211  */
212  for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
213  udelay(50);
214  mdic = er32(MDIC);
215  if (mdic & E1000_MDIC_READY)
216  break;
217  }
218  if (!(mdic & E1000_MDIC_READY)) {
219  e_dbg("MDI Read did not complete\n");
220  return -E1000_ERR_PHY;
221  }
222  if (mdic & E1000_MDIC_ERROR) {
223  e_dbg("MDI Error\n");
224  return -E1000_ERR_PHY;
225  }
226  *data = (u16) mdic;
227 
228  /*
229  * Allow some time after each MDIC transaction to avoid
230  * reading duplicate data in the next MDIC transaction.
231  */
232  if (hw->mac.type == e1000_pch2lan)
233  udelay(100);
234 
235  return 0;
236 }
237 
246 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
247 {
248  struct e1000_phy_info *phy = &hw->phy;
249  u32 i, mdic = 0;
250 
251  if (offset > MAX_PHY_REG_ADDRESS) {
252  e_dbg("PHY Address %d is out of range\n", offset);
253  return -E1000_ERR_PARAM;
254  }
255 
256  /*
257  * Set up Op-code, Phy Address, and register offset in the MDI
258  * Control register. The MAC will take care of interfacing with the
259  * PHY to retrieve the desired data.
260  */
261  mdic = (((u32)data) |
262  (offset << E1000_MDIC_REG_SHIFT) |
263  (phy->addr << E1000_MDIC_PHY_SHIFT) |
264  (E1000_MDIC_OP_WRITE));
265 
266  ew32(MDIC, mdic);
267 
268  /*
269  * Poll the ready bit to see if the MDI read completed
270  * Increasing the time out as testing showed failures with
271  * the lower time out
272  */
273  for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
274  udelay(50);
275  mdic = er32(MDIC);
276  if (mdic & E1000_MDIC_READY)
277  break;
278  }
279  if (!(mdic & E1000_MDIC_READY)) {
280  e_dbg("MDI Write did not complete\n");
281  return -E1000_ERR_PHY;
282  }
283  if (mdic & E1000_MDIC_ERROR) {
284  e_dbg("MDI Error\n");
285  return -E1000_ERR_PHY;
286  }
287 
288  /*
289  * Allow some time after each MDIC transaction to avoid
290  * reading duplicate data in the next MDIC transaction.
291  */
292  if (hw->mac.type == e1000_pch2lan)
293  udelay(100);
294 
295  return 0;
296 }
297 
308 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
309 {
310  s32 ret_val;
311 
312  ret_val = hw->phy.ops.acquire(hw);
313  if (ret_val)
314  return ret_val;
315 
316  ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
317  data);
318 
319  hw->phy.ops.release(hw);
320 
321  return ret_val;
322 }
323 
333 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
334 {
335  s32 ret_val;
336 
337  ret_val = hw->phy.ops.acquire(hw);
338  if (ret_val)
339  return ret_val;
340 
341  ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
342  data);
343 
344  hw->phy.ops.release(hw);
345 
346  return ret_val;
347 }
348 
358 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
359 {
360  e_dbg("Setting page 0x%x\n", page);
361 
362  hw->phy.addr = 1;
363 
364  return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
365 }
366 
378 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
379  bool locked)
380 {
381  s32 ret_val = 0;
382 
383  if (!locked) {
384  if (!hw->phy.ops.acquire)
385  return 0;
386 
387  ret_val = hw->phy.ops.acquire(hw);
388  if (ret_val)
389  return ret_val;
390  }
391 
392  if (offset > MAX_PHY_MULTI_PAGE_REG)
393  ret_val = e1000e_write_phy_reg_mdic(hw,
394  IGP01E1000_PHY_PAGE_SELECT,
395  (u16)offset);
396  if (!ret_val)
397  ret_val = e1000e_read_phy_reg_mdic(hw,
398  MAX_PHY_REG_ADDRESS & offset,
399  data);
400  if (!locked)
401  hw->phy.ops.release(hw);
402 
403  return ret_val;
404 }
405 
416 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
417 {
418  return __e1000e_read_phy_reg_igp(hw, offset, data, false);
419 }
420 
430 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
431 {
432  return __e1000e_read_phy_reg_igp(hw, offset, data, true);
433 }
434 
445 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
446  bool locked)
447 {
448  s32 ret_val = 0;
449 
450  if (!locked) {
451  if (!hw->phy.ops.acquire)
452  return 0;
453 
454  ret_val = hw->phy.ops.acquire(hw);
455  if (ret_val)
456  return ret_val;
457  }
458 
459  if (offset > MAX_PHY_MULTI_PAGE_REG)
460  ret_val = e1000e_write_phy_reg_mdic(hw,
461  IGP01E1000_PHY_PAGE_SELECT,
462  (u16)offset);
463  if (!ret_val)
464  ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
465  offset,
466  data);
467  if (!locked)
468  hw->phy.ops.release(hw);
469 
470  return ret_val;
471 }
472 
482 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
483 {
484  return __e1000e_write_phy_reg_igp(hw, offset, data, false);
485 }
486 
496 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
497 {
498  return __e1000e_write_phy_reg_igp(hw, offset, data, true);
499 }
500 
512 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
513  bool locked)
514 {
515  u32 kmrnctrlsta;
516 
517  if (!locked) {
518  s32 ret_val = 0;
519 
520  if (!hw->phy.ops.acquire)
521  return 0;
522 
523  ret_val = hw->phy.ops.acquire(hw);
524  if (ret_val)
525  return ret_val;
526  }
527 
528  kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
529  E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
530  ew32(KMRNCTRLSTA, kmrnctrlsta);
531  e1e_flush();
532 
533  udelay(2);
534 
535  kmrnctrlsta = er32(KMRNCTRLSTA);
536  *data = (u16)kmrnctrlsta;
537 
538  if (!locked)
539  hw->phy.ops.release(hw);
540 
541  return 0;
542 }
543 
554 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
555 {
556  return __e1000_read_kmrn_reg(hw, offset, data, false);
557 }
558 
569 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
570 {
571  return __e1000_read_kmrn_reg(hw, offset, data, true);
572 }
573 
585 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
586  bool locked)
587 {
588  u32 kmrnctrlsta;
589 
590  if (!locked) {
591  s32 ret_val = 0;
592 
593  if (!hw->phy.ops.acquire)
594  return 0;
595 
596  ret_val = hw->phy.ops.acquire(hw);
597  if (ret_val)
598  return ret_val;
599  }
600 
601  kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
602  E1000_KMRNCTRLSTA_OFFSET) | data;
603  ew32(KMRNCTRLSTA, kmrnctrlsta);
604  e1e_flush();
605 
606  udelay(2);
607 
608  if (!locked)
609  hw->phy.ops.release(hw);
610 
611  return 0;
612 }
613 
623 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
624 {
625  return __e1000_write_kmrn_reg(hw, offset, data, false);
626 }
627 
637 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
638 {
639  return __e1000_write_kmrn_reg(hw, offset, data, true);
640 }
641 
648 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
649 {
650  s32 ret_val;
651  u16 phy_data;
652 
653  /* Resolve Master/Slave mode */
654  ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &phy_data);
655  if (ret_val)
656  return ret_val;
657 
658  /* load defaults for future use */
659  hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
660  ((phy_data & CR_1000T_MS_VALUE) ?
661  e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
662 
663  switch (hw->phy.ms_type) {
664  case e1000_ms_force_master:
665  phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
666  break;
667  case e1000_ms_force_slave:
668  phy_data |= CR_1000T_MS_ENABLE;
669  phy_data &= ~(CR_1000T_MS_VALUE);
670  break;
671  case e1000_ms_auto:
672  phy_data &= ~CR_1000T_MS_ENABLE;
673  /* fall-through */
674  default:
675  break;
676  }
677 
678  return e1e_wphy(hw, PHY_1000T_CTRL, phy_data);
679 }
680 
687 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
688 {
689  s32 ret_val;
690  u16 phy_data;
691 
692  /* Enable CRS on Tx. This must be set for half-duplex operation. */
693  ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
694  if (ret_val)
695  return ret_val;
696 
697  phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
698 
699  /* Enable downshift */
700  phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
701 
702  ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
703  if (ret_val)
704  return ret_val;
705 
706  /* Set MDI/MDIX mode */
707  ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
708  if (ret_val)
709  return ret_val;
710  phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
711  /*
712  * Options:
713  * 0 - Auto (default)
714  * 1 - MDI mode
715  * 2 - MDI-X mode
716  */
717  switch (hw->phy.mdix) {
718  case 1:
719  break;
720  case 2:
721  phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
722  break;
723  case 0:
724  default:
725  phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
726  break;
727  }
728  ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
729  if (ret_val)
730  return ret_val;
731 
732  return e1000_set_master_slave_mode(hw);
733 }
734 
742 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
743 {
744  struct e1000_phy_info *phy = &hw->phy;
745  s32 ret_val;
746  u16 phy_data;
747 
748  /* Enable CRS on Tx. This must be set for half-duplex operation. */
749  ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
750  if (ret_val)
751  return ret_val;
752 
753  /* For BM PHY this bit is downshift enable */
754  if (phy->type != e1000_phy_bm)
755  phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
756 
757  /*
758  * Options:
759  * MDI/MDI-X = 0 (default)
760  * 0 - Auto for all speeds
761  * 1 - MDI mode
762  * 2 - MDI-X mode
763  * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
764  */
765  phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
766 
767  switch (phy->mdix) {
768  case 1:
769  phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
770  break;
771  case 2:
772  phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
773  break;
774  case 3:
775  phy_data |= M88E1000_PSCR_AUTO_X_1000T;
776  break;
777  case 0:
778  default:
779  phy_data |= M88E1000_PSCR_AUTO_X_MODE;
780  break;
781  }
782 
783  /*
784  * Options:
785  * disable_polarity_correction = 0 (default)
786  * Automatic Correction for Reversed Cable Polarity
787  * 0 - Disabled
788  * 1 - Enabled
789  */
790  phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
791  if (phy->disable_polarity_correction)
792  phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
793 
794  /* Enable downshift on BM (disabled by default) */
795  if (phy->type == e1000_phy_bm) {
796  /* For 82574/82583, first disable then enable downshift */
797  if (phy->id == BME1000_E_PHY_ID_R2) {
798  phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
799  ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
800  phy_data);
801  if (ret_val)
802  return ret_val;
803  /* Commit the changes. */
804  ret_val = e1000e_commit_phy(hw);
805  if (ret_val) {
806  e_dbg("Error committing the PHY changes\n");
807  return ret_val;
808  }
809  }
810 
811  phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
812  }
813 
814  ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
815  if (ret_val)
816  return ret_val;
817 
818  if ((phy->type == e1000_phy_m88) &&
819  (phy->revision < E1000_REVISION_4) &&
820  (phy->id != BME1000_E_PHY_ID_R2)) {
821  /*
822  * Force TX_CLK in the Extended PHY Specific Control Register
823  * to 25MHz clock.
824  */
825  ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
826  if (ret_val)
827  return ret_val;
828 
829  phy_data |= M88E1000_EPSCR_TX_CLK_25;
830 
831  if ((phy->revision == 2) &&
832  (phy->id == M88E1111_I_PHY_ID)) {
833  /* 82573L PHY - set the downshift counter to 5x. */
834  phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
835  phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
836  } else {
837  /* Configure Master and Slave downshift values */
838  phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
839  M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
840  phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
841  M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
842  }
843  ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
844  if (ret_val)
845  return ret_val;
846  }
847 
848  if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
849  /* Set PHY page 0, register 29 to 0x0003 */
850  ret_val = e1e_wphy(hw, 29, 0x0003);
851  if (ret_val)
852  return ret_val;
853 
854  /* Set PHY page 0, register 30 to 0x0000 */
855  ret_val = e1e_wphy(hw, 30, 0x0000);
856  if (ret_val)
857  return ret_val;
858  }
859 
860  /* Commit the changes. */
861  ret_val = e1000e_commit_phy(hw);
862  if (ret_val) {
863  e_dbg("Error committing the PHY changes\n");
864  return ret_val;
865  }
866 
867  if (phy->type == e1000_phy_82578) {
868  ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
869  if (ret_val)
870  return ret_val;
871 
872  /* 82578 PHY - set the downshift count to 1x. */
873  phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
874  phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
875  ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
876  if (ret_val)
877  return ret_val;
878  }
879 
880  return 0;
881 }
882 
890 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
891 {
892  struct e1000_phy_info *phy = &hw->phy;
893  s32 ret_val;
894  u16 data;
895 
896  ret_val = e1000_phy_hw_reset(hw);
897  if (ret_val) {
898  e_dbg("Error resetting the PHY.\n");
899  return ret_val;
900  }
901 
902  /*
903  * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
904  * timeout issues when LFS is enabled.
905  */
906  msleep(100);
907 
908  /* disable lplu d0 during driver init */
909  ret_val = e1000_set_d0_lplu_state(hw, false);
910  if (ret_val) {
911  e_dbg("Error Disabling LPLU D0\n");
912  return ret_val;
913  }
914  /* Configure mdi-mdix settings */
915  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
916  if (ret_val)
917  return ret_val;
918 
919  data &= ~IGP01E1000_PSCR_AUTO_MDIX;
920 
921  switch (phy->mdix) {
922  case 1:
923  data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
924  break;
925  case 2:
926  data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
927  break;
928  case 0:
929  default:
930  data |= IGP01E1000_PSCR_AUTO_MDIX;
931  break;
932  }
933  ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
934  if (ret_val)
935  return ret_val;
936 
937  /* set auto-master slave resolution settings */
938  if (hw->mac.autoneg) {
939  /*
940  * when autonegotiation advertisement is only 1000Mbps then we
941  * should disable SmartSpeed and enable Auto MasterSlave
942  * resolution as hardware default.
943  */
944  if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
945  /* Disable SmartSpeed */
946  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
947  &data);
948  if (ret_val)
949  return ret_val;
950 
951  data &= ~IGP01E1000_PSCFR_SMART_SPEED;
952  ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
953  data);
954  if (ret_val)
955  return ret_val;
956 
957  /* Set auto Master/Slave resolution process */
958  ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
959  if (ret_val)
960  return ret_val;
961 
962  data &= ~CR_1000T_MS_ENABLE;
963  ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
964  if (ret_val)
965  return ret_val;
966  }
967 
968  ret_val = e1000_set_master_slave_mode(hw);
969  }
970 
971  return ret_val;
972 }
973 
983 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
984 {
985  struct e1000_phy_info *phy = &hw->phy;
986  s32 ret_val;
987  u16 mii_autoneg_adv_reg;
988  u16 mii_1000t_ctrl_reg = 0;
989 
990  phy->autoneg_advertised &= phy->autoneg_mask;
991 
992  /* Read the MII Auto-Neg Advertisement Register (Address 4). */
993  ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
994  if (ret_val)
995  return ret_val;
996 
997  if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
998  /* Read the MII 1000Base-T Control Register (Address 9). */
999  ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1000  if (ret_val)
1001  return ret_val;
1002  }
1003 
1004  /*
1005  * Need to parse both autoneg_advertised and fc and set up
1006  * the appropriate PHY registers. First we will parse for
1007  * autoneg_advertised software override. Since we can advertise
1008  * a plethora of combinations, we need to check each bit
1009  * individually.
1010  */
1011 
1012  /*
1013  * First we clear all the 10/100 mb speed bits in the Auto-Neg
1014  * Advertisement Register (Address 4) and the 1000 mb speed bits in
1015  * the 1000Base-T Control Register (Address 9).
1016  */
1017  mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1018  NWAY_AR_100TX_HD_CAPS |
1019  NWAY_AR_10T_FD_CAPS |
1020  NWAY_AR_10T_HD_CAPS);
1021  mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1022 
1023  e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
1024 
1025  /* Do we want to advertise 10 Mb Half Duplex? */
1026  if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1027  e_dbg("Advertise 10mb Half duplex\n");
1028  mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1029  }
1030 
1031  /* Do we want to advertise 10 Mb Full Duplex? */
1032  if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1033  e_dbg("Advertise 10mb Full duplex\n");
1034  mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1035  }
1036 
1037  /* Do we want to advertise 100 Mb Half Duplex? */
1038  if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1039  e_dbg("Advertise 100mb Half duplex\n");
1040  mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1041  }
1042 
1043  /* Do we want to advertise 100 Mb Full Duplex? */
1044  if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1045  e_dbg("Advertise 100mb Full duplex\n");
1046  mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1047  }
1048 
1049  /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1050  if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1051  e_dbg("Advertise 1000mb Half duplex request denied!\n");
1052 
1053  /* Do we want to advertise 1000 Mb Full Duplex? */
1054  if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1055  e_dbg("Advertise 1000mb Full duplex\n");
1056  mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1057  }
1058 
1059  /*
1060  * Check for a software override of the flow control settings, and
1061  * setup the PHY advertisement registers accordingly. If
1062  * auto-negotiation is enabled, then software will have to set the
1063  * "PAUSE" bits to the correct value in the Auto-Negotiation
1064  * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1065  * negotiation.
1066  *
1067  * The possible values of the "fc" parameter are:
1068  * 0: Flow control is completely disabled
1069  * 1: Rx flow control is enabled (we can receive pause frames
1070  * but not send pause frames).
1071  * 2: Tx flow control is enabled (we can send pause frames
1072  * but we do not support receiving pause frames).
1073  * 3: Both Rx and Tx flow control (symmetric) are enabled.
1074  * other: No software override. The flow control configuration
1075  * in the EEPROM is used.
1076  */
1077  switch (hw->fc.current_mode) {
1078  case e1000_fc_none:
1079  /*
1080  * Flow control (Rx & Tx) is completely disabled by a
1081  * software over-ride.
1082  */
1083  mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1084  break;
1085  case e1000_fc_rx_pause:
1086  /*
1087  * Rx Flow control is enabled, and Tx Flow control is
1088  * disabled, by a software over-ride.
1089  *
1090  * Since there really isn't a way to advertise that we are
1091  * capable of Rx Pause ONLY, we will advertise that we
1092  * support both symmetric and asymmetric Rx PAUSE. Later
1093  * (in e1000e_config_fc_after_link_up) we will disable the
1094  * hw's ability to send PAUSE frames.
1095  */
1096  mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1097  break;
1098  case e1000_fc_tx_pause:
1099  /*
1100  * Tx Flow control is enabled, and Rx Flow control is
1101  * disabled, by a software over-ride.
1102  */
1103  mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1104  mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1105  break;
1106  case e1000_fc_full:
1107  /*
1108  * Flow control (both Rx and Tx) is enabled by a software
1109  * over-ride.
1110  */
1111  mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1112  break;
1113  default:
1114  e_dbg("Flow control param set incorrectly\n");
1115  return -E1000_ERR_CONFIG;
1116  }
1117 
1118  ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1119  if (ret_val)
1120  return ret_val;
1121 
1122  e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1123 
1124  if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1125  ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1126 
1127  return ret_val;
1128 }
1129 
1139 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1140 {
1141  struct e1000_phy_info *phy = &hw->phy;
1142  s32 ret_val;
1143  u16 phy_ctrl;
1144 
1145  /*
1146  * Perform some bounds checking on the autoneg advertisement
1147  * parameter.
1148  */
1149  phy->autoneg_advertised &= phy->autoneg_mask;
1150 
1151  /*
1152  * If autoneg_advertised is zero, we assume it was not defaulted
1153  * by the calling code so we set to advertise full capability.
1154  */
1155  if (!phy->autoneg_advertised)
1156  phy->autoneg_advertised = phy->autoneg_mask;
1157 
1158  e_dbg("Reconfiguring auto-neg advertisement params\n");
1159  ret_val = e1000_phy_setup_autoneg(hw);
1160  if (ret_val) {
1161  e_dbg("Error Setting up Auto-Negotiation\n");
1162  return ret_val;
1163  }
1164  e_dbg("Restarting Auto-Neg\n");
1165 
1166  /*
1167  * Restart auto-negotiation by setting the Auto Neg Enable bit and
1168  * the Auto Neg Restart bit in the PHY control register.
1169  */
1170  ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1171  if (ret_val)
1172  return ret_val;
1173 
1174  phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1175  ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1176  if (ret_val)
1177  return ret_val;
1178 
1179  /*
1180  * Does the user want to wait for Auto-Neg to complete here, or
1181  * check at a later time (for example, callback routine).
1182  */
1183  if (phy->autoneg_wait_to_complete) {
1184  ret_val = e1000_wait_autoneg(hw);
1185  if (ret_val) {
1186  e_dbg("Error while waiting for autoneg to complete\n");
1187  return ret_val;
1188  }
1189  }
1190 
1191  hw->mac.get_link_status = true;
1192 
1193  return ret_val;
1194 }
1195 
1205 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1206 {
1207  s32 ret_val;
1208  bool link;
1209 
1210  if (hw->mac.autoneg) {
1211  /*
1212  * Setup autoneg and flow control advertisement and perform
1213  * autonegotiation.
1214  */
1215  ret_val = e1000_copper_link_autoneg(hw);
1216  if (ret_val)
1217  return ret_val;
1218  } else {
1219  /*
1220  * PHY will be set to 10H, 10F, 100H or 100F
1221  * depending on user settings.
1222  */
1223  e_dbg("Forcing Speed and Duplex\n");
1224  ret_val = e1000_phy_force_speed_duplex(hw);
1225  if (ret_val) {
1226  e_dbg("Error Forcing Speed and Duplex\n");
1227  return ret_val;
1228  }
1229  }
1230 
1231  /*
1232  * Check link status. Wait up to 100 microseconds for link to become
1233  * valid.
1234  */
1235  ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1236  &link);
1237  if (ret_val)
1238  return ret_val;
1239 
1240  if (link) {
1241  e_dbg("Valid link established!!!\n");
1242  hw->mac.ops.config_collision_dist(hw);
1243  ret_val = e1000e_config_fc_after_link_up(hw);
1244  } else {
1245  e_dbg("Unable to establish link!!!\n");
1246  }
1247 
1248  return ret_val;
1249 }
1250 
1259 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1260 {
1261  struct e1000_phy_info *phy = &hw->phy;
1262  s32 ret_val;
1263  u16 phy_data;
1264  bool link;
1265 
1266  ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1267  if (ret_val)
1268  return ret_val;
1269 
1270  e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1271 
1272  ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1273  if (ret_val)
1274  return ret_val;
1275 
1276  /*
1277  * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1278  * forced whenever speed and duplex are forced.
1279  */
1280  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1281  if (ret_val)
1282  return ret_val;
1283 
1284  phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1285  phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1286 
1287  ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1288  if (ret_val)
1289  return ret_val;
1290 
1291  e_dbg("IGP PSCR: %X\n", phy_data);
1292 
1293  udelay(1);
1294 
1295  if (phy->autoneg_wait_to_complete) {
1296  e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1297 
1298  ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1299  100000, &link);
1300  if (ret_val)
1301  return ret_val;
1302 
1303  if (!link)
1304  e_dbg("Link taking longer than expected.\n");
1305 
1306  /* Try once more */
1307  ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1308  100000, &link);
1309  }
1310 
1311  return ret_val;
1312 }
1313 
1324 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1325 {
1326  struct e1000_phy_info *phy = &hw->phy;
1327  s32 ret_val;
1328  u16 phy_data;
1329  bool link;
1330 
1331  /*
1332  * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1333  * forced whenever speed and duplex are forced.
1334  */
1335  ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1336  if (ret_val)
1337  return ret_val;
1338 
1339  phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1340  ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1341  if (ret_val)
1342  return ret_val;
1343 
1344  e_dbg("M88E1000 PSCR: %X\n", phy_data);
1345 
1346  ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1347  if (ret_val)
1348  return ret_val;
1349 
1350  e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1351 
1352  ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1353  if (ret_val)
1354  return ret_val;
1355 
1356  /* Reset the phy to commit changes. */
1357  ret_val = e1000e_commit_phy(hw);
1358  if (ret_val)
1359  return ret_val;
1360 
1361  if (phy->autoneg_wait_to_complete) {
1362  e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1363 
1364  ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1365  100000, &link);
1366  if (ret_val)
1367  return ret_val;
1368 
1369  if (!link) {
1370  if (hw->phy.type != e1000_phy_m88) {
1371  e_dbg("Link taking longer than expected.\n");
1372  } else {
1373  /*
1374  * We didn't get link.
1375  * Reset the DSP and cross our fingers.
1376  */
1377  ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1378  0x001d);
1379  if (ret_val)
1380  return ret_val;
1381  ret_val = e1000e_phy_reset_dsp(hw);
1382  if (ret_val)
1383  return ret_val;
1384  }
1385  }
1386 
1387  /* Try once more */
1388  ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1389  100000, &link);
1390  if (ret_val)
1391  return ret_val;
1392  }
1393 
1394  if (hw->phy.type != e1000_phy_m88)
1395  return 0;
1396 
1397  ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1398  if (ret_val)
1399  return ret_val;
1400 
1401  /*
1402  * Resetting the phy means we need to re-force TX_CLK in the
1403  * Extended PHY Specific Control Register to 25MHz clock from
1404  * the reset value of 2.5MHz.
1405  */
1406  phy_data |= M88E1000_EPSCR_TX_CLK_25;
1407  ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1408  if (ret_val)
1409  return ret_val;
1410 
1411  /*
1412  * In addition, we must re-enable CRS on Tx for both half and full
1413  * duplex.
1414  */
1415  ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1416  if (ret_val)
1417  return ret_val;
1418 
1419  phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1420  ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1421 
1422  return ret_val;
1423 }
1424 
1433 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1434 {
1435  struct e1000_phy_info *phy = &hw->phy;
1436  s32 ret_val;
1437  u16 data;
1438  bool link;
1439 
1440  ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1441  if (ret_val)
1442  return ret_val;
1443 
1444  e1000e_phy_force_speed_duplex_setup(hw, &data);
1445 
1446  ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1447  if (ret_val)
1448  return ret_val;
1449 
1450  /* Disable MDI-X support for 10/100 */
1451  ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1452  if (ret_val)
1453  return ret_val;
1454 
1455  data &= ~IFE_PMC_AUTO_MDIX;
1456  data &= ~IFE_PMC_FORCE_MDIX;
1457 
1458  ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1459  if (ret_val)
1460  return ret_val;
1461 
1462  e_dbg("IFE PMC: %X\n", data);
1463 
1464  udelay(1);
1465 
1466  if (phy->autoneg_wait_to_complete) {
1467  e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1468 
1469  ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1470  100000, &link);
1471  if (ret_val)
1472  return ret_val;
1473 
1474  if (!link)
1475  e_dbg("Link taking longer than expected.\n");
1476 
1477  /* Try once more */
1478  ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1479  100000, &link);
1480  if (ret_val)
1481  return ret_val;
1482  }
1483 
1484  return 0;
1485 }
1486 
1499 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1500 {
1501  struct e1000_mac_info *mac = &hw->mac;
1502  u32 ctrl;
1503 
1504  /* Turn off flow control when forcing speed/duplex */
1505  hw->fc.current_mode = e1000_fc_none;
1506 
1507  /* Force speed/duplex on the mac */
1508  ctrl = er32(CTRL);
1509  ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1510  ctrl &= ~E1000_CTRL_SPD_SEL;
1511 
1512  /* Disable Auto Speed Detection */
1513  ctrl &= ~E1000_CTRL_ASDE;
1514 
1515  /* Disable autoneg on the phy */
1516  *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1517 
1518  /* Forcing Full or Half Duplex? */
1519  if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1520  ctrl &= ~E1000_CTRL_FD;
1521  *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1522  e_dbg("Half Duplex\n");
1523  } else {
1524  ctrl |= E1000_CTRL_FD;
1525  *phy_ctrl |= MII_CR_FULL_DUPLEX;
1526  e_dbg("Full Duplex\n");
1527  }
1528 
1529  /* Forcing 10mb or 100mb? */
1530  if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1531  ctrl |= E1000_CTRL_SPD_100;
1532  *phy_ctrl |= MII_CR_SPEED_100;
1533  *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1534  e_dbg("Forcing 100mb\n");
1535  } else {
1536  ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1537  *phy_ctrl |= MII_CR_SPEED_10;
1538  *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1539  e_dbg("Forcing 10mb\n");
1540  }
1541 
1542  hw->mac.ops.config_collision_dist(hw);
1543 
1544  ew32(CTRL, ctrl);
1545 }
1546 
1561 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1562 {
1563  struct e1000_phy_info *phy = &hw->phy;
1564  s32 ret_val;
1565  u16 data;
1566 
1567  ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1568  if (ret_val)
1569  return ret_val;
1570 
1571  if (!active) {
1572  data &= ~IGP02E1000_PM_D3_LPLU;
1573  ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1574  if (ret_val)
1575  return ret_val;
1576  /*
1577  * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1578  * during Dx states where the power conservation is most
1579  * important. During driver activity we should enable
1580  * SmartSpeed, so performance is maintained.
1581  */
1582  if (phy->smart_speed == e1000_smart_speed_on) {
1583  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1584  &data);
1585  if (ret_val)
1586  return ret_val;
1587 
1588  data |= IGP01E1000_PSCFR_SMART_SPEED;
1589  ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1590  data);
1591  if (ret_val)
1592  return ret_val;
1593  } else if (phy->smart_speed == e1000_smart_speed_off) {
1594  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1595  &data);
1596  if (ret_val)
1597  return ret_val;
1598 
1599  data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1600  ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1601  data);
1602  if (ret_val)
1603  return ret_val;
1604  }
1605  } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1606  (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1607  (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1608  data |= IGP02E1000_PM_D3_LPLU;
1609  ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1610  if (ret_val)
1611  return ret_val;
1612 
1613  /* When LPLU is enabled, we should disable SmartSpeed */
1614  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1615  if (ret_val)
1616  return ret_val;
1617 
1618  data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1619  ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1620  }
1621 
1622  return ret_val;
1623 }
1624 
1633 s32 e1000e_check_downshift(struct e1000_hw *hw)
1634 {
1635  struct e1000_phy_info *phy = &hw->phy;
1636  s32 ret_val;
1637  u16 phy_data, offset, mask;
1638 
1639  switch (phy->type) {
1640  case e1000_phy_m88:
1641  case e1000_phy_gg82563:
1642  case e1000_phy_bm:
1643  case e1000_phy_82578:
1644  offset = M88E1000_PHY_SPEC_STATUS;
1645  mask = M88E1000_PSSR_DOWNSHIFT;
1646  break;
1647  case e1000_phy_igp_2:
1648  case e1000_phy_igp_3:
1649  offset = IGP01E1000_PHY_LINK_HEALTH;
1650  mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1651  break;
1652  default:
1653  /* speed downshift not supported */
1654  phy->speed_downgraded = false;
1655  return 0;
1656  }
1657 
1658  ret_val = e1e_rphy(hw, offset, &phy_data);
1659 
1660  if (!ret_val)
1661  phy->speed_downgraded = !!(phy_data & mask);
1662 
1663  return ret_val;
1664 }
1665 
1674 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1675 {
1676  struct e1000_phy_info *phy = &hw->phy;
1677  s32 ret_val;
1678  u16 data;
1679 
1680  ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1681 
1682  if (!ret_val)
1683  phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1684  ? e1000_rev_polarity_reversed
1685  : e1000_rev_polarity_normal;
1686 
1687  return ret_val;
1688 }
1689 
1699 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1700 {
1701  struct e1000_phy_info *phy = &hw->phy;
1702  s32 ret_val;
1703  u16 data, offset, mask;
1704 
1705  /*
1706  * Polarity is determined based on the speed of
1707  * our connection.
1708  */
1709  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1710  if (ret_val)
1711  return ret_val;
1712 
1713  if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1714  IGP01E1000_PSSR_SPEED_1000MBPS) {
1715  offset = IGP01E1000_PHY_PCS_INIT_REG;
1716  mask = IGP01E1000_PHY_POLARITY_MASK;
1717  } else {
1718  /*
1719  * This really only applies to 10Mbps since
1720  * there is no polarity for 100Mbps (always 0).
1721  */
1722  offset = IGP01E1000_PHY_PORT_STATUS;
1723  mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1724  }
1725 
1726  ret_val = e1e_rphy(hw, offset, &data);
1727 
1728  if (!ret_val)
1729  phy->cable_polarity = (data & mask)
1730  ? e1000_rev_polarity_reversed
1731  : e1000_rev_polarity_normal;
1732 
1733  return ret_val;
1734 }
1735 
1742 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1743 {
1744  struct e1000_phy_info *phy = &hw->phy;
1745  s32 ret_val;
1746  u16 phy_data, offset, mask;
1747 
1748  /*
1749  * Polarity is determined based on the reversal feature being enabled.
1750  */
1751  if (phy->polarity_correction) {
1752  offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1753  mask = IFE_PESC_POLARITY_REVERSED;
1754  } else {
1755  offset = IFE_PHY_SPECIAL_CONTROL;
1756  mask = IFE_PSC_FORCE_POLARITY;
1757  }
1758 
1759  ret_val = e1e_rphy(hw, offset, &phy_data);
1760 
1761  if (!ret_val)
1762  phy->cable_polarity = (phy_data & mask)
1763  ? e1000_rev_polarity_reversed
1764  : e1000_rev_polarity_normal;
1765 
1766  return ret_val;
1767 }
1768 
1776 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1777 {
1778  s32 ret_val = 0;
1779  u16 i, phy_status;
1780 
1781  /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1782  for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1783  ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1784  if (ret_val)
1785  break;
1786  ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1787  if (ret_val)
1788  break;
1789  if (phy_status & MII_SR_AUTONEG_COMPLETE)
1790  break;
1791  msleep(100);
1792  }
1793 
1794  /*
1795  * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1796  * has completed.
1797  */
1798  return ret_val;
1799 }
1800 
1810 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1811  u32 usec_interval, bool *success)
1812 {
1813  s32 ret_val = 0;
1814  u16 i, phy_status;
1815 
1816  for (i = 0; i < iterations; i++) {
1817  /*
1818  * Some PHYs require the PHY_STATUS register to be read
1819  * twice due to the link bit being sticky. No harm doing
1820  * it across the board.
1821  */
1822  ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1823  if (ret_val)
1824  /*
1825  * If the first read fails, another entity may have
1826  * ownership of the resources, wait and try again to
1827  * see if they have relinquished the resources yet.
1828  */
1829  udelay(usec_interval);
1830  ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1831  if (ret_val)
1832  break;
1833  if (phy_status & MII_SR_LINK_STATUS)
1834  break;
1835  if (usec_interval >= 1000)
1836  mdelay(usec_interval/1000);
1837  else
1838  udelay(usec_interval);
1839  }
1840 
1841  *success = (i < iterations);
1842 
1843  return ret_val;
1844 }
1845 
1861 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1862 {
1863  struct e1000_phy_info *phy = &hw->phy;
1864  s32 ret_val;
1865  u16 phy_data, index;
1866 
1867  ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1868  if (ret_val)
1869  return ret_val;
1870 
1871  index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1872  M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1873 
1874  if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1875  return -E1000_ERR_PHY;
1876 
1877  phy->min_cable_length = e1000_m88_cable_length_table[index];
1878  phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1879 
1880  phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1881 
1882  return 0;
1883 }
1884 
1896 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1897 {
1898  struct e1000_phy_info *phy = &hw->phy;
1899  s32 ret_val;
1900  u16 phy_data, i, agc_value = 0;
1901  u16 cur_agc_index, max_agc_index = 0;
1902  u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1903  static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1904  IGP02E1000_PHY_AGC_A,
1905  IGP02E1000_PHY_AGC_B,
1906  IGP02E1000_PHY_AGC_C,
1907  IGP02E1000_PHY_AGC_D
1908  };
1909 
1910  /* Read the AGC registers for all channels */
1911  for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1912  ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1913  if (ret_val)
1914  return ret_val;
1915 
1916  /*
1917  * Getting bits 15:9, which represent the combination of
1918  * coarse and fine gain values. The result is a number
1919  * that can be put into the lookup table to obtain the
1920  * approximate cable length.
1921  */
1922  cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1923  IGP02E1000_AGC_LENGTH_MASK;
1924 
1925  /* Array index bound check. */
1926  if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1927  (cur_agc_index == 0))
1928  return -E1000_ERR_PHY;
1929 
1930  /* Remove min & max AGC values from calculation. */
1931  if (e1000_igp_2_cable_length_table[min_agc_index] >
1932  e1000_igp_2_cable_length_table[cur_agc_index])
1933  min_agc_index = cur_agc_index;
1934  if (e1000_igp_2_cable_length_table[max_agc_index] <
1935  e1000_igp_2_cable_length_table[cur_agc_index])
1936  max_agc_index = cur_agc_index;
1937 
1938  agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1939  }
1940 
1941  agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1942  e1000_igp_2_cable_length_table[max_agc_index]);
1943  agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1944 
1945  /* Calculate cable length with the error range of +/- 10 meters. */
1946  phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1947  (agc_value - IGP02E1000_AGC_RANGE) : 0;
1948  phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1949 
1950  phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1951 
1952  return 0;
1953 }
1954 
1965 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1966 {
1967  struct e1000_phy_info *phy = &hw->phy;
1968  s32 ret_val;
1969  u16 phy_data;
1970  bool link;
1971 
1972  if (phy->media_type != e1000_media_type_copper) {
1973  e_dbg("Phy info is only valid for copper media\n");
1974  return -E1000_ERR_CONFIG;
1975  }
1976 
1977  ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1978  if (ret_val)
1979  return ret_val;
1980 
1981  if (!link) {
1982  e_dbg("Phy info is only valid if link is up\n");
1983  return -E1000_ERR_CONFIG;
1984  }
1985 
1986  ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1987  if (ret_val)
1988  return ret_val;
1989 
1990  phy->polarity_correction = !!(phy_data &
1991  M88E1000_PSCR_POLARITY_REVERSAL);
1992 
1993  ret_val = e1000_check_polarity_m88(hw);
1994  if (ret_val)
1995  return ret_val;
1996 
1997  ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1998  if (ret_val)
1999  return ret_val;
2000 
2001  phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2002 
2003  if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2004  ret_val = e1000_get_cable_length(hw);
2005  if (ret_val)
2006  return ret_val;
2007 
2008  ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
2009  if (ret_val)
2010  return ret_val;
2011 
2012  phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2013  ? e1000_1000t_rx_status_ok
2014  : e1000_1000t_rx_status_not_ok;
2015 
2016  phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2017  ? e1000_1000t_rx_status_ok
2018  : e1000_1000t_rx_status_not_ok;
2019  } else {
2020  /* Set values to "undefined" */
2021  phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2022  phy->local_rx = e1000_1000t_rx_status_undefined;
2023  phy->remote_rx = e1000_1000t_rx_status_undefined;
2024  }
2025 
2026  return ret_val;
2027 }
2028 
2038 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
2039 {
2040  struct e1000_phy_info *phy = &hw->phy;
2041  s32 ret_val;
2042  u16 data;
2043  bool link;
2044 
2045  ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2046  if (ret_val)
2047  return ret_val;
2048 
2049  if (!link) {
2050  e_dbg("Phy info is only valid if link is up\n");
2051  return -E1000_ERR_CONFIG;
2052  }
2053 
2054  phy->polarity_correction = true;
2055 
2056  ret_val = e1000_check_polarity_igp(hw);
2057  if (ret_val)
2058  return ret_val;
2059 
2060  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2061  if (ret_val)
2062  return ret_val;
2063 
2064  phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2065 
2066  if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2067  IGP01E1000_PSSR_SPEED_1000MBPS) {
2068  ret_val = e1000_get_cable_length(hw);
2069  if (ret_val)
2070  return ret_val;
2071 
2072  ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2073  if (ret_val)
2074  return ret_val;
2075 
2076  phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2077  ? e1000_1000t_rx_status_ok
2078  : e1000_1000t_rx_status_not_ok;
2079 
2080  phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2081  ? e1000_1000t_rx_status_ok
2082  : e1000_1000t_rx_status_not_ok;
2083  } else {
2084  phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2085  phy->local_rx = e1000_1000t_rx_status_undefined;
2086  phy->remote_rx = e1000_1000t_rx_status_undefined;
2087  }
2088 
2089  return ret_val;
2090 }
2091 
2098 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2099 {
2100  struct e1000_phy_info *phy = &hw->phy;
2101  s32 ret_val;
2102  u16 data;
2103  bool link;
2104 
2105  ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2106  if (ret_val)
2107  return ret_val;
2108 
2109  if (!link) {
2110  e_dbg("Phy info is only valid if link is up\n");
2111  return -E1000_ERR_CONFIG;
2112  }
2113 
2114  ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2115  if (ret_val)
2116  return ret_val;
2117  phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2118 
2119  if (phy->polarity_correction) {
2120  ret_val = e1000_check_polarity_ife(hw);
2121  if (ret_val)
2122  return ret_val;
2123  } else {
2124  /* Polarity is forced */
2125  phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2126  ? e1000_rev_polarity_reversed
2127  : e1000_rev_polarity_normal;
2128  }
2129 
2130  ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2131  if (ret_val)
2132  return ret_val;
2133 
2134  phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2135 
2136  /* The following parameters are undefined for 10/100 operation. */
2137  phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2138  phy->local_rx = e1000_1000t_rx_status_undefined;
2139  phy->remote_rx = e1000_1000t_rx_status_undefined;
2140 
2141  return 0;
2142 }
2143 
2151 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2152 {
2153  s32 ret_val;
2154  u16 phy_ctrl;
2155 
2156  ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2157  if (ret_val)
2158  return ret_val;
2159 
2160  phy_ctrl |= MII_CR_RESET;
2161  ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2162  if (ret_val)
2163  return ret_val;
2164 
2165  udelay(1);
2166 
2167  return ret_val;
2168 }
2169 
2179 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2180 {
2181  struct e1000_phy_info *phy = &hw->phy;
2182  s32 ret_val;
2183  u32 ctrl;
2184 
2185  if (phy->ops.check_reset_block) {
2186  ret_val = phy->ops.check_reset_block(hw);
2187  if (ret_val)
2188  return 0;
2189  }
2190 
2191  ret_val = phy->ops.acquire(hw);
2192  if (ret_val)
2193  return ret_val;
2194 
2195  ctrl = er32(CTRL);
2196  ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2197  e1e_flush();
2198 
2199  udelay(phy->reset_delay_us);
2200 
2201  ew32(CTRL, ctrl);
2202  e1e_flush();
2203 
2204  udelay(150);
2205 
2206  phy->ops.release(hw);
2207 
2208  return e1000_get_phy_cfg_done(hw);
2209 }
2210 
2218 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2219 {
2220  mdelay(10);
2221 
2222  return 0;
2223 }
2224 
2231 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2232 {
2233  e_dbg("Running IGP 3 PHY init script\n");
2234 
2235  /* PHY init IGP 3 */
2236  /* Enable rise/fall, 10-mode work in class-A */
2237  e1e_wphy(hw, 0x2F5B, 0x9018);
2238  /* Remove all caps from Replica path filter */
2239  e1e_wphy(hw, 0x2F52, 0x0000);
2240  /* Bias trimming for ADC, AFE and Driver (Default) */
2241  e1e_wphy(hw, 0x2FB1, 0x8B24);
2242  /* Increase Hybrid poly bias */
2243  e1e_wphy(hw, 0x2FB2, 0xF8F0);
2244  /* Add 4% to Tx amplitude in Gig mode */
2245  e1e_wphy(hw, 0x2010, 0x10B0);
2246  /* Disable trimming (TTT) */
2247  e1e_wphy(hw, 0x2011, 0x0000);
2248  /* Poly DC correction to 94.6% + 2% for all channels */
2249  e1e_wphy(hw, 0x20DD, 0x249A);
2250  /* ABS DC correction to 95.9% */
2251  e1e_wphy(hw, 0x20DE, 0x00D3);
2252  /* BG temp curve trim */
2253  e1e_wphy(hw, 0x28B4, 0x04CE);
2254  /* Increasing ADC OPAMP stage 1 currents to max */
2255  e1e_wphy(hw, 0x2F70, 0x29E4);
2256  /* Force 1000 ( required for enabling PHY regs configuration) */
2257  e1e_wphy(hw, 0x0000, 0x0140);
2258  /* Set upd_freq to 6 */
2259  e1e_wphy(hw, 0x1F30, 0x1606);
2260  /* Disable NPDFE */
2261  e1e_wphy(hw, 0x1F31, 0xB814);
2262  /* Disable adaptive fixed FFE (Default) */
2263  e1e_wphy(hw, 0x1F35, 0x002A);
2264  /* Enable FFE hysteresis */
2265  e1e_wphy(hw, 0x1F3E, 0x0067);
2266  /* Fixed FFE for short cable lengths */
2267  e1e_wphy(hw, 0x1F54, 0x0065);
2268  /* Fixed FFE for medium cable lengths */
2269  e1e_wphy(hw, 0x1F55, 0x002A);
2270  /* Fixed FFE for long cable lengths */
2271  e1e_wphy(hw, 0x1F56, 0x002A);
2272  /* Enable Adaptive Clip Threshold */
2273  e1e_wphy(hw, 0x1F72, 0x3FB0);
2274  /* AHT reset limit to 1 */
2275  e1e_wphy(hw, 0x1F76, 0xC0FF);
2276  /* Set AHT master delay to 127 msec */
2277  e1e_wphy(hw, 0x1F77, 0x1DEC);
2278  /* Set scan bits for AHT */
2279  e1e_wphy(hw, 0x1F78, 0xF9EF);
2280  /* Set AHT Preset bits */
2281  e1e_wphy(hw, 0x1F79, 0x0210);
2282  /* Change integ_factor of channel A to 3 */
2283  e1e_wphy(hw, 0x1895, 0x0003);
2284  /* Change prop_factor of channels BCD to 8 */
2285  e1e_wphy(hw, 0x1796, 0x0008);
2286  /* Change cg_icount + enable integbp for channels BCD */
2287  e1e_wphy(hw, 0x1798, 0xD008);
2288  /*
2289  * Change cg_icount + enable integbp + change prop_factor_master
2290  * to 8 for channel A
2291  */
2292  e1e_wphy(hw, 0x1898, 0xD918);
2293  /* Disable AHT in Slave mode on channel A */
2294  e1e_wphy(hw, 0x187A, 0x0800);
2295  /*
2296  * Enable LPLU and disable AN to 1000 in non-D0a states,
2297  * Enable SPD+B2B
2298  */
2299  e1e_wphy(hw, 0x0019, 0x008D);
2300  /* Enable restart AN on an1000_dis change */
2301  e1e_wphy(hw, 0x001B, 0x2080);
2302  /* Enable wh_fifo read clock in 10/100 modes */
2303  e1e_wphy(hw, 0x0014, 0x0045);
2304  /* Restart AN, Speed selection is 1000 */
2305  e1e_wphy(hw, 0x0000, 0x1340);
2306 
2307  return 0;
2308 }
2309 
2310 /* Internal function pointers */
2311 
2319 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2320 {
2321  if (hw->phy.ops.get_cfg_done)
2322  return hw->phy.ops.get_cfg_done(hw);
2323 
2324  return 0;
2325 }
2326 
2334 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2335 {
2336  if (hw->phy.ops.force_speed_duplex)
2337  return hw->phy.ops.force_speed_duplex(hw);
2338 
2339  return 0;
2340 }
2341 
2348 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2349 {
2350  enum e1000_phy_type phy_type = e1000_phy_unknown;
2351 
2352  switch (phy_id) {
2353  case M88E1000_I_PHY_ID:
2354  case M88E1000_E_PHY_ID:
2355  case M88E1111_I_PHY_ID:
2356  case M88E1011_I_PHY_ID:
2357  phy_type = e1000_phy_m88;
2358  break;
2359  case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2360  phy_type = e1000_phy_igp_2;
2361  break;
2362  case GG82563_E_PHY_ID:
2363  phy_type = e1000_phy_gg82563;
2364  break;
2365  case IGP03E1000_E_PHY_ID:
2366  phy_type = e1000_phy_igp_3;
2367  break;
2368  case IFE_E_PHY_ID:
2369  case IFE_PLUS_E_PHY_ID:
2370  case IFE_C_E_PHY_ID:
2371  phy_type = e1000_phy_ife;
2372  break;
2373  case BME1000_E_PHY_ID:
2374  case BME1000_E_PHY_ID_R2:
2375  phy_type = e1000_phy_bm;
2376  break;
2377  case I82578_E_PHY_ID:
2378  phy_type = e1000_phy_82578;
2379  break;
2380  case I82577_E_PHY_ID:
2381  phy_type = e1000_phy_82577;
2382  break;
2383  case I82579_E_PHY_ID:
2384  phy_type = e1000_phy_82579;
2385  break;
2386  case I217_E_PHY_ID:
2387  phy_type = e1000_phy_i217;
2388  break;
2389  default:
2390  phy_type = e1000_phy_unknown;
2391  break;
2392  }
2393  return phy_type;
2394 }
2395 
2404 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2405 {
2406  u32 phy_addr = 0;
2407  u32 i;
2408  enum e1000_phy_type phy_type = e1000_phy_unknown;
2409 
2410  hw->phy.id = phy_type;
2411 
2412  for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2413  hw->phy.addr = phy_addr;
2414  i = 0;
2415 
2416  do {
2417  e1000e_get_phy_id(hw);
2418  phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2419 
2420  /*
2421  * If phy_type is valid, break - we found our
2422  * PHY address
2423  */
2424  if (phy_type != e1000_phy_unknown)
2425  return 0;
2426 
2427  usleep_range(1000, 2000);
2428  i++;
2429  } while (i < 10);
2430  }
2431 
2432  return -E1000_ERR_PHY_TYPE;
2433 }
2434 
2441 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2442 {
2443  u32 phy_addr = 2;
2444 
2445  if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2446  phy_addr = 1;
2447 
2448  return phy_addr;
2449 }
2450 
2460 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2461 {
2462  s32 ret_val;
2463  u32 page = offset >> IGP_PAGE_SHIFT;
2464 
2465  ret_val = hw->phy.ops.acquire(hw);
2466  if (ret_val)
2467  return ret_val;
2468 
2469  /* Page 800 works differently than the rest so it has its own func */
2470  if (page == BM_WUC_PAGE) {
2471  ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2472  false, false);
2473  goto release;
2474  }
2475 
2476  hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2477 
2478  if (offset > MAX_PHY_MULTI_PAGE_REG) {
2479  u32 page_shift, page_select;
2480 
2481  /*
2482  * Page select is register 31 for phy address 1 and 22 for
2483  * phy address 2 and 3. Page select is shifted only for
2484  * phy address 1.
2485  */
2486  if (hw->phy.addr == 1) {
2487  page_shift = IGP_PAGE_SHIFT;
2488  page_select = IGP01E1000_PHY_PAGE_SELECT;
2489  } else {
2490  page_shift = 0;
2491  page_select = BM_PHY_PAGE_SELECT;
2492  }
2493 
2494  /* Page is shifted left, PHY expects (page x 32) */
2495  ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2496  (page << page_shift));
2497  if (ret_val)
2498  goto release;
2499  }
2500 
2501  ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2502  data);
2503 
2504 release:
2505  hw->phy.ops.release(hw);
2506  return ret_val;
2507 }
2508 
2519 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2520 {
2521  s32 ret_val;
2522  u32 page = offset >> IGP_PAGE_SHIFT;
2523 
2524  ret_val = hw->phy.ops.acquire(hw);
2525  if (ret_val)
2526  return ret_val;
2527 
2528  /* Page 800 works differently than the rest so it has its own func */
2529  if (page == BM_WUC_PAGE) {
2530  ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2531  true, false);
2532  goto release;
2533  }
2534 
2535  hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2536 
2537  if (offset > MAX_PHY_MULTI_PAGE_REG) {
2538  u32 page_shift, page_select;
2539 
2540  /*
2541  * Page select is register 31 for phy address 1 and 22 for
2542  * phy address 2 and 3. Page select is shifted only for
2543  * phy address 1.
2544  */
2545  if (hw->phy.addr == 1) {
2546  page_shift = IGP_PAGE_SHIFT;
2547  page_select = IGP01E1000_PHY_PAGE_SELECT;
2548  } else {
2549  page_shift = 0;
2550  page_select = BM_PHY_PAGE_SELECT;
2551  }
2552 
2553  /* Page is shifted left, PHY expects (page x 32) */
2554  ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2555  (page << page_shift));
2556  if (ret_val)
2557  goto release;
2558  }
2559 
2560  ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2561  data);
2562 release:
2563  hw->phy.ops.release(hw);
2564  return ret_val;
2565 }
2566 
2577 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2578 {
2579  s32 ret_val;
2580  u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2581 
2582  ret_val = hw->phy.ops.acquire(hw);
2583  if (ret_val)
2584  return ret_val;
2585 
2586  /* Page 800 works differently than the rest so it has its own func */
2587  if (page == BM_WUC_PAGE) {
2588  ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2589  true, false);
2590  goto release;
2591  }
2592 
2593  hw->phy.addr = 1;
2594 
2595  if (offset > MAX_PHY_MULTI_PAGE_REG) {
2596 
2597  /* Page is shifted left, PHY expects (page x 32) */
2598  ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2599  page);
2600 
2601  if (ret_val)
2602  goto release;
2603  }
2604 
2605  ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2606  data);
2607 release:
2608  hw->phy.ops.release(hw);
2609  return ret_val;
2610 }
2611 
2621 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2622 {
2623  s32 ret_val;
2624  u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2625 
2626  ret_val = hw->phy.ops.acquire(hw);
2627  if (ret_val)
2628  return ret_val;
2629 
2630  /* Page 800 works differently than the rest so it has its own func */
2631  if (page == BM_WUC_PAGE) {
2632  ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2633  false, false);
2634  goto release;
2635  }
2636 
2637  hw->phy.addr = 1;
2638 
2639  if (offset > MAX_PHY_MULTI_PAGE_REG) {
2640  /* Page is shifted left, PHY expects (page x 32) */
2641  ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2642  page);
2643 
2644  if (ret_val)
2645  goto release;
2646  }
2647 
2648  ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2649  data);
2650 
2651 release:
2652  hw->phy.ops.release(hw);
2653  return ret_val;
2654 }
2655 
2664 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2665 {
2666  s32 ret_val;
2667  u16 temp;
2668 
2669  /* All page select, port ctrl and wakeup registers use phy address 1 */
2670  hw->phy.addr = 1;
2671 
2672  /* Select Port Control Registers page */
2673  ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2674  if (ret_val) {
2675  e_dbg("Could not set Port Control page\n");
2676  return ret_val;
2677  }
2678 
2679  ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2680  if (ret_val) {
2681  e_dbg("Could not read PHY register %d.%d\n",
2682  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2683  return ret_val;
2684  }
2685 
2686  /*
2687  * Enable both PHY wakeup mode and Wakeup register page writes.
2688  * Prevent a power state change by disabling ME and Host PHY wakeup.
2689  */
2690  temp = *phy_reg;
2691  temp |= BM_WUC_ENABLE_BIT;
2692  temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2693 
2694  ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2695  if (ret_val) {
2696  e_dbg("Could not write PHY register %d.%d\n",
2697  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2698  return ret_val;
2699  }
2700 
2701  /*
2702  * Select Host Wakeup Registers page - caller now able to write
2703  * registers on the Wakeup registers page
2704  */
2705  return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2706 }
2707 
2719 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2720 {
2721  s32 ret_val = 0;
2722 
2723  /* Select Port Control Registers page */
2724  ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2725  if (ret_val) {
2726  e_dbg("Could not set Port Control page\n");
2727  return ret_val;
2728  }
2729 
2730  /* Restore 769.17 to its original value */
2731  ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2732  if (ret_val)
2733  e_dbg("Could not restore PHY register %d.%d\n",
2734  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2735 
2736  return ret_val;
2737 }
2738 
2764 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2765  u16 *data, bool read, bool page_set)
2766 {
2767  s32 ret_val;
2768  u16 reg = BM_PHY_REG_NUM(offset);
2769  u16 page = BM_PHY_REG_PAGE(offset);
2770  u16 phy_reg = 0;
2771 
2772  /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2773  if ((hw->mac.type == e1000_pchlan) &&
2774  (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2775  e_dbg("Attempting to access page %d while gig enabled.\n",
2776  page);
2777 
2778  if (!page_set) {
2779  /* Enable access to PHY wakeup registers */
2780  ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2781  if (ret_val) {
2782  e_dbg("Could not enable PHY wakeup reg access\n");
2783  return ret_val;
2784  }
2785  }
2786 
2787  e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2788 
2789  /* Write the Wakeup register page offset value using opcode 0x11 */
2790  ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2791  if (ret_val) {
2792  e_dbg("Could not write address opcode to page %d\n", page);
2793  return ret_val;
2794  }
2795 
2796  if (read) {
2797  /* Read the Wakeup register page value using opcode 0x12 */
2798  ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2799  data);
2800  } else {
2801  /* Write the Wakeup register page value using opcode 0x12 */
2802  ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2803  *data);
2804  }
2805 
2806  if (ret_val) {
2807  e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2808  return ret_val;
2809  }
2810 
2811  if (!page_set)
2812  ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2813 
2814  return ret_val;
2815 }
2816 
2825 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2826 {
2827  u16 mii_reg = 0;
2828 
2829  /* The PHY will retain its settings across a power down/up cycle */
2830  e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2831  mii_reg &= ~MII_CR_POWER_DOWN;
2832  e1e_wphy(hw, PHY_CONTROL, mii_reg);
2833 }
2834 
2843 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2844 {
2845  u16 mii_reg = 0;
2846 
2847  /* The PHY will retain its settings across a power down/up cycle */
2848  e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2849  mii_reg |= MII_CR_POWER_DOWN;
2850  e1e_wphy(hw, PHY_CONTROL, mii_reg);
2851  usleep_range(1000, 2000);
2852 }
2853 
2861 s32 e1000e_commit_phy(struct e1000_hw *hw)
2862 {
2863  if (hw->phy.ops.commit)
2864  return hw->phy.ops.commit(hw);
2865 
2866  return 0;
2867 }
2868 
2883 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2884 {
2885  if (hw->phy.ops.set_d0_lplu_state)
2886  return hw->phy.ops.set_d0_lplu_state(hw, active);
2887 
2888  return 0;
2889 }
2890 
2902 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2903  bool locked, bool page_set)
2904 {
2905  s32 ret_val;
2906  u16 page = BM_PHY_REG_PAGE(offset);
2907  u16 reg = BM_PHY_REG_NUM(offset);
2908  u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2909 
2910  if (!locked) {
2911  ret_val = hw->phy.ops.acquire(hw);
2912  if (ret_val)
2913  return ret_val;
2914  }
2915 
2916  /* Page 800 works differently than the rest so it has its own func */
2917  if (page == BM_WUC_PAGE) {
2918  ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2919  true, page_set);
2920  goto out;
2921  }
2922 
2923  if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2924  ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2925  data, true);
2926  goto out;
2927  }
2928 
2929  if (!page_set) {
2930  if (page == HV_INTC_FC_PAGE_START)
2931  page = 0;
2932 
2933  if (reg > MAX_PHY_MULTI_PAGE_REG) {
2934  /* Page is shifted left, PHY expects (page x 32) */
2935  ret_val = e1000_set_page_igp(hw,
2936  (page << IGP_PAGE_SHIFT));
2937 
2938  hw->phy.addr = phy_addr;
2939 
2940  if (ret_val)
2941  goto out;
2942  }
2943  }
2944 
2945  e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2946  page << IGP_PAGE_SHIFT, reg);
2947 
2948  ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2949  data);
2950 out:
2951  if (!locked)
2952  hw->phy.ops.release(hw);
2953 
2954  return ret_val;
2955 }
2956 
2967 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2968 {
2969  return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2970 }
2971 
2981 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2982 {
2983  return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2984 }
2985 
2995 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2996 {
2997  return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2998 }
2999 
3010 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3011  bool locked, bool page_set)
3012 {
3013  s32 ret_val;
3014  u16 page = BM_PHY_REG_PAGE(offset);
3015  u16 reg = BM_PHY_REG_NUM(offset);
3016  u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3017 
3018  if (!locked) {
3019  ret_val = hw->phy.ops.acquire(hw);
3020  if (ret_val)
3021  return ret_val;
3022  }
3023 
3024  /* Page 800 works differently than the rest so it has its own func */
3025  if (page == BM_WUC_PAGE) {
3026  ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3027  false, page_set);
3028  goto out;
3029  }
3030 
3031  if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3032  ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3033  &data, false);
3034  goto out;
3035  }
3036 
3037  if (!page_set) {
3038  if (page == HV_INTC_FC_PAGE_START)
3039  page = 0;
3040 
3041  /*
3042  * Workaround MDIO accesses being disabled after entering IEEE
3043  * Power Down (when bit 11 of the PHY Control register is set)
3044  */
3045  if ((hw->phy.type == e1000_phy_82578) &&
3046  (hw->phy.revision >= 1) &&
3047  (hw->phy.addr == 2) &&
3048  !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
3049  u16 data2 = 0x7EFF;
3050  ret_val = e1000_access_phy_debug_regs_hv(hw,
3051  (1 << 6) | 0x3,
3052  &data2, false);
3053  if (ret_val)
3054  goto out;
3055  }
3056 
3057  if (reg > MAX_PHY_MULTI_PAGE_REG) {
3058  /* Page is shifted left, PHY expects (page x 32) */
3059  ret_val = e1000_set_page_igp(hw,
3060  (page << IGP_PAGE_SHIFT));
3061 
3062  hw->phy.addr = phy_addr;
3063 
3064  if (ret_val)
3065  goto out;
3066  }
3067  }
3068 
3069  e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3070  page << IGP_PAGE_SHIFT, reg);
3071 
3072  ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3073  data);
3074 
3075 out:
3076  if (!locked)
3077  hw->phy.ops.release(hw);
3078 
3079  return ret_val;
3080 }
3081 
3091 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3092 {
3093  return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3094 }
3095 
3105 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3106 {
3107  return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3108 }
3109 
3119 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3120 {
3121  return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3122 }
3123 
3128 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3129 {
3130  u32 phy_addr = 2;
3131 
3132  if (page >= HV_INTC_FC_PAGE_START)
3133  phy_addr = 1;
3134 
3135  return phy_addr;
3136 }
3137 
3150 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3151  u16 *data, bool read)
3152 {
3153  s32 ret_val;
3154  u32 addr_reg = 0;
3155  u32 data_reg = 0;
3156 
3157  /* This takes care of the difference with desktop vs mobile phy */
3158  addr_reg = (hw->phy.type == e1000_phy_82578) ?
3159  I82578_ADDR_REG : I82577_ADDR_REG;
3160  data_reg = addr_reg + 1;
3161 
3162  /* All operations in this function are phy address 2 */
3163  hw->phy.addr = 2;
3164 
3165  /* masking with 0x3F to remove the page from offset */
3166  ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3167  if (ret_val) {
3168  e_dbg("Could not write the Address Offset port register\n");
3169  return ret_val;
3170  }
3171 
3172  /* Read or write the data value next */
3173  if (read)
3174  ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3175  else
3176  ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3177 
3178  if (ret_val)
3179  e_dbg("Could not access the Data port register\n");
3180 
3181  return ret_val;
3182 }
3183 
3195 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3196 {
3197  s32 ret_val = 0;
3198  u16 data;
3199 
3200  if (hw->phy.type != e1000_phy_82578)
3201  return 0;
3202 
3203  /* Do not apply workaround if in PHY loopback bit 14 set */
3204  e1e_rphy(hw, PHY_CONTROL, &data);
3205  if (data & PHY_CONTROL_LB)
3206  return 0;
3207 
3208  /* check if link is up and at 1Gbps */
3209  ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3210  if (ret_val)
3211  return ret_val;
3212 
3213  data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3214  BM_CS_STATUS_SPEED_MASK;
3215 
3216  if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3217  BM_CS_STATUS_SPEED_1000))
3218  return 0;
3219 
3220  msleep(200);
3221 
3222  /* flush the packets in the fifo buffer */
3223  ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3224  HV_MUX_DATA_CTRL_FORCE_SPEED);
3225  if (ret_val)
3226  return ret_val;
3227 
3228  return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3229 }
3230 
3239 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3240 {
3241  struct e1000_phy_info *phy = &hw->phy;
3242  s32 ret_val;
3243  u16 data;
3244 
3245  ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3246 
3247  if (!ret_val)
3248  phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3249  ? e1000_rev_polarity_reversed
3250  : e1000_rev_polarity_normal;
3251 
3252  return ret_val;
3253 }
3254 
3261 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3262 {
3263  struct e1000_phy_info *phy = &hw->phy;
3264  s32 ret_val;
3265  u16 phy_data;
3266  bool link;
3267 
3268  ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
3269  if (ret_val)
3270  return ret_val;
3271 
3272  e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3273 
3274  ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
3275  if (ret_val)
3276  return ret_val;
3277 
3278  udelay(1);
3279 
3280  if (phy->autoneg_wait_to_complete) {
3281  e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3282 
3283  ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3284  100000, &link);
3285  if (ret_val)
3286  return ret_val;
3287 
3288  if (!link)
3289  e_dbg("Link taking longer than expected.\n");
3290 
3291  /* Try once more */
3292  ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3293  100000, &link);
3294  }
3295 
3296  return ret_val;
3297 }
3298 
3308 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3309 {
3310  struct e1000_phy_info *phy = &hw->phy;
3311  s32 ret_val;
3312  u16 data;
3313  bool link;
3314 
3315  ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3316  if (ret_val)
3317  return ret_val;
3318 
3319  if (!link) {
3320  e_dbg("Phy info is only valid if link is up\n");
3321  return -E1000_ERR_CONFIG;
3322  }
3323 
3324  phy->polarity_correction = true;
3325 
3326  ret_val = e1000_check_polarity_82577(hw);
3327  if (ret_val)
3328  return ret_val;
3329 
3330  ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3331  if (ret_val)
3332  return ret_val;
3333 
3334  phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3335 
3336  if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3337  I82577_PHY_STATUS2_SPEED_1000MBPS) {
3338  ret_val = hw->phy.ops.get_cable_length(hw);
3339  if (ret_val)
3340  return ret_val;
3341 
3342  ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
3343  if (ret_val)
3344  return ret_val;
3345 
3346  phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3347  ? e1000_1000t_rx_status_ok
3348  : e1000_1000t_rx_status_not_ok;
3349 
3350  phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3351  ? e1000_1000t_rx_status_ok
3352  : e1000_1000t_rx_status_not_ok;
3353  } else {
3354  phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3355  phy->local_rx = e1000_1000t_rx_status_undefined;
3356  phy->remote_rx = e1000_1000t_rx_status_undefined;
3357  }
3358 
3359  return 0;
3360 }
3361 
3369 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3370 {
3371  struct e1000_phy_info *phy = &hw->phy;
3372  s32 ret_val;
3373  u16 phy_data, length;
3374 
3375  ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3376  if (ret_val)
3377  return ret_val;
3378 
3379  length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3380  I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3381 
3382  if (length == E1000_CABLE_LENGTH_UNDEFINED)
3383  ret_val = -E1000_ERR_PHY;
3384 
3385  phy->cable_length = length;
3386 
3387  return 0;
3388 }
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