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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/bitops.h>#include <linux/types.h>#include <linux/timer.h>#include <linux/workqueue.h>#include <linux/io.h>#include <linux/netdevice.h>#include <linux/pci.h>#include <linux/pci-aspm.h>#include <linux/crc32.h>#include <linux/if_vlan.h>#include "hw.h"Go to the source code of this file.
Data Structures | |
| struct | e1000_ps_page |
| struct | e1000_buffer |
| struct | e1000_ring |
| struct | e1000_phy_regs |
| struct | e1000_adapter |
| struct | e1000_info |
Macros | |
| #define | e_dbg(format, arg...) netdev_dbg(hw->adapter->netdev, format, ## arg) |
| #define | e_err(format, arg...) netdev_err(adapter->netdev, format, ## arg) |
| #define | e_info(format, arg...) netdev_info(adapter->netdev, format, ## arg) |
| #define | e_warn(format, arg...) netdev_warn(adapter->netdev, format, ## arg) |
| #define | e_notice(format, arg...) netdev_notice(adapter->netdev, format, ## arg) |
| #define | E1000E_INT_MODE_LEGACY 0 |
| #define | E1000E_INT_MODE_MSI 1 |
| #define | E1000E_INT_MODE_MSIX 2 |
| #define | E1000_DEFAULT_TXD 256 |
| #define | E1000_MAX_TXD 4096 |
| #define | E1000_MIN_TXD 64 |
| #define | E1000_DEFAULT_RXD 256 |
| #define | E1000_MAX_RXD 4096 |
| #define | E1000_MIN_RXD 64 |
| #define | E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ |
| #define | E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ |
| #define | E1000_ERT_2048 0x100 |
| #define | E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ |
| #define | E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
| #define | AUTO_ALL_MODES 0 |
| #define | E1000_EEPROM_APME 0x0400 |
| #define | E1000_MNG_VLAN_NONE (-1) |
| #define | PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) |
| #define | DEFAULT_JUMBO 9234 |
| #define | BM_PORT_CTRL_PAGE 769 |
| #define | PHY_UPPER_SHIFT 21 |
| #define | BM_PHY_REG(page, reg) |
| #define | BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) |
| #define | BM_RCTL PHY_REG(BM_WUC_PAGE, 0) |
| #define | BM_WUC PHY_REG(BM_WUC_PAGE, 1) |
| #define | BM_WUFC PHY_REG(BM_WUC_PAGE, 2) |
| #define | BM_WUS PHY_REG(BM_WUC_PAGE, 3) |
| #define | BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) |
| #define | BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) |
| #define | BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) |
| #define | BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) |
| #define | BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) |
| #define | BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ |
| #define | BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ |
| #define | BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ |
| #define | BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ |
| #define | BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ |
| #define | BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ |
| #define | BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ |
| #define | HV_STATS_PAGE 778 |
| #define | HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */ |
| #define | HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) |
| #define | HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */ |
| #define | HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) |
| #define | HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */ |
| #define | HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) |
| #define | HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */ |
| #define | HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) |
| #define | HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */ |
| #define | HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) |
| #define | HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ |
| #define | HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) |
| #define | HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */ |
| #define | HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) |
| #define | E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ |
| #define | BM_CS_STATUS 17 |
| #define | BM_CS_STATUS_LINK_UP 0x0400 |
| #define | BM_CS_STATUS_RESOLVED 0x0800 |
| #define | BM_CS_STATUS_SPEED_MASK 0xC000 |
| #define | BM_CS_STATUS_SPEED_1000 0x8000 |
| #define | HV_M_STATUS 26 |
| #define | HV_M_STATUS_AUTONEG_COMPLETE 0x1000 |
| #define | HV_M_STATUS_SPEED_MASK 0x0300 |
| #define | HV_M_STATUS_SPEED_1000 0x0200 |
| #define | HV_M_STATUS_LINK_UP 0x0040 |
| #define | E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ |
| #define | E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 |
| #define | LINK_TIMEOUT 100 |
| #define | E1000_CHECK_RESET_COUNT 25 |
| #define | DEFAULT_RDTR 0 |
| #define | DEFAULT_RADV 8 |
| #define | BURST_RDTR 0x20 |
| #define | BURST_RADV 0x20 |
| #define | E1000_TXDCTL_DMA_BURST_ENABLE |
| #define | E1000_RXDCTL_DMA_BURST_ENABLE |
| #define | E1000_TIDV_FPD (1 << 31) |
| #define | E1000_RDTR_FPD (1 << 31) |
| #define | FLAG_HAS_AMT (1 << 0) |
| #define | FLAG_HAS_FLASH (1 << 1) |
| #define | FLAG_HAS_HW_VLAN_FILTER (1 << 2) |
| #define | FLAG_HAS_WOL (1 << 3) |
| #define | FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) |
| #define | FLAG_HAS_SWSM_ON_LOAD (1 << 6) |
| #define | FLAG_HAS_JUMBO_FRAMES (1 << 7) |
| #define | FLAG_READ_ONLY_NVM (1 << 8) |
| #define | FLAG_IS_ICH (1 << 9) |
| #define | FLAG_HAS_MSIX (1 << 10) |
| #define | FLAG_HAS_SMART_POWER_DOWN (1 << 11) |
| #define | FLAG_IS_QUAD_PORT_A (1 << 12) |
| #define | FLAG_IS_QUAD_PORT (1 << 13) |
| #define | FLAG_APME_IN_WUC (1 << 15) |
| #define | FLAG_APME_IN_CTRL3 (1 << 16) |
| #define | FLAG_APME_CHECK_PORT_B (1 << 17) |
| #define | FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) |
| #define | FLAG_NO_WAKE_UCAST (1 << 19) |
| #define | FLAG_MNG_PT_ENABLED (1 << 20) |
| #define | FLAG_RESET_OVERWRITES_LAA (1 << 21) |
| #define | FLAG_TARC_SPEED_MODE_BIT (1 << 22) |
| #define | FLAG_TARC_SET_BIT_ZERO (1 << 23) |
| #define | FLAG_RX_NEEDS_RESTART (1 << 24) |
| #define | FLAG_LSC_GIG_SPEED_DROP (1 << 25) |
| #define | FLAG_SMART_POWER_DOWN (1 << 26) |
| #define | FLAG_MSI_ENABLED (1 << 27) |
| #define | FLAG_TSO_FORCE (1 << 29) |
| #define | FLAG_RX_RESTART_NOW (1 << 30) |
| #define | FLAG_MSI_TEST_FAILED (1 << 31) |
| #define | FLAG2_CRC_STRIPPING (1 << 0) |
| #define | FLAG2_HAS_PHY_WAKEUP (1 << 1) |
| #define | FLAG2_IS_DISCARDING (1 << 2) |
| #define | FLAG2_DISABLE_ASPM_L1 (1 << 3) |
| #define | FLAG2_HAS_PHY_STATS (1 << 4) |
| #define | FLAG2_HAS_EEE (1 << 5) |
| #define | FLAG2_DMA_BURST (1 << 6) |
| #define | FLAG2_DISABLE_ASPM_L0S (1 << 7) |
| #define | FLAG2_DISABLE_AIM (1 << 8) |
| #define | FLAG2_CHECK_PHY_HANG (1 << 9) |
| #define | FLAG2_NO_DISABLE_RX (1 << 10) |
| #define | FLAG2_PCIM2PCI_ARBITER_WA (1 << 11) |
| #define | FLAG2_DFLT_CRC_STRIPPING (1 << 12) |
| #define | E1000_RX_DESC_PS(R, i) (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) |
| #define | E1000_RX_DESC_EXT(R, i) (&(((union e1000_rx_desc_extended *)((R).desc))[i])) |
| #define | E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) |
| #define | E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) |
| #define | E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) |
| #define | er32(reg) __er32(hw, E1000_##reg) |
| #define | ew32(reg, val) __ew32(hw, E1000_##reg, (val)) |
| #define | e1e_flush() er32(STATUS) |
| #define | E1000_WRITE_REG_ARRAY(a, reg, offset, value) (__ew32((a), (reg + ((offset) << 2)), (value))) |
| #define | E1000_READ_REG_ARRAY(a, reg, offset) (readl((a)->hw_addr + reg + ((offset) << 2))) |
Enumerations | |
| enum | e1000_boards { board_82571, board_82572, board_82573, board_82574, board_82583, board_80003es2lan, board_ich8lan, board_ich9lan, board_ich10lan, board_pchlan, board_pch2lan, board_pch_lpt } |
| enum | e1000_state_t { __E1000_TESTING, __E1000_RESETTING, __E1000_DOWN, __E1000_TESTING, __E1000_RESETTING, __E1000_ACCESS_SHARED_RESOURCE, __E1000_DOWN, __IGB_TESTING, __IGB_RESETTING, __IGB_DOWN } |
| enum | latency_range { lowest_latency = 0, low_latency = 1, bulk_latency = 2, latency_invalid = 255, lowest_latency = 0, low_latency = 1, bulk_latency = 2, latency_invalid = 255, lowest_latency = 0, low_latency = 1, bulk_latency = 2, latency_invalid = 255, lowest_latency = 0, low_latency = 1, bulk_latency = 2, latency_invalid = 255, lowest_latency = 0, low_latency = 1, bulk_latency = 2, latency_invalid = 255, lowest_latency = 0, low_latency = 1, bulk_latency = 2, latency_invalid = 255 } |
| #define BM_MTA | ( | _i | ) | (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) |
| #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) |
| #define BM_RAR_CTRL | ( | _i | ) | (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) |
| #define BM_RAR_H | ( | _i | ) | (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) |
| #define BM_RAR_L | ( | _i | ) | (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) |
| #define BM_RAR_M | ( | _i | ) | (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) |
| #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) |
| #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ |
| #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) |
| #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) |
| #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) |
| #define E1000_CONTEXT_DESC | ( | R, | |
| i | |||
| ) | E1000_GET_DESC(R, i, e1000_context_desc) |
| #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ |
| #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ |
| #define E1000_RXDCTL_DMA_BURST_ENABLE |
| #define E1000_TX_DESC | ( | R, | |
| i | |||
| ) | E1000_GET_DESC(R, i, e1000_tx_desc) |
| #define E1000_TXDCTL_DMA_BURST_ENABLE |
| #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) |
| #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */ |
| #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) |
| #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ |
| #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) |
| #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */ |
| #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) |
| #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */ |
| #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) |
| #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */ |
| #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) |
| #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */ |
| #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) |
| #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */ |
| #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) |
| enum e1000_boards |
| enum e1000_state_t |
| enum latency_range |
e1000_check_alt_mac_addr_generic - Check for alternate MAC addr : pointer to the HW structure
Checks the nvm for an alternate MAC address. An alternate MAC address can be setup by pre-boot software and must be treated like a permanent address and must override the actual permanent MAC address. If an alternate MAC address is found it is programmed into RAR0, replacing the permanent address that was installed into RAR0 by the Si on reset. This function will return SUCCESS unless it encounters an error while reading the EEPROM.
e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs : pointer to the HW structure : pointer to original contents of BM_WUC_ENABLE_REG
Restore BM_WUC_ENABLE_REG to its original value.
Assumes semaphore already acquired and *phy_reg is the contents of the BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by caller.
e1000_get_phy_info_82577 - Retrieve I82577 PHY information : pointer to the HW structure
Read PHY status to determine if link is up. If link is up, then set/determine 10base-T extended distance and polarity correction. Read PHY port status to determine MDI/MDIx and speed. Based on the speed, determine on the cable length, local and remote receiver.
e1000_link_stall_workaround_hv - Si workaround : pointer to the HW structure
This function works around a Si bug where the link partner can get a link up indication before the PHY does. If small packets are sent by the link partner they can be placed in the packet buffer without being properly accounted for by the PHY and will stall preventing further packets from being received. The workaround is to clear the packet buffer after the PHY detects link up.
e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 : pointer to the HW structure
During Sx to S0 transitions on non-managed devices or managed devices on which PHY resets are not blocked, if the PHY registers cannot be accessed properly by the s/w toggle the LANPHYPC value to power cycle the PHY. On i217, setup Intel Rapid Start Technology.
e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx : pointer to the HW structure
During S0 to Sx transition, it is possible the link remains at gig instead of negotiating to a lower speed. Before going to Sx, set 'Gig Disable' to force link speed negotiation to a lower speed based on the LPLU setting in the NVM or custom setting. For PCH and newer parts, the OEM bits PHY register (LED, GbE disable and LPLU configurations) also needs to be written. Parts that support (and are linked to a partner which support) EEE in 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power than 10Mbps w/o EEE.
| void e1000e_check_options | ( | struct e1000_adapter * | adapter | ) |
e1000e_check_options - Range Checking for Command Line Parameters : board private structure
This routine checks all command line parameters for valid user input. If an invalid value is given, or if no user specified value exists, a default value is used. The final value is stored in a variable in the adapter structure.
e1000e_config_fc_after_link_up - Configures flow control after link : pointer to the HW structure
Checks the status of auto-negotiation after link up to ensure that the speed and duplex were not forced. If the link needed to be forced, then flow control needs to be forced also. If auto-negotiation is enabled and did not fail, then we configure flow control based on our link partner.
e1000e_disable_pcie_master - Disables PCI-express master access : pointer to the HW structure
Returns 0 if successful, else returns -10 (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused the master requests to be disabled.
Disables PCI-Express master access and verifies there are no pending requests.
| void e1000e_down | ( | struct e1000_adapter * | adapter | ) |
e1000e_force_mac_fc - Force the MAC's flow control settings : pointer to the HW structure
Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the device control register to reflect the adapter settings. TFCE and RFCE need to be explicitly set by software when a copper PHY is used because autonegotiation is managed by the PHY rather than the MAC. Software must also configure these bits when link is forced on a fiber connection.
| void e1000e_free_rx_resources | ( | struct e1000_ring * | rx_ring | ) |
| void e1000e_free_tx_resources | ( | struct e1000_ring * | tx_ring | ) |
e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY : pointer to the HW structure
The automatic gain control (agc) normalizes the amplitude of the received signal, adjusting for the attenuation produced by the cable. By reading the AGC registers, which represent the combination of coarse and fine gain value, the value can be put into a lookup table to obtain the approximate cable length for each channel.
e1000e_get_cable_length_m88 - Determine cable length for m88 PHY : pointer to the HW structure
Reads the PHY specific status register to retrieve the cable length information. The cable length is determined by averaging the minimum and maximum values to get the "average" cable length. The m88 PHY has four possible cable length values, which are: Register Value Cable Length 0 < 50 meters 1 50 - 80 meters 2 80 - 110 meters 3 110 - 140 meters 4 > 140 meters
| void e1000e_get_hw_control | ( | struct e1000_adapter * | adapter | ) |
e1000e_get_hw_control - get control of the h/w from f/w : address of board private structure
e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. For ASF and Pass Through versions of f/w this means that the driver is loaded. For AMT version (only with 82573) of the f/w this means that the network i/f is open.
e1000e_get_phy_info_igp - Retrieve igp PHY information : pointer to the HW structure
Read PHY status to determine if link is up. If link is up, then set/determine 10base-T extended distance and polarity correction. Read PHY port status to determine MDI/MDIx and speed. Based on the speed, determine on the cable length, local and remote receiver.
e1000e_get_phy_info_m88 - Retrieve PHY information : pointer to the HW structure
Valid for only copper links. Read the PHY status register (sticky read) to verify that link is up. Read the PHY special control register to determine the polarity and 10base-T extended distance. Read the PHY special status register to determine MDI/MDIx and current speed. If speed is 1000, then determine cable length, local and remote receiver.
| enum e1000_phy_type e1000e_get_phy_type_from_id | ( | u32 | phy_id | ) |
|
read |
e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working : pointer to the HW structure
Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), LPLU, Gig disable, MDIC PHY reset): 1) Set Kumeran Near-end loopback 2) Clear Kumeran Near-end loopback Should only be called for ICH8[m] devices with any 1G Phy.
e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY : pointer to the HW structure
Calls the PHY setup function to force speed and duplex. Clears the auto-crossover to force MDI manually. Resets the PHY to commit the changes. If time expires while waiting for link up, we reset the DSP. After reset, TX_CLK and CRS on Tx must be set. Return successful upon successful completion, else return corresponding error code.
e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex : pointer to the HW structure : pointer to current value of PHY_CONTROL
Forces speed and duplex on the PHY by doing the following: disable flow control, force speed/duplex on the MAC, disable auto speed detection, disable auto-negotiation, configure duplex, configure speed, configure the collision distance, write configuration to CTRL register. The caller must write to the PHY_CONTROL register for these settings to take affect.
| s32 e1000e_phy_has_link_generic | ( | struct e1000_hw * | hw, |
| u32 | iterations, | ||
| u32 | usec_interval, | ||
| bool * | success | ||
| ) |
e1000e_phy_hw_reset_generic - PHY hardware reset : pointer to the HW structure
Verify the reset block is not blocking us from resetting. Acquire semaphore (if necessary) and read/set/write the device control reset bit in the PHY. Wait the appropriate delay time for the device to reset and release the semaphore (if necessary).
| void e1000e_power_up_phy | ( | struct e1000_adapter * | adapter | ) |
e1000e_power_up_phy - restore link in case the phy was powered down : address of board private structure
The phy may be powered down to save power and turn off link when the driver is unloaded and wake on lan is not enabled (among others) *** this routine MUST be followed by a call to e1000e_reset ***
e1000e_read_kmrn_reg - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore then reads the PHY register at offset using the kumeran interface. The information retrieved is stored in data. Release the acquired semaphore before exiting.
e1000e_read_phy_reg_m88 - Read m88 PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary, then reads the PHY register at offset and storing the retrieved information in data. Release any acquired semaphores before exiting.
| void e1000e_reinit_locked | ( | struct e1000_adapter * | adapter | ) |
| void e1000e_release_hw_control | ( | struct e1000_adapter * | adapter | ) |
e1000e_release_hw_control - release control of the h/w to f/w : address of board private structure
e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. For ASF and Pass Through versions of f/w this means that the driver is no longer loaded. For AMT version (only with 82573) i of the f/w this means that the network i/f is closed.
| void e1000e_reset | ( | struct e1000_adapter * | adapter | ) |
| void e1000e_reset_interrupt_capability | ( | struct e1000_adapter * | adapter | ) |
e1000e_set_d3_lplu_state - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu
Success returns 0, Failure returns 1
The low power link up (lplu) state is set to the power management level D3 and SmartSpeed is disabled when active is true, else clear lplu for D3 and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU is used during Dx states where the power conservation is most important. During driver activity, SmartSpeed should be enabled so performance is maintained.
| void e1000e_set_ethtool_ops | ( | struct net_device * | netdev | ) |
| void e1000e_set_interrupt_capability | ( | struct e1000_adapter * | adapter | ) |
e1000e_setup_copper_link - Configure copper link settings : pointer to the HW structure
Calls the appropriate function to configure the link for auto-neg or forced speed and duplex. Then we check for link, once link is established calls to configure collision distance and flow control are called. If link is not established, we return -E1000_ERR_PHY (-2).
e1000e_setup_link_generic - Setup flow control and link settings : pointer to the HW structure
Determines which flow control settings to use, then configures flow control. Calls the appropriate media-specific link configuration function. Assuming the adapter has a valid link partner, a valid link should be established. Assumes the hardware has previously been reset and the transmitter and receiver are not enabled.
| int e1000e_setup_rx_resources | ( | struct e1000_ring * | rx_ring | ) |
| int e1000e_setup_tx_resources | ( | struct e1000_ring * | tx_ring | ) |
| int e1000e_up | ( | struct e1000_adapter * | adapter | ) |
| void e1000e_update_mc_addr_list_generic | ( | struct e1000_hw * | hw, |
| u8 * | mc_addr_list, | ||
| u32 | mc_addr_count | ||
| ) |
| void e1000e_write_itr | ( | struct e1000_adapter * | adapter, |
| u32 | itr | ||
| ) |
e1000e_write_itr - write the ITR value to the appropriate registers : address of board private structure : new ITR value to program
e1000e_write_itr determines if the adapter is in MSI-X mode and, if so, writes the EITR registers with the ITR value. Otherwise, it writes the ITR value into the ITR register.
e1000e_write_nvm_spi - Write to EEPROM using SPI : pointer to the HW structure : offset within the EEPROM to be written to : number of words to write : 16 bit word(s) to be written to the EEPROM
Writes data to EEPROM at offset using SPI interface.
If e1000e_update_nvm_checksum is not called after this function , the EEPROM will most likely contain an invalid checksum.
e1000e_write_protect_nvm_ich8lan - Make the NVM read-only : pointer to the HW structure
To prevent malicious write/erase of the NVM, set it to be read-only so that the hardware ignores all write/erase cycles of the NVM via the flash control registers. The shadow-ram copy of the NVM will still be updated, however any updates to this copy will not stick across driver reloads.
| struct e1000_info e1000_82571_info |
| struct e1000_info e1000_82572_info |
| struct e1000_info e1000_82573_info |
| struct e1000_info e1000_82574_info |
| struct e1000_info e1000_82583_info |
| struct e1000_info e1000_es2_info |
Definition at line 1478 of file 80003es2lan.c.
| struct e1000_info e1000_ich10_info |
| struct e1000_info e1000_ich8_info |
| struct e1000_info e1000_ich9_info |
| struct e1000_info e1000_pch2_info |
| struct e1000_info e1000_pch_info |
| struct e1000_info e1000_pch_lpt_info |
1.8.2