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ni_65xx.c
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1 /*
2  comedi/drivers/ni_6514.c
3  driver for National Instruments PCI-6514
4 
5  Copyright (C) 2006 Jon Grierson <[email protected]>
6  Copyright (C) 2006 Frank Mori Hess <[email protected]>
7 
8  COMEDI - Linux Control and Measurement Device Interface
9  Copyright (C) 1999,2002,2003 David A. Schleef <[email protected]>
10 
11  This program is free software; you can redistribute it and/or modify
12  it under the terms of the GNU General Public License as published by
13  the Free Software Foundation; either version 2 of the License, or
14  (at your option) any later version.
15 
16  This program is distributed in the hope that it will be useful,
17  but WITHOUT ANY WARRANTY; without even the implied warranty of
18  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  GNU General Public License for more details.
20 
21  You should have received a copy of the GNU General Public License
22  along with this program; if not, write to the Free Software
23  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 
25 */
26 /*
27 Driver: ni_65xx
28 Description: National Instruments 65xx static dio boards
29 Author: Jon Grierson <[email protected]>,
30  Frank Mori Hess <[email protected]>
31 Status: testing
32 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
33  PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
34  PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
35  PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
36 Updated: Wed Oct 18 08:59:11 EDT 2006
37 
38 Based on the PCI-6527 driver by ds.
39 The interrupt subdevice (subdevice 3) is probably broken for all boards
40 except maybe the 6514.
41 
42 */
43 
44 /*
45  Manuals (available from ftp://ftp.natinst.com/support/manuals)
46 
47  370106b.pdf 6514 Register Level Programmer Manual
48 
49  */
50 
51 #define _GNU_SOURCE
52 #define DEBUG 1
53 #define DEBUG_FLAGS
54 #include <linux/interrupt.h>
55 #include <linux/slab.h>
56 #include "../comedidev.h"
57 
58 #include "comedi_fc.h"
59 #include "mite.h"
60 
61 #define NI6514_DIO_SIZE 4096
62 #define NI6514_MITE_SIZE 4096
63 
64 #define NI_65XX_MAX_NUM_PORTS 12
65 static const unsigned ni_65xx_channels_per_port = 8;
66 static const unsigned ni_65xx_port_offset = 0x10;
67 
68 static inline unsigned Port_Data(unsigned port)
69 {
70  return 0x40 + port * ni_65xx_port_offset;
71 }
72 
73 static inline unsigned Port_Select(unsigned port)
74 {
75  return 0x41 + port * ni_65xx_port_offset;
76 }
77 
78 static inline unsigned Rising_Edge_Detection_Enable(unsigned port)
79 {
80  return 0x42 + port * ni_65xx_port_offset;
81 }
82 
83 static inline unsigned Falling_Edge_Detection_Enable(unsigned port)
84 {
85  return 0x43 + port * ni_65xx_port_offset;
86 }
87 
88 static inline unsigned Filter_Enable(unsigned port)
89 {
90  return 0x44 + port * ni_65xx_port_offset;
91 }
92 
93 #define ID_Register 0x00
94 
95 #define Clear_Register 0x01
96 #define ClrEdge 0x08
97 #define ClrOverflow 0x04
98 
99 #define Filter_Interval 0x08
100 
101 #define Change_Status 0x02
102 #define MasterInterruptStatus 0x04
103 #define Overflow 0x02
104 #define EdgeStatus 0x01
105 
106 #define Master_Interrupt_Control 0x03
107 #define FallingEdgeIntEnable 0x10
108 #define RisingEdgeIntEnable 0x08
109 #define MasterInterruptEnable 0x04
110 #define OverflowIntEnable 0x02
111 #define EdgeIntEnable 0x01
112 
113 struct ni_65xx_board {
114  int dev_id;
115  const char *name;
116  unsigned num_dio_ports;
117  unsigned num_di_ports;
118  unsigned num_do_ports;
119  unsigned invert_outputs:1;
120 };
121 
122 static const struct ni_65xx_board ni_65xx_boards[] = {
123  {
124  .dev_id = 0x7085,
125  .name = "pci-6509",
126  .num_dio_ports = 12,
127  .invert_outputs = 0},
128  {
129  .dev_id = 0x1710,
130  .name = "pxi-6509",
131  .num_dio_ports = 12,
132  .invert_outputs = 0},
133  {
134  .dev_id = 0x7124,
135  .name = "pci-6510",
136  .num_di_ports = 4},
137  {
138  .dev_id = 0x70c3,
139  .name = "pci-6511",
140  .num_di_ports = 8},
141  {
142  .dev_id = 0x70d3,
143  .name = "pxi-6511",
144  .num_di_ports = 8},
145  {
146  .dev_id = 0x70cc,
147  .name = "pci-6512",
148  .num_do_ports = 8},
149  {
150  .dev_id = 0x70d2,
151  .name = "pxi-6512",
152  .num_do_ports = 8},
153  {
154  .dev_id = 0x70c8,
155  .name = "pci-6513",
156  .num_do_ports = 8,
157  .invert_outputs = 1},
158  {
159  .dev_id = 0x70d1,
160  .name = "pxi-6513",
161  .num_do_ports = 8,
162  .invert_outputs = 1},
163  {
164  .dev_id = 0x7088,
165  .name = "pci-6514",
166  .num_di_ports = 4,
167  .num_do_ports = 4,
168  .invert_outputs = 1},
169  {
170  .dev_id = 0x70CD,
171  .name = "pxi-6514",
172  .num_di_ports = 4,
173  .num_do_ports = 4,
174  .invert_outputs = 1},
175  {
176  .dev_id = 0x7087,
177  .name = "pci-6515",
178  .num_di_ports = 4,
179  .num_do_ports = 4,
180  .invert_outputs = 1},
181  {
182  .dev_id = 0x70c9,
183  .name = "pxi-6515",
184  .num_di_ports = 4,
185  .num_do_ports = 4,
186  .invert_outputs = 1},
187  {
188  .dev_id = 0x7125,
189  .name = "pci-6516",
190  .num_do_ports = 4,
191  .invert_outputs = 1},
192  {
193  .dev_id = 0x7126,
194  .name = "pci-6517",
195  .num_do_ports = 4,
196  .invert_outputs = 1},
197  {
198  .dev_id = 0x7127,
199  .name = "pci-6518",
200  .num_di_ports = 2,
201  .num_do_ports = 2,
202  .invert_outputs = 1},
203  {
204  .dev_id = 0x7128,
205  .name = "pci-6519",
206  .num_di_ports = 2,
207  .num_do_ports = 2,
208  .invert_outputs = 1},
209  {
210  .dev_id = 0x71c5,
211  .name = "pci-6520",
212  .num_di_ports = 1,
213  .num_do_ports = 1,
214  },
215  {
216  .dev_id = 0x718b,
217  .name = "pci-6521",
218  .num_di_ports = 1,
219  .num_do_ports = 1,
220  },
221  {
222  .dev_id = 0x718c,
223  .name = "pxi-6521",
224  .num_di_ports = 1,
225  .num_do_ports = 1,
226  },
227  {
228  .dev_id = 0x70a9,
229  .name = "pci-6528",
230  .num_di_ports = 3,
231  .num_do_ports = 3,
232  },
233  {
234  .dev_id = 0x7086,
235  .name = "pxi-6528",
236  .num_di_ports = 3,
237  .num_do_ports = 3,
238  },
239 };
240 
241 #define n_ni_65xx_boards ARRAY_SIZE(ni_65xx_boards)
242 static inline const struct ni_65xx_board *board(struct comedi_device *dev)
243 {
244  return dev->board_ptr;
245 }
246 
247 static inline unsigned ni_65xx_port_by_channel(unsigned channel)
248 {
249  return channel / ni_65xx_channels_per_port;
250 }
251 
252 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
253  *board)
254 {
255  return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
256 }
257 
258 static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table) = {
259  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1710)},
260  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7085)},
261  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7086)},
262  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7087)},
263  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7088)},
264  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70a9)},
265  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c3)},
266  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c8)},
267  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c9)},
268  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70cc)},
269  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70CD)},
270  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70d1)},
271  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70d2)},
272  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70d3)},
273  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7124)},
274  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7125)},
275  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7126)},
276  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7127)},
277  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7128)},
278  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x718b)},
279  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x718c)},
280  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x71c5)},
281  {0}
282 };
283 
284 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
285 
286 struct ni_65xx_private {
287  struct mite_struct *mite;
288  unsigned int filter_interval;
289  unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
290  unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
291  unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
292 };
293 
294 static inline struct ni_65xx_private *private(struct comedi_device *dev)
295 {
296  return dev->private;
297 }
298 
299 struct ni_65xx_subdevice_private {
300  unsigned base_port;
301 };
302 
303 static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice
304  *subdev)
305 {
306  return subdev->private;
307 }
308 
309 static struct ni_65xx_subdevice_private *ni_65xx_alloc_subdevice_private(void)
310 {
311  struct ni_65xx_subdevice_private *subdev_private =
312  kzalloc(sizeof(struct ni_65xx_subdevice_private), GFP_KERNEL);
313  if (subdev_private == NULL)
314  return NULL;
315  return subdev_private;
316 }
317 
318 static int ni_65xx_config_filter(struct comedi_device *dev,
319  struct comedi_subdevice *s,
320  struct comedi_insn *insn, unsigned int *data)
321 {
322  const unsigned chan = CR_CHAN(insn->chanspec);
323  const unsigned port =
324  sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
325 
326  if (data[0] != INSN_CONFIG_FILTER)
327  return -EINVAL;
328  if (data[1]) {
329  static const unsigned filter_resolution_ns = 200;
330  static const unsigned max_filter_interval = 0xfffff;
331  unsigned interval =
332  (data[1] +
333  (filter_resolution_ns / 2)) / filter_resolution_ns;
334  if (interval > max_filter_interval)
335  interval = max_filter_interval;
336  data[1] = interval * filter_resolution_ns;
337 
338  if (interval != private(dev)->filter_interval) {
339  writeb(interval,
340  private(dev)->mite->daq_io_addr +
341  Filter_Interval);
342  private(dev)->filter_interval = interval;
343  }
344 
345  private(dev)->filter_enable[port] |=
346  1 << (chan % ni_65xx_channels_per_port);
347  } else {
348  private(dev)->filter_enable[port] &=
349  ~(1 << (chan % ni_65xx_channels_per_port));
350  }
351 
352  writeb(private(dev)->filter_enable[port],
353  private(dev)->mite->daq_io_addr + Filter_Enable(port));
354 
355  return 2;
356 }
357 
358 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
359  struct comedi_subdevice *s,
360  struct comedi_insn *insn, unsigned int *data)
361 {
362  unsigned port;
363 
364  if (insn->n < 1)
365  return -EINVAL;
366  port = sprivate(s)->base_port +
367  ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
368  switch (data[0]) {
369  case INSN_CONFIG_FILTER:
370  return ni_65xx_config_filter(dev, s, insn, data);
371  break;
372  case INSN_CONFIG_DIO_OUTPUT:
373  if (s->type != COMEDI_SUBD_DIO)
374  return -EINVAL;
375  private(dev)->dio_direction[port] = COMEDI_OUTPUT;
376  writeb(0, private(dev)->mite->daq_io_addr + Port_Select(port));
377  return 1;
378  break;
379  case INSN_CONFIG_DIO_INPUT:
380  if (s->type != COMEDI_SUBD_DIO)
381  return -EINVAL;
382  private(dev)->dio_direction[port] = COMEDI_INPUT;
383  writeb(1, private(dev)->mite->daq_io_addr + Port_Select(port));
384  return 1;
385  break;
386  case INSN_CONFIG_DIO_QUERY:
387  if (s->type != COMEDI_SUBD_DIO)
388  return -EINVAL;
389  data[1] = private(dev)->dio_direction[port];
390  return insn->n;
391  break;
392  default:
393  break;
394  }
395  return -EINVAL;
396 }
397 
398 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
399  struct comedi_subdevice *s,
400  struct comedi_insn *insn, unsigned int *data)
401 {
402  unsigned base_bitfield_channel;
403  const unsigned max_ports_per_bitfield = 5;
404  unsigned read_bits = 0;
405  unsigned j;
406 
407  base_bitfield_channel = CR_CHAN(insn->chanspec);
408  for (j = 0; j < max_ports_per_bitfield; ++j) {
409  const unsigned port_offset =
410  ni_65xx_port_by_channel(base_bitfield_channel) + j;
411  const unsigned port =
412  sprivate(s)->base_port + port_offset;
413  unsigned base_port_channel;
414  unsigned port_mask, port_data, port_read_bits;
415  int bitshift;
416  if (port >= ni_65xx_total_num_ports(board(dev)))
417  break;
418  base_port_channel = port_offset * ni_65xx_channels_per_port;
419  port_mask = data[0];
420  port_data = data[1];
421  bitshift = base_port_channel - base_bitfield_channel;
422  if (bitshift >= 32 || bitshift <= -32)
423  break;
424  if (bitshift > 0) {
425  port_mask >>= bitshift;
426  port_data >>= bitshift;
427  } else {
428  port_mask <<= -bitshift;
429  port_data <<= -bitshift;
430  }
431  port_mask &= 0xff;
432  port_data &= 0xff;
433  if (port_mask) {
434  unsigned bits;
435  private(dev)->output_bits[port] &= ~port_mask;
436  private(dev)->output_bits[port] |=
437  port_data & port_mask;
438  bits = private(dev)->output_bits[port];
439  if (board(dev)->invert_outputs)
440  bits = ~bits;
441  writeb(bits,
442  private(dev)->mite->daq_io_addr +
443  Port_Data(port));
444  }
445  port_read_bits =
446  readb(private(dev)->mite->daq_io_addr + Port_Data(port));
447  if (s->type == COMEDI_SUBD_DO && board(dev)->invert_outputs) {
448  /* Outputs inverted, so invert value read back from
449  * DO subdevice. (Does not apply to boards with DIO
450  * subdevice.) */
451  port_read_bits ^= 0xFF;
452  }
453  if (bitshift > 0)
454  port_read_bits <<= bitshift;
455  else
456  port_read_bits >>= -bitshift;
457 
458  read_bits |= port_read_bits;
459  }
460  data[1] = read_bits;
461  return insn->n;
462 }
463 
464 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
465 {
466  struct comedi_device *dev = d;
467  struct comedi_subdevice *s = &dev->subdevices[2];
468  unsigned int status;
469 
470  status = readb(private(dev)->mite->daq_io_addr + Change_Status);
471  if ((status & MasterInterruptStatus) == 0)
472  return IRQ_NONE;
473  if ((status & EdgeStatus) == 0)
474  return IRQ_NONE;
475 
476  writeb(ClrEdge | ClrOverflow,
477  private(dev)->mite->daq_io_addr + Clear_Register);
478 
479  comedi_buf_put(s->async, 0);
480  s->async->events |= COMEDI_CB_EOS;
481  comedi_event(dev, s);
482  return IRQ_HANDLED;
483 }
484 
485 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
486  struct comedi_subdevice *s,
487  struct comedi_cmd *cmd)
488 {
489  int err = 0;
490 
491  /* Step 1 : check if triggers are trivially valid */
492 
493  err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
494  err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
495  err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
496  err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
497  err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
498 
499  if (err)
500  return 1;
501 
502  /* Step 2a : make sure trigger sources are unique */
503  /* Step 2b : and mutually compatible */
504 
505  if (err)
506  return 2;
507 
508  /* step 3: make sure arguments are trivially compatible */
509 
510  if (cmd->start_arg != 0) {
511  cmd->start_arg = 0;
512  err++;
513  }
514  if (cmd->scan_begin_arg != 0) {
515  cmd->scan_begin_arg = 0;
516  err++;
517  }
518  if (cmd->convert_arg != 0) {
519  cmd->convert_arg = 0;
520  err++;
521  }
522 
523  if (cmd->scan_end_arg != 1) {
524  cmd->scan_end_arg = 1;
525  err++;
526  }
527  if (cmd->stop_arg != 0) {
528  cmd->stop_arg = 0;
529  err++;
530  }
531 
532  if (err)
533  return 3;
534 
535  /* step 4: fix up any arguments */
536 
537  if (err)
538  return 4;
539 
540  return 0;
541 }
542 
543 static int ni_65xx_intr_cmd(struct comedi_device *dev,
544  struct comedi_subdevice *s)
545 {
546  /* struct comedi_cmd *cmd = &s->async->cmd; */
547 
548  writeb(ClrEdge | ClrOverflow,
549  private(dev)->mite->daq_io_addr + Clear_Register);
550  writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
551  MasterInterruptEnable | EdgeIntEnable,
552  private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
553 
554  return 0;
555 }
556 
557 static int ni_65xx_intr_cancel(struct comedi_device *dev,
558  struct comedi_subdevice *s)
559 {
560  writeb(0x00,
561  private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
562 
563  return 0;
564 }
565 
566 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
567  struct comedi_subdevice *s,
568  struct comedi_insn *insn, unsigned int *data)
569 {
570  data[1] = 0;
571  return insn->n;
572 }
573 
574 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
575  struct comedi_subdevice *s,
576  struct comedi_insn *insn,
577  unsigned int *data)
578 {
579  if (insn->n < 1)
580  return -EINVAL;
581  if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
582  return -EINVAL;
583 
584  writeb(data[1],
585  private(dev)->mite->daq_io_addr +
586  Rising_Edge_Detection_Enable(0));
587  writeb(data[1] >> 8,
588  private(dev)->mite->daq_io_addr +
589  Rising_Edge_Detection_Enable(0x10));
590  writeb(data[1] >> 16,
591  private(dev)->mite->daq_io_addr +
592  Rising_Edge_Detection_Enable(0x20));
593  writeb(data[1] >> 24,
594  private(dev)->mite->daq_io_addr +
595  Rising_Edge_Detection_Enable(0x30));
596 
597  writeb(data[2],
598  private(dev)->mite->daq_io_addr +
599  Falling_Edge_Detection_Enable(0));
600  writeb(data[2] >> 8,
601  private(dev)->mite->daq_io_addr +
602  Falling_Edge_Detection_Enable(0x10));
603  writeb(data[2] >> 16,
604  private(dev)->mite->daq_io_addr +
605  Falling_Edge_Detection_Enable(0x20));
606  writeb(data[2] >> 24,
607  private(dev)->mite->daq_io_addr +
608  Falling_Edge_Detection_Enable(0x30));
609 
610  return 2;
611 }
612 
613 static const struct ni_65xx_board *
614 ni_65xx_find_boardinfo(struct pci_dev *pcidev)
615 {
616  unsigned int dev_id = pcidev->device;
617  unsigned int n;
618 
619  for (n = 0; n < ARRAY_SIZE(ni_65xx_boards); n++) {
620  const struct ni_65xx_board *board = &ni_65xx_boards[n];
621  if (board->dev_id == dev_id)
622  return board;
623  }
624  return NULL;
625 }
626 
627 static int __devinit ni_65xx_attach_pci(struct comedi_device *dev,
628  struct pci_dev *pcidev)
629 {
630  struct comedi_subdevice *s;
631  unsigned i;
632  int ret;
633 
634  ret = alloc_private(dev, sizeof(struct ni_65xx_private));
635  if (ret < 0)
636  return ret;
637 
638  dev->board_ptr = ni_65xx_find_boardinfo(pcidev);
639  if (!dev->board_ptr)
640  return -ENODEV;
641 
642  private(dev)->mite = mite_alloc(pcidev);
643  if (!private(dev)->mite)
644  return -ENOMEM;
645 
646  ret = mite_setup(private(dev)->mite);
647  if (ret < 0) {
648  dev_warn(dev->class_dev, "error setting up mite\n");
649  return ret;
650  }
651 
652  dev->board_name = board(dev)->name;
653  dev->irq = mite_irq(private(dev)->mite);
654  dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
655  readb(private(dev)->mite->daq_io_addr + ID_Register));
656 
657  ret = comedi_alloc_subdevices(dev, 4);
658  if (ret)
659  return ret;
660 
661  s = &dev->subdevices[0];
662  if (board(dev)->num_di_ports) {
663  s->type = COMEDI_SUBD_DI;
664  s->subdev_flags = SDF_READABLE;
665  s->n_chan =
666  board(dev)->num_di_ports * ni_65xx_channels_per_port;
667  s->range_table = &range_digital;
668  s->maxdata = 1;
669  s->insn_config = ni_65xx_dio_insn_config;
670  s->insn_bits = ni_65xx_dio_insn_bits;
671  s->private = ni_65xx_alloc_subdevice_private();
672  if (s->private == NULL)
673  return -ENOMEM;
674  sprivate(s)->base_port = 0;
675  } else {
676  s->type = COMEDI_SUBD_UNUSED;
677  }
678 
679  s = &dev->subdevices[1];
680  if (board(dev)->num_do_ports) {
681  s->type = COMEDI_SUBD_DO;
682  s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
683  s->n_chan =
684  board(dev)->num_do_ports * ni_65xx_channels_per_port;
685  s->range_table = &range_digital;
686  s->maxdata = 1;
687  s->insn_bits = ni_65xx_dio_insn_bits;
688  s->private = ni_65xx_alloc_subdevice_private();
689  if (s->private == NULL)
690  return -ENOMEM;
691  sprivate(s)->base_port = board(dev)->num_di_ports;
692  } else {
693  s->type = COMEDI_SUBD_UNUSED;
694  }
695 
696  s = &dev->subdevices[2];
697  if (board(dev)->num_dio_ports) {
698  s->type = COMEDI_SUBD_DIO;
699  s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
700  s->n_chan =
701  board(dev)->num_dio_ports * ni_65xx_channels_per_port;
702  s->range_table = &range_digital;
703  s->maxdata = 1;
704  s->insn_config = ni_65xx_dio_insn_config;
705  s->insn_bits = ni_65xx_dio_insn_bits;
706  s->private = ni_65xx_alloc_subdevice_private();
707  if (s->private == NULL)
708  return -ENOMEM;
709  sprivate(s)->base_port = 0;
710  for (i = 0; i < board(dev)->num_dio_ports; ++i) {
711  /* configure all ports for input */
712  writeb(0x1,
713  private(dev)->mite->daq_io_addr +
714  Port_Select(i));
715  }
716  } else {
717  s->type = COMEDI_SUBD_UNUSED;
718  }
719 
720  s = &dev->subdevices[3];
721  dev->read_subdev = s;
722  s->type = COMEDI_SUBD_DI;
723  s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
724  s->n_chan = 1;
725  s->range_table = &range_unknown;
726  s->maxdata = 1;
727  s->do_cmdtest = ni_65xx_intr_cmdtest;
728  s->do_cmd = ni_65xx_intr_cmd;
729  s->cancel = ni_65xx_intr_cancel;
730  s->insn_bits = ni_65xx_intr_insn_bits;
731  s->insn_config = ni_65xx_intr_insn_config;
732 
733  for (i = 0; i < ni_65xx_total_num_ports(board(dev)); ++i) {
734  writeb(0x00,
735  private(dev)->mite->daq_io_addr + Filter_Enable(i));
736  if (board(dev)->invert_outputs)
737  writeb(0x01,
738  private(dev)->mite->daq_io_addr + Port_Data(i));
739  else
740  writeb(0x00,
741  private(dev)->mite->daq_io_addr + Port_Data(i));
742  }
743  writeb(ClrEdge | ClrOverflow,
744  private(dev)->mite->daq_io_addr + Clear_Register);
745  writeb(0x00,
746  private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
747 
748  /* Set filter interval to 0 (32bit reg) */
749  writeb(0x00000000, private(dev)->mite->daq_io_addr + Filter_Interval);
750 
751  ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
752  "ni_65xx", dev);
753  if (ret < 0) {
754  dev->irq = 0;
755  dev_warn(dev->class_dev, "irq not available\n");
756  }
757 
758  return 0;
759 }
760 
761 static void ni_65xx_detach(struct comedi_device *dev)
762 {
763  if (private(dev) && private(dev)->mite
764  && private(dev)->mite->daq_io_addr) {
765  writeb(0x00,
766  private(dev)->mite->daq_io_addr +
767  Master_Interrupt_Control);
768  }
769  if (dev->irq)
770  free_irq(dev->irq, dev);
771  if (private(dev)) {
772  struct comedi_subdevice *s;
773  unsigned i;
774 
775  for (i = 0; i < dev->n_subdevices; ++i) {
776  s = &dev->subdevices[i];
777  kfree(s->private);
778  s->private = NULL;
779  }
780  if (private(dev)->mite) {
781  mite_unsetup(private(dev)->mite);
782  mite_free(private(dev)->mite);
783  }
784  }
785 }
786 
787 static struct comedi_driver ni_65xx_driver = {
788  .driver_name = "ni_65xx",
789  .module = THIS_MODULE,
790  .attach_pci = ni_65xx_attach_pci,
791  .detach = ni_65xx_detach,
792 };
793 
794 static int __devinit ni_65xx_pci_probe(struct pci_dev *dev,
795  const struct pci_device_id *ent)
796 {
797  return comedi_pci_auto_config(dev, &ni_65xx_driver);
798 }
799 
800 static void __devexit ni_65xx_pci_remove(struct pci_dev *dev)
801 {
802  comedi_pci_auto_unconfig(dev);
803 }
804 
805 static struct pci_driver ni_65xx_pci_driver = {
806  .name = "ni_65xx",
807  .id_table = ni_65xx_pci_table,
808  .probe = ni_65xx_pci_probe,
809  .remove = __devexit_p(ni_65xx_pci_remove)
810 };
811 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
812 
813 MODULE_AUTHOR("Comedi http://www.comedi.org");
814 MODULE_DESCRIPTION("Comedi low-level driver");
815 MODULE_LICENSE("GPL");
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