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ni_660x.c
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1 /*
2  comedi/drivers/ni_660x.c
3  Hardware driver for NI 660x devices
4 
5  This program is free software; you can redistribute it and/or modify
6  it under the terms of the GNU General Public License as published by
7  the Free Software Foundation; either version 2 of the License, or
8  (at your option) any later version.
9 
10  This program is distributed in the hope that it will be useful,
11  but WITHOUT ANY WARRANTY; without even the implied warranty of
12  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  GNU General Public License for more details.
14 
15  You should have received a copy of the GNU General Public License
16  along with this program; if not, write to the Free Software
17  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19 
20 /*
21 Driver: ni_660x
22 Description: National Instruments 660x counter/timer boards
23 Devices:
24 [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
25  PXI-6608
26 Author: J.P. Mellor <[email protected]>,
27  [email protected],
28  [email protected],
29  [email protected],
30  Frank Mori Hess <[email protected]>
31 Updated: Thu Oct 18 12:56:06 EDT 2007
32 Status: experimental
33 
34 Encoders work. PulseGeneration (both single pulse and pulse train)
35 works. Buffered commands work for input but not output.
36 
37 References:
38 DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
39 DAQ 6601/6602 User Manual (NI 322137B-01)
40 
41 */
42 
43 #include <linux/interrupt.h>
44 #include "../comedidev.h"
45 #include "mite.h"
46 #include "ni_tio.h"
47 
48 enum ni_660x_constants {
49  min_counter_pfi_chan = 8,
50  max_dio_pfi_chan = 31,
51  counters_per_chip = 4
52 };
53 
54 #define NUM_PFI_CHANNELS 40
55 /* really there are only up to 3 dma channels, but the register layout allows
56 for 4 */
57 #define MAX_DMA_CHANNEL 4
58 
59 /* See Register-Level Programmer Manual page 3.1 */
60 enum NI_660x_Register {
61  G0InterruptAcknowledge,
62  G0StatusRegister,
63  G1InterruptAcknowledge,
64  G1StatusRegister,
65  G01StatusRegister,
66  G0CommandRegister,
67  STCDIOParallelInput,
68  G1CommandRegister,
69  G0HWSaveRegister,
70  G1HWSaveRegister,
71  STCDIOOutput,
72  STCDIOControl,
73  G0SWSaveRegister,
74  G1SWSaveRegister,
75  G0ModeRegister,
76  G01JointStatus1Register,
77  G1ModeRegister,
78  STCDIOSerialInput,
79  G0LoadARegister,
80  G01JointStatus2Register,
81  G0LoadBRegister,
82  G1LoadARegister,
83  G1LoadBRegister,
84  G0InputSelectRegister,
85  G1InputSelectRegister,
86  G0AutoincrementRegister,
87  G1AutoincrementRegister,
88  G01JointResetRegister,
89  G0InterruptEnable,
90  G1InterruptEnable,
91  G0CountingModeRegister,
92  G1CountingModeRegister,
93  G0SecondGateRegister,
94  G1SecondGateRegister,
95  G0DMAConfigRegister,
96  G0DMAStatusRegister,
97  G1DMAConfigRegister,
98  G1DMAStatusRegister,
99  G2InterruptAcknowledge,
100  G2StatusRegister,
101  G3InterruptAcknowledge,
102  G3StatusRegister,
103  G23StatusRegister,
104  G2CommandRegister,
105  G3CommandRegister,
106  G2HWSaveRegister,
107  G3HWSaveRegister,
108  G2SWSaveRegister,
109  G3SWSaveRegister,
110  G2ModeRegister,
111  G23JointStatus1Register,
112  G3ModeRegister,
113  G2LoadARegister,
114  G23JointStatus2Register,
115  G2LoadBRegister,
116  G3LoadARegister,
117  G3LoadBRegister,
118  G2InputSelectRegister,
119  G3InputSelectRegister,
120  G2AutoincrementRegister,
121  G3AutoincrementRegister,
122  G23JointResetRegister,
123  G2InterruptEnable,
124  G3InterruptEnable,
125  G2CountingModeRegister,
126  G3CountingModeRegister,
127  G3SecondGateRegister,
128  G2SecondGateRegister,
129  G2DMAConfigRegister,
130  G2DMAStatusRegister,
131  G3DMAConfigRegister,
132  G3DMAStatusRegister,
133  DIO32Input,
134  DIO32Output,
135  ClockConfigRegister,
136  GlobalInterruptStatusRegister,
137  DMAConfigRegister,
138  GlobalInterruptConfigRegister,
139  IOConfigReg0_1,
140  IOConfigReg2_3,
141  IOConfigReg4_5,
142  IOConfigReg6_7,
143  IOConfigReg8_9,
144  IOConfigReg10_11,
145  IOConfigReg12_13,
146  IOConfigReg14_15,
147  IOConfigReg16_17,
148  IOConfigReg18_19,
149  IOConfigReg20_21,
150  IOConfigReg22_23,
151  IOConfigReg24_25,
152  IOConfigReg26_27,
153  IOConfigReg28_29,
154  IOConfigReg30_31,
155  IOConfigReg32_33,
156  IOConfigReg34_35,
157  IOConfigReg36_37,
158  IOConfigReg38_39,
159  NumRegisters,
160 };
161 
162 static inline unsigned IOConfigReg(unsigned pfi_channel)
163 {
164  unsigned reg = IOConfigReg0_1 + pfi_channel / 2;
165  BUG_ON(reg > IOConfigReg38_39);
166  return reg;
167 }
168 
169 enum ni_660x_register_width {
170  DATA_1B,
171  DATA_2B,
172  DATA_4B
173 };
174 
175 enum ni_660x_register_direction {
176  NI_660x_READ,
177  NI_660x_WRITE,
178  NI_660x_READ_WRITE
179 };
180 
181 enum ni_660x_pfi_output_select {
182  pfi_output_select_high_Z = 0,
183  pfi_output_select_counter = 1,
184  pfi_output_select_do = 2,
185  num_pfi_output_selects
186 };
187 
188 enum ni_660x_subdevices {
189  NI_660X_DIO_SUBDEV = 1,
190  NI_660X_GPCT_SUBDEV_0 = 2
191 };
192 static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
193 {
194  return NI_660X_GPCT_SUBDEV_0 + index;
195 }
196 
197 struct NI_660xRegisterData {
198 
199  const char *name; /* Register Name */
200  int offset; /* Offset from base address from GPCT chip */
201  enum ni_660x_register_direction direction;
202  enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */
203 };
204 
205 static const struct NI_660xRegisterData registerData[NumRegisters] = {
206  {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
207  {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
208  {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
209  {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
210  {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
211  {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
212  {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
213  {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
214  {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
215  {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
216  {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
217  {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
218  {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
219  {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
220  {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
221  {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
222  {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
223  {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
224  {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
225  {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
226  {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
227  {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
228  {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
229  {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
230  {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
231  {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
232  {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
233  {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
234  {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
235  {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
236  {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
237  {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
238  {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
239  {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
240  {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
241  {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
242  {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
243  {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
244  {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
245  {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
246  {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
247  {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
248  {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
249  {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
250  {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
251  {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
252  {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
253  {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
254  {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
255  {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
256  {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
257  {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
258  {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
259  {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
260  {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
261  {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
262  {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
263  {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
264  {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
265  {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
266  {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
267  {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
268  {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
269  {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
270  {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
271  {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
272  {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
273  {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
274  {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
275  {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
276  {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
277  {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
278  {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
279  {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
280  {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
281  {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
282  {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
283  {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
284  {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
285  {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
286  {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
287  {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
288  {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
289  {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
290  {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
291  {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
292  {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
293  {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
294  {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
295  {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
296  {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
297  {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
298  {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
299  {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
300  {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
301  {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
302  {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
303  {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
304 };
305 
306 /* kind of ENABLE for the second counter */
307 enum clock_config_register_bits {
308  CounterSwap = 0x1 << 21
309 };
310 
311 /* ioconfigreg */
312 static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
313 {
314  if (pfi_channel % 2)
315  return 0;
316  else
317  return 8;
318 }
319 
320 static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
321 {
322  return 0x3 << ioconfig_bitshift(pfi_channel);
323 }
324 
325 static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
326  unsigned output_select)
327 {
328  return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
329 }
330 
331 static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
332 {
333  return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
334 }
335 
336 static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
337  unsigned input_select)
338 {
339  return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
340 }
341 
342 /* dma configuration register bits */
343 static inline unsigned dma_select_mask(unsigned dma_channel)
344 {
345  BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
346  return 0x1f << (8 * dma_channel);
347 }
348 
349 enum dma_selection {
350  dma_selection_none = 0x1f,
351 };
352 static inline unsigned dma_selection_counter(unsigned counter_index)
353 {
354  BUG_ON(counter_index >= counters_per_chip);
355  return counter_index;
356 }
357 
358 static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
359 {
360  BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
361  return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
362 }
363 
364 static inline unsigned dma_reset_bit(unsigned dma_channel)
365 {
366  BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
367  return 0x80 << (8 * dma_channel);
368 }
369 
370 enum global_interrupt_status_register_bits {
371  Counter_0_Int_Bit = 0x100,
372  Counter_1_Int_Bit = 0x200,
373  Counter_2_Int_Bit = 0x400,
374  Counter_3_Int_Bit = 0x800,
375  Cascade_Int_Bit = 0x20000000,
376  Global_Int_Bit = 0x80000000
377 };
378 
379 enum global_interrupt_config_register_bits {
380  Cascade_Int_Enable_Bit = 0x20000000,
381  Global_Int_Polarity_Bit = 0x40000000,
382  Global_Int_Enable_Bit = 0x80000000
383 };
384 
385 /* Offset of the GPCT chips from the base-address of the card */
386 /* First chip is at base-address + 0x00, etc. */
387 static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
388 
389 /* Board description*/
390 struct ni_660x_board {
391  unsigned short dev_id; /* `lspci` will show you this */
392  const char *name;
393  unsigned n_chips; /* total number of TIO chips */
394 };
395 
396 static const struct ni_660x_board ni_660x_boards[] = {
397  {
398  .dev_id = 0x2c60,
399  .name = "PCI-6601",
400  .n_chips = 1,
401  },
402  {
403  .dev_id = 0x1310,
404  .name = "PCI-6602",
405  .n_chips = 2,
406  },
407  {
408  .dev_id = 0x1360,
409  .name = "PXI-6602",
410  .n_chips = 2,
411  },
412  {
413  .dev_id = 0x2cc0,
414  .name = "PXI-6608",
415  .n_chips = 2,
416  },
417 };
418 
419 #define NI_660X_MAX_NUM_CHIPS 2
420 #define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
421 
422 static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = {
423  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c60)},
424  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1310)},
425  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1360)},
426  {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2cc0)},
427  {0}
428 };
429 
430 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
431 
432 struct ni_660x_private {
433  struct mite_struct *mite;
434  struct ni_gpct_device *counter_dev;
435  uint64_t pfi_direction_bits;
436  struct mite_dma_descriptor_ring
437  *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
438  spinlock_t mite_channel_lock;
439  /* interrupt_lock prevents races between interrupt and comedi_poll */
440  spinlock_t interrupt_lock;
441  unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
442  spinlock_t soft_reg_copy_lock;
443  unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
444 };
445 
446 static inline struct ni_660x_private *private(struct comedi_device *dev)
447 {
448  return dev->private;
449 }
450 
451 /* initialized in ni_660x_attach_pci() */
452 static inline const struct ni_660x_board *board(struct comedi_device *dev)
453 {
454  return dev->board_ptr;
455 }
456 
457 static int ni_660x_attach_pci(struct comedi_device *dev,
458  struct pci_dev *pcidev);
459 static void ni_660x_detach(struct comedi_device *dev);
460 static void init_tio_chip(struct comedi_device *dev, int chipset);
461 static void ni_660x_select_pfi_output(struct comedi_device *dev,
462  unsigned pfi_channel,
463  unsigned output_select);
464 
465 static struct comedi_driver ni_660x_driver = {
466  .driver_name = "ni_660x",
467  .module = THIS_MODULE,
468  .attach_pci = ni_660x_attach_pci,
469  .detach = ni_660x_detach,
470 };
471 
472 static int __devinit ni_660x_pci_probe(struct pci_dev *dev,
473  const struct pci_device_id *ent)
474 {
475  return comedi_pci_auto_config(dev, &ni_660x_driver);
476 }
477 
478 static void __devexit ni_660x_pci_remove(struct pci_dev *dev)
479 {
480  comedi_pci_auto_unconfig(dev);
481 }
482 
483 static struct pci_driver ni_660x_pci_driver = {
484  .name = "ni_660x",
485  .id_table = ni_660x_pci_table,
486  .probe = ni_660x_pci_probe,
487  .remove = __devexit_p(ni_660x_pci_remove)
488 };
489 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
490 
491 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
492  unsigned source);
493 
494 /* Possible instructions for a GPCT */
495 static int ni_660x_GPCT_rinsn(struct comedi_device *dev,
496  struct comedi_subdevice *s,
497  struct comedi_insn *insn, unsigned int *data);
498 static int ni_660x_GPCT_insn_config(struct comedi_device *dev,
499  struct comedi_subdevice *s,
500  struct comedi_insn *insn,
501  unsigned int *data);
502 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
503  struct comedi_subdevice *s,
504  struct comedi_insn *insn, unsigned int *data);
505 
506 /* Possible instructions for Digital IO */
507 static int ni_660x_dio_insn_config(struct comedi_device *dev,
508  struct comedi_subdevice *s,
509  struct comedi_insn *insn,
510  unsigned int *data);
511 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
512  struct comedi_subdevice *s,
513  struct comedi_insn *insn, unsigned int *data);
514 
515 static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
516 {
517  return board(dev)->n_chips * counters_per_chip;
518 }
519 
520 static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg)
521 {
522  enum NI_660x_Register ni_660x_register;
523  switch (reg) {
524  case NITIO_G0_Autoincrement_Reg:
525  ni_660x_register = G0AutoincrementRegister;
526  break;
527  case NITIO_G1_Autoincrement_Reg:
528  ni_660x_register = G1AutoincrementRegister;
529  break;
530  case NITIO_G2_Autoincrement_Reg:
531  ni_660x_register = G2AutoincrementRegister;
532  break;
533  case NITIO_G3_Autoincrement_Reg:
534  ni_660x_register = G3AutoincrementRegister;
535  break;
536  case NITIO_G0_Command_Reg:
537  ni_660x_register = G0CommandRegister;
538  break;
539  case NITIO_G1_Command_Reg:
540  ni_660x_register = G1CommandRegister;
541  break;
542  case NITIO_G2_Command_Reg:
543  ni_660x_register = G2CommandRegister;
544  break;
545  case NITIO_G3_Command_Reg:
546  ni_660x_register = G3CommandRegister;
547  break;
548  case NITIO_G0_HW_Save_Reg:
549  ni_660x_register = G0HWSaveRegister;
550  break;
551  case NITIO_G1_HW_Save_Reg:
552  ni_660x_register = G1HWSaveRegister;
553  break;
554  case NITIO_G2_HW_Save_Reg:
555  ni_660x_register = G2HWSaveRegister;
556  break;
557  case NITIO_G3_HW_Save_Reg:
558  ni_660x_register = G3HWSaveRegister;
559  break;
560  case NITIO_G0_SW_Save_Reg:
561  ni_660x_register = G0SWSaveRegister;
562  break;
563  case NITIO_G1_SW_Save_Reg:
564  ni_660x_register = G1SWSaveRegister;
565  break;
566  case NITIO_G2_SW_Save_Reg:
567  ni_660x_register = G2SWSaveRegister;
568  break;
569  case NITIO_G3_SW_Save_Reg:
570  ni_660x_register = G3SWSaveRegister;
571  break;
572  case NITIO_G0_Mode_Reg:
573  ni_660x_register = G0ModeRegister;
574  break;
575  case NITIO_G1_Mode_Reg:
576  ni_660x_register = G1ModeRegister;
577  break;
578  case NITIO_G2_Mode_Reg:
579  ni_660x_register = G2ModeRegister;
580  break;
581  case NITIO_G3_Mode_Reg:
582  ni_660x_register = G3ModeRegister;
583  break;
584  case NITIO_G0_LoadA_Reg:
585  ni_660x_register = G0LoadARegister;
586  break;
587  case NITIO_G1_LoadA_Reg:
588  ni_660x_register = G1LoadARegister;
589  break;
590  case NITIO_G2_LoadA_Reg:
591  ni_660x_register = G2LoadARegister;
592  break;
593  case NITIO_G3_LoadA_Reg:
594  ni_660x_register = G3LoadARegister;
595  break;
596  case NITIO_G0_LoadB_Reg:
597  ni_660x_register = G0LoadBRegister;
598  break;
599  case NITIO_G1_LoadB_Reg:
600  ni_660x_register = G1LoadBRegister;
601  break;
602  case NITIO_G2_LoadB_Reg:
603  ni_660x_register = G2LoadBRegister;
604  break;
605  case NITIO_G3_LoadB_Reg:
606  ni_660x_register = G3LoadBRegister;
607  break;
608  case NITIO_G0_Input_Select_Reg:
609  ni_660x_register = G0InputSelectRegister;
610  break;
611  case NITIO_G1_Input_Select_Reg:
612  ni_660x_register = G1InputSelectRegister;
613  break;
614  case NITIO_G2_Input_Select_Reg:
615  ni_660x_register = G2InputSelectRegister;
616  break;
617  case NITIO_G3_Input_Select_Reg:
618  ni_660x_register = G3InputSelectRegister;
619  break;
620  case NITIO_G01_Status_Reg:
621  ni_660x_register = G01StatusRegister;
622  break;
623  case NITIO_G23_Status_Reg:
624  ni_660x_register = G23StatusRegister;
625  break;
626  case NITIO_G01_Joint_Reset_Reg:
627  ni_660x_register = G01JointResetRegister;
628  break;
629  case NITIO_G23_Joint_Reset_Reg:
630  ni_660x_register = G23JointResetRegister;
631  break;
632  case NITIO_G01_Joint_Status1_Reg:
633  ni_660x_register = G01JointStatus1Register;
634  break;
635  case NITIO_G23_Joint_Status1_Reg:
636  ni_660x_register = G23JointStatus1Register;
637  break;
638  case NITIO_G01_Joint_Status2_Reg:
639  ni_660x_register = G01JointStatus2Register;
640  break;
641  case NITIO_G23_Joint_Status2_Reg:
642  ni_660x_register = G23JointStatus2Register;
643  break;
644  case NITIO_G0_Counting_Mode_Reg:
645  ni_660x_register = G0CountingModeRegister;
646  break;
647  case NITIO_G1_Counting_Mode_Reg:
648  ni_660x_register = G1CountingModeRegister;
649  break;
650  case NITIO_G2_Counting_Mode_Reg:
651  ni_660x_register = G2CountingModeRegister;
652  break;
653  case NITIO_G3_Counting_Mode_Reg:
654  ni_660x_register = G3CountingModeRegister;
655  break;
656  case NITIO_G0_Second_Gate_Reg:
657  ni_660x_register = G0SecondGateRegister;
658  break;
659  case NITIO_G1_Second_Gate_Reg:
660  ni_660x_register = G1SecondGateRegister;
661  break;
662  case NITIO_G2_Second_Gate_Reg:
663  ni_660x_register = G2SecondGateRegister;
664  break;
665  case NITIO_G3_Second_Gate_Reg:
666  ni_660x_register = G3SecondGateRegister;
667  break;
668  case NITIO_G0_DMA_Config_Reg:
669  ni_660x_register = G0DMAConfigRegister;
670  break;
671  case NITIO_G0_DMA_Status_Reg:
672  ni_660x_register = G0DMAStatusRegister;
673  break;
674  case NITIO_G1_DMA_Config_Reg:
675  ni_660x_register = G1DMAConfigRegister;
676  break;
677  case NITIO_G1_DMA_Status_Reg:
678  ni_660x_register = G1DMAStatusRegister;
679  break;
680  case NITIO_G2_DMA_Config_Reg:
681  ni_660x_register = G2DMAConfigRegister;
682  break;
683  case NITIO_G2_DMA_Status_Reg:
684  ni_660x_register = G2DMAStatusRegister;
685  break;
686  case NITIO_G3_DMA_Config_Reg:
687  ni_660x_register = G3DMAConfigRegister;
688  break;
689  case NITIO_G3_DMA_Status_Reg:
690  ni_660x_register = G3DMAStatusRegister;
691  break;
692  case NITIO_G0_Interrupt_Acknowledge_Reg:
693  ni_660x_register = G0InterruptAcknowledge;
694  break;
695  case NITIO_G1_Interrupt_Acknowledge_Reg:
696  ni_660x_register = G1InterruptAcknowledge;
697  break;
698  case NITIO_G2_Interrupt_Acknowledge_Reg:
699  ni_660x_register = G2InterruptAcknowledge;
700  break;
701  case NITIO_G3_Interrupt_Acknowledge_Reg:
702  ni_660x_register = G3InterruptAcknowledge;
703  break;
704  case NITIO_G0_Status_Reg:
705  ni_660x_register = G0StatusRegister;
706  break;
707  case NITIO_G1_Status_Reg:
708  ni_660x_register = G1StatusRegister;
709  break;
710  case NITIO_G2_Status_Reg:
711  ni_660x_register = G2StatusRegister;
712  break;
713  case NITIO_G3_Status_Reg:
714  ni_660x_register = G3StatusRegister;
715  break;
716  case NITIO_G0_Interrupt_Enable_Reg:
717  ni_660x_register = G0InterruptEnable;
718  break;
719  case NITIO_G1_Interrupt_Enable_Reg:
720  ni_660x_register = G1InterruptEnable;
721  break;
722  case NITIO_G2_Interrupt_Enable_Reg:
723  ni_660x_register = G2InterruptEnable;
724  break;
725  case NITIO_G3_Interrupt_Enable_Reg:
726  ni_660x_register = G3InterruptEnable;
727  break;
728  default:
729  BUG();
730  return 0;
731  break;
732  }
733  return ni_660x_register;
734 }
735 
736 static inline void ni_660x_write_register(struct comedi_device *dev,
737  unsigned chip_index, unsigned bits,
738  enum NI_660x_Register reg)
739 {
740  void __iomem *write_address =
741  private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
742  registerData[reg].offset;
743 
744  switch (registerData[reg].size) {
745  case DATA_2B:
746  writew(bits, write_address);
747  break;
748  case DATA_4B:
749  writel(bits, write_address);
750  break;
751  default:
752  BUG();
753  break;
754  }
755 }
756 
757 static inline unsigned ni_660x_read_register(struct comedi_device *dev,
758  unsigned chip_index,
759  enum NI_660x_Register reg)
760 {
761  void __iomem *read_address =
762  private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
763  registerData[reg].offset;
764 
765  switch (registerData[reg].size) {
766  case DATA_2B:
767  return readw(read_address);
768  break;
769  case DATA_4B:
770  return readl(read_address);
771  break;
772  default:
773  BUG();
774  break;
775  }
776  return 0;
777 }
778 
779 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
780  enum ni_gpct_register reg)
781 {
782  struct comedi_device *dev = counter->counter_dev->dev;
783  enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
784  ni_660x_write_register(dev, counter->chip_index, bits,
785  ni_660x_register);
786 }
787 
788 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
789  enum ni_gpct_register reg)
790 {
791  struct comedi_device *dev = counter->counter_dev->dev;
792  enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
793  return ni_660x_read_register(dev, counter->chip_index,
794  ni_660x_register);
795 }
796 
797 static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
798  *priv,
799  struct ni_gpct
800  *counter)
801 {
802  return priv->mite_rings[counter->chip_index][counter->counter_index];
803 }
804 
805 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
806  unsigned mite_channel,
807  struct ni_gpct *counter)
808 {
809  unsigned long flags;
810  spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags);
811  private(dev)->dma_configuration_soft_copies[counter->chip_index] &=
812  ~dma_select_mask(mite_channel);
813  private(dev)->dma_configuration_soft_copies[counter->chip_index] |=
814  dma_select_bits(mite_channel,
815  dma_selection_counter(counter->counter_index));
816  ni_660x_write_register(dev, counter->chip_index,
817  private(dev)->
818  dma_configuration_soft_copies
819  [counter->chip_index] |
820  dma_reset_bit(mite_channel), DMAConfigRegister);
821  mmiowb();
822  spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags);
823 }
824 
825 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
826  unsigned mite_channel,
827  struct ni_gpct *counter)
828 {
829  unsigned long flags;
830  spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags);
831  private(dev)->dma_configuration_soft_copies[counter->chip_index] &=
832  ~dma_select_mask(mite_channel);
833  private(dev)->dma_configuration_soft_copies[counter->chip_index] |=
834  dma_select_bits(mite_channel, dma_selection_none);
835  ni_660x_write_register(dev, counter->chip_index,
836  private(dev)->
837  dma_configuration_soft_copies
838  [counter->chip_index], DMAConfigRegister);
839  mmiowb();
840  spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags);
841 }
842 
843 static int ni_660x_request_mite_channel(struct comedi_device *dev,
844  struct ni_gpct *counter,
845  enum comedi_io_direction direction)
846 {
847  unsigned long flags;
848  struct mite_channel *mite_chan;
849 
850  spin_lock_irqsave(&private(dev)->mite_channel_lock, flags);
851  BUG_ON(counter->mite_chan);
852  mite_chan =
853  mite_request_channel(private(dev)->mite, mite_ring(private(dev),
854  counter));
855  if (mite_chan == NULL) {
856  spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags);
857  comedi_error(dev,
858  "failed to reserve mite dma channel for counter.");
859  return -EBUSY;
860  }
861  mite_chan->dir = direction;
862  ni_tio_set_mite_channel(counter, mite_chan);
863  ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
864  spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags);
865  return 0;
866 }
867 
868 static void ni_660x_release_mite_channel(struct comedi_device *dev,
869  struct ni_gpct *counter)
870 {
871  unsigned long flags;
872 
873  spin_lock_irqsave(&private(dev)->mite_channel_lock, flags);
874  if (counter->mite_chan) {
875  struct mite_channel *mite_chan = counter->mite_chan;
876 
877  ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
878  ni_tio_set_mite_channel(counter, NULL);
879  mite_release_channel(mite_chan);
880  }
881  spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags);
882 }
883 
884 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
885 {
886  int retval;
887 
888  struct ni_gpct *counter = subdev_to_counter(s);
889 /* const struct comedi_cmd *cmd = &s->async->cmd; */
890 
891  retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
892  if (retval) {
893  comedi_error(dev,
894  "no dma channel available for use by counter");
895  return retval;
896  }
897  ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
898  retval = ni_tio_cmd(counter, s->async);
899 
900  return retval;
901 }
902 
903 static int ni_660x_cmdtest(struct comedi_device *dev,
904  struct comedi_subdevice *s, struct comedi_cmd *cmd)
905 {
906  struct ni_gpct *counter = subdev_to_counter(s);
907 
908  return ni_tio_cmdtest(counter, cmd);
909 }
910 
911 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
912 {
913  struct ni_gpct *counter = subdev_to_counter(s);
914  int retval;
915 
916  retval = ni_tio_cancel(counter);
917  ni_660x_release_mite_channel(dev, counter);
918  return retval;
919 }
920 
921 static void set_tio_counterswap(struct comedi_device *dev, int chipset)
922 {
923  /* See P. 3.5 of the Register-Level Programming manual. The
924  CounterSwap bit has to be set on the second chip, otherwise
925  it will try to use the same pins as the first chip.
926  */
927  if (chipset)
928  ni_660x_write_register(dev, chipset, CounterSwap,
929  ClockConfigRegister);
930  else
931  ni_660x_write_register(dev, chipset, 0, ClockConfigRegister);
932 }
933 
934 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
935  struct comedi_subdevice *s)
936 {
937  ni_tio_handle_interrupt(subdev_to_counter(s), s);
938  if (s->async->events) {
939  if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
940  COMEDI_CB_OVERFLOW)) {
941  ni_660x_cancel(dev, s);
942  }
943  comedi_event(dev, s);
944  }
945 }
946 
947 static irqreturn_t ni_660x_interrupt(int irq, void *d)
948 {
949  struct comedi_device *dev = d;
950  struct comedi_subdevice *s;
951  unsigned i;
952  unsigned long flags;
953 
954  if (dev->attached == 0)
955  return IRQ_NONE;
956  /* lock to avoid race with comedi_poll */
957  spin_lock_irqsave(&private(dev)->interrupt_lock, flags);
958  smp_mb();
959  for (i = 0; i < ni_660x_num_counters(dev); ++i) {
960  s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
961  ni_660x_handle_gpct_interrupt(dev, s);
962  }
963  spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags);
964  return IRQ_HANDLED;
965 }
966 
967 static int ni_660x_input_poll(struct comedi_device *dev,
968  struct comedi_subdevice *s)
969 {
970  unsigned long flags;
971  /* lock to avoid race with comedi_poll */
972  spin_lock_irqsave(&private(dev)->interrupt_lock, flags);
973  mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async);
974  spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags);
975  return comedi_buf_read_n_available(s->async);
976 }
977 
978 static int ni_660x_buf_change(struct comedi_device *dev,
979  struct comedi_subdevice *s,
980  unsigned long new_size)
981 {
982  int ret;
983 
984  ret = mite_buf_change(mite_ring(private(dev), subdev_to_counter(s)),
985  s->async);
986  if (ret < 0)
987  return ret;
988 
989  return 0;
990 }
991 
992 static int ni_660x_allocate_private(struct comedi_device *dev)
993 {
994  int retval;
995  unsigned i;
996 
997  retval = alloc_private(dev, sizeof(struct ni_660x_private));
998  if (retval < 0)
999  return retval;
1000 
1001  spin_lock_init(&private(dev)->mite_channel_lock);
1002  spin_lock_init(&private(dev)->interrupt_lock);
1003  spin_lock_init(&private(dev)->soft_reg_copy_lock);
1004  for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1005  private(dev)->pfi_output_selects[i] = pfi_output_select_counter;
1006 
1007  return 0;
1008 }
1009 
1010 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
1011 {
1012  unsigned i;
1013  unsigned j;
1014 
1015  for (i = 0; i < board(dev)->n_chips; ++i) {
1016  for (j = 0; j < counters_per_chip; ++j) {
1017  private(dev)->mite_rings[i][j] =
1018  mite_alloc_ring(private(dev)->mite);
1019  if (private(dev)->mite_rings[i][j] == NULL)
1020  return -ENOMEM;
1021  }
1022  }
1023  return 0;
1024 }
1025 
1026 static void ni_660x_free_mite_rings(struct comedi_device *dev)
1027 {
1028  unsigned i;
1029  unsigned j;
1030 
1031  for (i = 0; i < board(dev)->n_chips; ++i) {
1032  for (j = 0; j < counters_per_chip; ++j)
1033  mite_free_ring(private(dev)->mite_rings[i][j]);
1034  }
1035 }
1036 
1037 static const struct ni_660x_board *
1038 ni_660x_find_boardinfo(struct pci_dev *pcidev)
1039 {
1040  unsigned int dev_id = pcidev->device;
1041  unsigned int n;
1042 
1043  for (n = 0; n < ARRAY_SIZE(ni_660x_boards); n++) {
1044  const struct ni_660x_board *board = &ni_660x_boards[n];
1045  if (board->dev_id == dev_id)
1046  return board;
1047  }
1048  return NULL;
1049 }
1050 
1051 static int __devinit ni_660x_attach_pci(struct comedi_device *dev,
1052  struct pci_dev *pcidev)
1053 {
1054  struct comedi_subdevice *s;
1055  int ret;
1056  unsigned i;
1057  unsigned global_interrupt_config_bits;
1058 
1059  ret = ni_660x_allocate_private(dev);
1060  if (ret < 0)
1061  return ret;
1062  dev->board_ptr = ni_660x_find_boardinfo(pcidev);
1063  if (!dev->board_ptr)
1064  return -ENODEV;
1065  private(dev)->mite = mite_alloc(pcidev);
1066  if (!private(dev)->mite)
1067  return -ENOMEM;
1068 
1069  dev->board_name = board(dev)->name;
1070 
1071  ret = mite_setup2(private(dev)->mite, 1);
1072  if (ret < 0) {
1073  dev_warn(dev->class_dev, "error setting up mite\n");
1074  return ret;
1075  }
1076  comedi_set_hw_dev(dev, &private(dev)->mite->pcidev->dev);
1077  ret = ni_660x_alloc_mite_rings(dev);
1078  if (ret < 0)
1079  return ret;
1080 
1081  ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS);
1082  if (ret)
1083  return ret;
1084 
1085  s = &dev->subdevices[0];
1086  /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1087  s->type = COMEDI_SUBD_UNUSED;
1088 
1089  s = &dev->subdevices[NI_660X_DIO_SUBDEV];
1090  /* DIGITAL I/O SUBDEVICE */
1091  s->type = COMEDI_SUBD_DIO;
1092  s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1093  s->n_chan = NUM_PFI_CHANNELS;
1094  s->maxdata = 1;
1095  s->range_table = &range_digital;
1096  s->insn_bits = ni_660x_dio_insn_bits;
1097  s->insn_config = ni_660x_dio_insn_config;
1098  s->io_bits = 0; /* all bits default to input */
1099  /* we use the ioconfig registers to control dio direction, so zero
1100  output enables in stc dio control reg */
1101  ni_660x_write_register(dev, 0, 0, STCDIOControl);
1102 
1103  private(dev)->counter_dev = ni_gpct_device_construct(dev,
1104  &ni_gpct_write_register,
1105  &ni_gpct_read_register,
1106  ni_gpct_variant_660x,
1107  ni_660x_num_counters
1108  (dev));
1109  if (private(dev)->counter_dev == NULL)
1110  return -ENOMEM;
1111  for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1112  s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
1113  if (i < ni_660x_num_counters(dev)) {
1114  s->type = COMEDI_SUBD_COUNTER;
1115  s->subdev_flags =
1116  SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1117  SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1118  s->n_chan = 3;
1119  s->maxdata = 0xffffffff;
1120  s->insn_read = ni_660x_GPCT_rinsn;
1121  s->insn_write = ni_660x_GPCT_winsn;
1122  s->insn_config = ni_660x_GPCT_insn_config;
1123  s->do_cmd = &ni_660x_cmd;
1124  s->len_chanlist = 1;
1125  s->do_cmdtest = &ni_660x_cmdtest;
1126  s->cancel = &ni_660x_cancel;
1127  s->poll = &ni_660x_input_poll;
1128  s->async_dma_dir = DMA_BIDIRECTIONAL;
1129  s->buf_change = &ni_660x_buf_change;
1130  s->private = &private(dev)->counter_dev->counters[i];
1131 
1132  private(dev)->counter_dev->counters[i].chip_index =
1133  i / counters_per_chip;
1134  private(dev)->counter_dev->counters[i].counter_index =
1135  i % counters_per_chip;
1136  } else {
1137  s->type = COMEDI_SUBD_UNUSED;
1138  }
1139  }
1140  for (i = 0; i < board(dev)->n_chips; ++i)
1141  init_tio_chip(dev, i);
1142 
1143  for (i = 0; i < ni_660x_num_counters(dev); ++i)
1144  ni_tio_init_counter(&private(dev)->counter_dev->counters[i]);
1145 
1146  for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1147  if (i < min_counter_pfi_chan)
1148  ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1149  else
1150  ni_660x_set_pfi_routing(dev, i,
1151  pfi_output_select_counter);
1152  ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1153  }
1154  /* to be safe, set counterswap bits on tio chips after all the counter
1155  outputs have been set to high impedance mode */
1156  for (i = 0; i < board(dev)->n_chips; ++i)
1157  set_tio_counterswap(dev, i);
1158 
1159  ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt,
1160  IRQF_SHARED, "ni_660x", dev);
1161  if (ret < 0) {
1162  dev_warn(dev->class_dev, " irq not available\n");
1163  return ret;
1164  }
1165  dev->irq = mite_irq(private(dev)->mite);
1166  global_interrupt_config_bits = Global_Int_Enable_Bit;
1167  if (board(dev)->n_chips > 1)
1168  global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1169  ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1170  GlobalInterruptConfigRegister);
1171  dev_info(dev->class_dev, "ni_660x: %s attached\n", dev->board_name);
1172  return 0;
1173 }
1174 
1175 static void ni_660x_detach(struct comedi_device *dev)
1176 {
1177  if (dev->irq)
1178  free_irq(dev->irq, dev);
1179  if (dev->private) {
1180  if (private(dev)->counter_dev)
1181  ni_gpct_device_destroy(private(dev)->counter_dev);
1182  if (private(dev)->mite) {
1183  ni_660x_free_mite_rings(dev);
1184  mite_unsetup(private(dev)->mite);
1185  mite_free(private(dev)->mite);
1186  }
1187  }
1188 }
1189 
1190 static int
1191 ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1192  struct comedi_insn *insn, unsigned int *data)
1193 {
1194  return ni_tio_rinsn(subdev_to_counter(s), insn, data);
1195 }
1196 
1197 static void init_tio_chip(struct comedi_device *dev, int chipset)
1198 {
1199  unsigned i;
1200 
1201  /* init dma configuration register */
1202  private(dev)->dma_configuration_soft_copies[chipset] = 0;
1203  for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
1204  private(dev)->dma_configuration_soft_copies[chipset] |=
1205  dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
1206  }
1207  ni_660x_write_register(dev, chipset,
1208  private(dev)->
1209  dma_configuration_soft_copies[chipset],
1210  DMAConfigRegister);
1211  for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1212  ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
1213 }
1214 
1215 static int
1216 ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
1217  struct comedi_insn *insn, unsigned int *data)
1218 {
1219  return ni_tio_insn_config(subdev_to_counter(s), insn, data);
1220 }
1221 
1222 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
1223  struct comedi_subdevice *s,
1224  struct comedi_insn *insn, unsigned int *data)
1225 {
1226  return ni_tio_winsn(subdev_to_counter(s), insn, data);
1227 }
1228 
1229 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
1230  struct comedi_subdevice *s,
1231  struct comedi_insn *insn, unsigned int *data)
1232 {
1233  unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
1234 
1235  /* Check if we have to write some bits */
1236  if (data[0]) {
1237  s->state &= ~(data[0] << base_bitfield_channel);
1238  s->state |= (data[0] & data[1]) << base_bitfield_channel;
1239  /* Write out the new digital output lines */
1240  ni_660x_write_register(dev, 0, s->state, DIO32Output);
1241  }
1242  /* on return, data[1] contains the value of the digital
1243  * input and output lines. */
1244  data[1] =
1245  (ni_660x_read_register(dev, 0,
1246  DIO32Input) >> base_bitfield_channel);
1247  return insn->n;
1248 }
1249 
1250 static void ni_660x_select_pfi_output(struct comedi_device *dev,
1251  unsigned pfi_channel,
1252  unsigned output_select)
1253 {
1254  static const unsigned counter_4_7_first_pfi = 8;
1255  static const unsigned counter_4_7_last_pfi = 23;
1256  unsigned active_chipset = 0;
1257  unsigned idle_chipset = 0;
1258  unsigned active_bits;
1259  unsigned idle_bits;
1260 
1261  if (board(dev)->n_chips > 1) {
1262  if (output_select == pfi_output_select_counter &&
1263  pfi_channel >= counter_4_7_first_pfi &&
1264  pfi_channel <= counter_4_7_last_pfi) {
1265  active_chipset = 1;
1266  idle_chipset = 0;
1267  } else {
1268  active_chipset = 0;
1269  idle_chipset = 1;
1270  }
1271  }
1272 
1273  if (idle_chipset != active_chipset) {
1274  idle_bits =
1275  ni_660x_read_register(dev, idle_chipset,
1276  IOConfigReg(pfi_channel));
1277  idle_bits &= ~pfi_output_select_mask(pfi_channel);
1278  idle_bits |=
1279  pfi_output_select_bits(pfi_channel,
1280  pfi_output_select_high_Z);
1281  ni_660x_write_register(dev, idle_chipset, idle_bits,
1282  IOConfigReg(pfi_channel));
1283  }
1284 
1285  active_bits =
1286  ni_660x_read_register(dev, active_chipset,
1287  IOConfigReg(pfi_channel));
1288  active_bits &= ~pfi_output_select_mask(pfi_channel);
1289  active_bits |= pfi_output_select_bits(pfi_channel, output_select);
1290  ni_660x_write_register(dev, active_chipset, active_bits,
1291  IOConfigReg(pfi_channel));
1292 }
1293 
1294 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
1295  unsigned source)
1296 {
1297  if (source > num_pfi_output_selects)
1298  return -EINVAL;
1299  if (source == pfi_output_select_high_Z)
1300  return -EINVAL;
1301  if (chan < min_counter_pfi_chan) {
1302  if (source == pfi_output_select_counter)
1303  return -EINVAL;
1304  } else if (chan > max_dio_pfi_chan) {
1305  if (source == pfi_output_select_do)
1306  return -EINVAL;
1307  }
1308  BUG_ON(chan >= NUM_PFI_CHANNELS);
1309 
1310  private(dev)->pfi_output_selects[chan] = source;
1311  if (private(dev)->pfi_direction_bits & (((uint64_t) 1) << chan))
1312  ni_660x_select_pfi_output(dev, chan,
1313  private(dev)->
1314  pfi_output_selects[chan]);
1315  return 0;
1316 }
1317 
1318 static unsigned ni_660x_get_pfi_routing(struct comedi_device *dev,
1319  unsigned chan)
1320 {
1321  BUG_ON(chan >= NUM_PFI_CHANNELS);
1322  return private(dev)->pfi_output_selects[chan];
1323 }
1324 
1325 static void ni660x_config_filter(struct comedi_device *dev,
1326  unsigned pfi_channel,
1327  enum ni_gpct_filter_select filter)
1328 {
1329  unsigned bits = ni_660x_read_register(dev, 0, IOConfigReg(pfi_channel));
1330  bits &= ~pfi_input_select_mask(pfi_channel);
1331  bits |= pfi_input_select_bits(pfi_channel, filter);
1332  ni_660x_write_register(dev, 0, bits, IOConfigReg(pfi_channel));
1333 }
1334 
1335 static int ni_660x_dio_insn_config(struct comedi_device *dev,
1336  struct comedi_subdevice *s,
1337  struct comedi_insn *insn, unsigned int *data)
1338 {
1339  int chan = CR_CHAN(insn->chanspec);
1340 
1341  /* The input or output configuration of each digital line is
1342  * configured by a special insn_config instruction. chanspec
1343  * contains the channel to be changed, and data[0] contains the
1344  * value COMEDI_INPUT or COMEDI_OUTPUT. */
1345 
1346  switch (data[0]) {
1347  case INSN_CONFIG_DIO_OUTPUT:
1348  private(dev)->pfi_direction_bits |= ((uint64_t) 1) << chan;
1349  ni_660x_select_pfi_output(dev, chan,
1350  private(dev)->
1351  pfi_output_selects[chan]);
1352  break;
1353  case INSN_CONFIG_DIO_INPUT:
1354  private(dev)->pfi_direction_bits &= ~(((uint64_t) 1) << chan);
1355  ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1356  break;
1357  case INSN_CONFIG_DIO_QUERY:
1358  data[1] =
1359  (private(dev)->pfi_direction_bits &
1360  (((uint64_t) 1) << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1361  return 0;
1362  case INSN_CONFIG_SET_ROUTING:
1363  return ni_660x_set_pfi_routing(dev, chan, data[1]);
1364  break;
1365  case INSN_CONFIG_GET_ROUTING:
1366  data[1] = ni_660x_get_pfi_routing(dev, chan);
1367  break;
1368  case INSN_CONFIG_FILTER:
1369  ni660x_config_filter(dev, chan, data[1]);
1370  break;
1371  default:
1372  return -EINVAL;
1373  break;
1374  }
1375  return 0;
1376 }
1377 
1378 MODULE_AUTHOR("Comedi http://www.comedi.org");
1379 MODULE_DESCRIPTION("Comedi low-level driver");
1380 MODULE_LICENSE("GPL");
Generated on Thu Jan 10 2013 14:27:09 for Linux Kernel by   doxygen 1.8.2