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ni_mio_common.c
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1 /*
2  comedi/drivers/ni_mio_common.c
3  Hardware driver for DAQ-STC based boards
4 
5  COMEDI - Linux Control and Measurement Device Interface
6  Copyright (C) 1997-2001 David A. Schleef <[email protected]>
7  Copyright (C) 2002-2006 Frank Mori Hess <[email protected]>
8 
9  This program is free software; you can redistribute it and/or modify
10  it under the terms of the GNU General Public License as published by
11  the Free Software Foundation; either version 2 of the License, or
12  (at your option) any later version.
13 
14  This program is distributed in the hope that it will be useful,
15  but WITHOUT ANY WARRANTY; without even the implied warranty of
16  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  GNU General Public License for more details.
18 
19  You should have received a copy of the GNU General Public License
20  along with this program; if not, write to the Free Software
21  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 
23 */
24 
25 /*
26  This file is meant to be included by another file, e.g.,
27  ni_atmio.c or ni_pcimio.c.
28 
29  Interrupt support originally added by Truxton Fulton
30  <[email protected]>
31 
32  References (from ftp://ftp.natinst.com/support/manuals):
33 
34  340747b.pdf AT-MIO E series Register Level Programmer Manual
35  341079b.pdf PCI E Series RLPM
36  340934b.pdf DAQ-STC reference manual
37  67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
38  release_ni611x.pdf
39  release_ni67xx.pdf
40  Other possibly relevant info:
41 
42  320517c.pdf User manual (obsolete)
43  320517f.pdf User manual (new)
44  320889a.pdf delete
45  320906c.pdf maximum signal ratings
46  321066a.pdf about 16x
47  321791a.pdf discontinuation of at-mio-16e-10 rev. c
48  321808a.pdf about at-mio-16e-10 rev P
49  321837a.pdf discontinuation of at-mio-16de-10 rev d
50  321838a.pdf about at-mio-16de-10 rev N
51 
52  ISSUES:
53 
54  - the interrupt routine needs to be cleaned up
55 
56  2006-02-07: S-Series PCI-6143: Support has been added but is not
57  fully tested as yet. Terry Barnaby, BEAM Ltd.
58 */
59 
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
63 
64 #include <linux/interrupt.h>
65 #include <linux/sched.h>
66 #include "8255.h"
67 #include "mite.h"
68 #include "comedi_fc.h"
69 
70 #ifndef MDPRINTK
71 #define MDPRINTK(format, args...)
72 #endif
73 
74 /* A timeout count */
75 #define NI_TIMEOUT 1000
76 static const unsigned old_RTSI_clock_channel = 7;
77 
78 /* Note: this table must match the ai_gain_* definitions */
79 static const short ni_gainlkup[][16] = {
80  [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
81  0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
82  [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
83  [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
84  0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
85  [ai_gain_4] = {0, 1, 4, 7},
86  [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
87  0x003, 0x004, 0x005, 0x006},
88  [ai_gain_622x] = {0, 1, 4, 5},
89  [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
90  [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
91 };
92 
93 static const struct comedi_lrange range_ni_E_ai = { 16, {
94  RANGE(-10, 10),
95  RANGE(-5, 5),
96  RANGE(-2.5, 2.5),
97  RANGE(-1, 1),
98  RANGE(-0.5, 0.5),
99  RANGE(-0.25, 0.25),
100  RANGE(-0.1, 0.1),
101  RANGE(-0.05, 0.05),
102  RANGE(0, 20),
103  RANGE(0, 10),
104  RANGE(0, 5),
105  RANGE(0, 2),
106  RANGE(0, 1),
107  RANGE(0, 0.5),
108  RANGE(0, 0.2),
109  RANGE(0, 0.1),
110  }
111 };
112 
113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
114  RANGE(-10, 10),
115  RANGE(-5, 5),
116  RANGE(-1, 1),
117  RANGE(-0.1,
118  0.1),
119  RANGE(0, 10),
120  RANGE(0, 5),
121  RANGE(0, 1),
122  RANGE(0, 0.1),
123  }
124 };
125 
126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
127  RANGE(-10,
128  10),
129  RANGE(-5, 5),
130  RANGE(-2, 2),
131  RANGE(-1, 1),
132  RANGE(-0.5,
133  0.5),
134  RANGE(-0.2,
135  0.2),
136  RANGE(-0.1,
137  0.1),
138  RANGE(0, 10),
139  RANGE(0, 5),
140  RANGE(0, 2),
141  RANGE(0, 1),
142  RANGE(0,
143  0.5),
144  RANGE(0,
145  0.2),
146  RANGE(0,
147  0.1),
148  }
149 };
150 
151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
152  RANGE(-10, 10),
153  RANGE(-5, 5),
154  RANGE(-0.5,
155  0.5),
156  RANGE(-0.05,
157  0.05),
158  }
159 };
160 
161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
162  RANGE(-50, 50),
163  RANGE(-20, 20),
164  RANGE(-10, 10),
165  RANGE(-5, 5),
166  RANGE(-2, 2),
167  RANGE(-1, 1),
168  RANGE(-0.5, 0.5),
169  RANGE(-0.2, 0.2),
170  }
171 };
172 
173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
174  RANGE(-10, 10),
175  RANGE(-5, 5),
176  RANGE(-1, 1),
177  RANGE(-0.2, 0.2),
178  }
179 };
180 
181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
182  RANGE(-10, 10),
183  RANGE(-5, 5),
184  RANGE(-2, 2),
185  RANGE(-1, 1),
186  RANGE(-0.5, 0.5),
187  RANGE(-0.2, 0.2),
188  RANGE(-0.1, 0.1),
189  }
190 };
191 
192 static const struct comedi_lrange range_ni_S_ai_6143 = { 1, {
193  RANGE(-5, +5),
194  }
195 };
196 
197 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
198  RANGE(-10, 10),
199  RANGE(0, 10),
200  RANGE_ext(-1, 1),
201  RANGE_ext(0, 1),
202  }
203 };
204 
205 static const struct comedi_lrange *const ni_range_lkup[] = {
206  [ai_gain_16] = &range_ni_E_ai,
207  [ai_gain_8] = &range_ni_E_ai_limited,
208  [ai_gain_14] = &range_ni_E_ai_limited14,
209  [ai_gain_4] = &range_ni_E_ai_bipolar4,
210  [ai_gain_611x] = &range_ni_E_ai_611x,
211  [ai_gain_622x] = &range_ni_M_ai_622x,
212  [ai_gain_628x] = &range_ni_M_ai_628x,
213  [ai_gain_6143] = &range_ni_S_ai_6143
214 };
215 
216 static int ni_dio_insn_config(struct comedi_device *dev,
217  struct comedi_subdevice *s,
218  struct comedi_insn *insn, unsigned int *data);
219 static int ni_dio_insn_bits(struct comedi_device *dev,
220  struct comedi_subdevice *s,
221  struct comedi_insn *insn, unsigned int *data);
222 static int ni_cdio_cmdtest(struct comedi_device *dev,
223  struct comedi_subdevice *s, struct comedi_cmd *cmd);
224 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
225 static int ni_cdio_cancel(struct comedi_device *dev,
226  struct comedi_subdevice *s);
227 static void handle_cdio_interrupt(struct comedi_device *dev);
228 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
229  unsigned int trignum);
230 
231 static int ni_serial_insn_config(struct comedi_device *dev,
232  struct comedi_subdevice *s,
233  struct comedi_insn *insn, unsigned int *data);
234 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
235  struct comedi_subdevice *s,
236  unsigned char data_out,
237  unsigned char *data_in);
238 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
239  struct comedi_subdevice *s,
240  unsigned char data_out,
241  unsigned char *data_in);
242 
243 static int ni_calib_insn_read(struct comedi_device *dev,
244  struct comedi_subdevice *s,
245  struct comedi_insn *insn, unsigned int *data);
246 static int ni_calib_insn_write(struct comedi_device *dev,
247  struct comedi_subdevice *s,
248  struct comedi_insn *insn, unsigned int *data);
249 
250 static int ni_eeprom_insn_read(struct comedi_device *dev,
251  struct comedi_subdevice *s,
252  struct comedi_insn *insn, unsigned int *data);
253 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
254  struct comedi_subdevice *s,
255  struct comedi_insn *insn,
256  unsigned int *data);
257 
258 static int ni_pfi_insn_bits(struct comedi_device *dev,
259  struct comedi_subdevice *s,
260  struct comedi_insn *insn, unsigned int *data);
261 static int ni_pfi_insn_config(struct comedi_device *dev,
262  struct comedi_subdevice *s,
263  struct comedi_insn *insn, unsigned int *data);
264 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
265  unsigned chan);
266 
267 static void ni_rtsi_init(struct comedi_device *dev);
268 static int ni_rtsi_insn_bits(struct comedi_device *dev,
269  struct comedi_subdevice *s,
270  struct comedi_insn *insn, unsigned int *data);
271 static int ni_rtsi_insn_config(struct comedi_device *dev,
272  struct comedi_subdevice *s,
273  struct comedi_insn *insn, unsigned int *data);
274 
275 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
276 static int ni_read_eeprom(struct comedi_device *dev, int addr);
277 
278 #ifdef DEBUG_STATUS_A
279 static void ni_mio_print_status_a(int status);
280 #else
281 #define ni_mio_print_status_a(a)
282 #endif
283 #ifdef DEBUG_STATUS_B
284 static void ni_mio_print_status_b(int status);
285 #else
286 #define ni_mio_print_status_b(a)
287 #endif
288 
289 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
290 #ifndef PCIDMA
291 static void ni_handle_fifo_half_full(struct comedi_device *dev);
292 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
293  struct comedi_subdevice *s);
294 #endif
295 static void ni_handle_fifo_dregs(struct comedi_device *dev);
296 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
297  unsigned int trignum);
298 static void ni_load_channelgain_list(struct comedi_device *dev,
299  unsigned int n_chan, unsigned int *list);
300 static void shutdown_ai_command(struct comedi_device *dev);
301 
302 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
303  unsigned int trignum);
304 
305 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
306 
307 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
308 
309 static int ni_gpct_insn_write(struct comedi_device *dev,
310  struct comedi_subdevice *s,
311  struct comedi_insn *insn, unsigned int *data);
312 static int ni_gpct_insn_read(struct comedi_device *dev,
313  struct comedi_subdevice *s,
314  struct comedi_insn *insn, unsigned int *data);
315 static int ni_gpct_insn_config(struct comedi_device *dev,
316  struct comedi_subdevice *s,
317  struct comedi_insn *insn, unsigned int *data);
318 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
319 static int ni_gpct_cmdtest(struct comedi_device *dev,
320  struct comedi_subdevice *s, struct comedi_cmd *cmd);
321 static int ni_gpct_cancel(struct comedi_device *dev,
322  struct comedi_subdevice *s);
323 static void handle_gpct_interrupt(struct comedi_device *dev,
324  unsigned short counter_index);
325 
326 static int init_cs5529(struct comedi_device *dev);
327 static int cs5529_do_conversion(struct comedi_device *dev,
328  unsigned short *data);
329 static int cs5529_ai_insn_read(struct comedi_device *dev,
330  struct comedi_subdevice *s,
331  struct comedi_insn *insn, unsigned int *data);
332 #ifdef NI_CS5529_DEBUG
333 static unsigned int cs5529_config_read(struct comedi_device *dev,
334  unsigned int reg_select_bits);
335 #endif
336 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
337  unsigned int reg_select_bits);
338 
339 static int ni_m_series_pwm_config(struct comedi_device *dev,
340  struct comedi_subdevice *s,
341  struct comedi_insn *insn, unsigned int *data);
342 static int ni_6143_pwm_config(struct comedi_device *dev,
343  struct comedi_subdevice *s,
344  struct comedi_insn *insn, unsigned int *data);
345 
346 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
347  unsigned period_ns);
348 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
349 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
350 
351 enum aimodes {
352  AIMODE_NONE = 0,
353  AIMODE_HALF_FULL = 1,
354  AIMODE_SCAN = 2,
355  AIMODE_SAMPLE = 3,
356 };
357 
358 enum ni_common_subdevices {
359  NI_AI_SUBDEV,
360  NI_AO_SUBDEV,
361  NI_DIO_SUBDEV,
362  NI_8255_DIO_SUBDEV,
363  NI_UNUSED_SUBDEV,
364  NI_CALIBRATION_SUBDEV,
365  NI_EEPROM_SUBDEV,
366  NI_PFI_DIO_SUBDEV,
367  NI_CS5529_CALIBRATION_SUBDEV,
368  NI_SERIAL_SUBDEV,
369  NI_RTSI_SUBDEV,
370  NI_GPCT0_SUBDEV,
371  NI_GPCT1_SUBDEV,
372  NI_FREQ_OUT_SUBDEV,
373  NI_NUM_SUBDEVICES
374 };
375 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
376 {
377  switch (counter_index) {
378  case 0:
379  return NI_GPCT0_SUBDEV;
380  break;
381  case 1:
382  return NI_GPCT1_SUBDEV;
383  break;
384  default:
385  break;
386  }
387  BUG();
388  return NI_GPCT0_SUBDEV;
389 }
390 
391 enum timebase_nanoseconds {
392  TIMEBASE_1_NS = 50,
393  TIMEBASE_2_NS = 10000
394 };
395 
396 #define SERIAL_DISABLED 0
397 #define SERIAL_600NS 600
398 #define SERIAL_1_2US 1200
399 #define SERIAL_10US 10000
400 
401 static const int num_adc_stages_611x = 3;
402 
403 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
404  unsigned ai_mite_status);
405 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
406  unsigned ao_mite_status);
407 static void get_last_sample_611x(struct comedi_device *dev);
408 static void get_last_sample_6143(struct comedi_device *dev);
409 
410 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
411  unsigned bit_mask, unsigned bit_values)
412 {
413  unsigned long flags;
414 
415  spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
416  switch (reg) {
417  case Interrupt_A_Enable_Register:
418  devpriv->int_a_enable_reg &= ~bit_mask;
419  devpriv->int_a_enable_reg |= bit_values & bit_mask;
420  devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
421  Interrupt_A_Enable_Register);
422  break;
423  case Interrupt_B_Enable_Register:
424  devpriv->int_b_enable_reg &= ~bit_mask;
425  devpriv->int_b_enable_reg |= bit_values & bit_mask;
426  devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
427  Interrupt_B_Enable_Register);
428  break;
429  case IO_Bidirection_Pin_Register:
430  devpriv->io_bidirection_pin_reg &= ~bit_mask;
431  devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
432  devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
433  IO_Bidirection_Pin_Register);
434  break;
435  case AI_AO_Select:
436  devpriv->ai_ao_select_reg &= ~bit_mask;
437  devpriv->ai_ao_select_reg |= bit_values & bit_mask;
438  ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
439  break;
440  case G0_G1_Select:
441  devpriv->g0_g1_select_reg &= ~bit_mask;
442  devpriv->g0_g1_select_reg |= bit_values & bit_mask;
443  ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
444  break;
445  default:
446  printk("Warning %s() called with invalid register\n", __func__);
447  printk("reg is %d\n", reg);
448  break;
449  }
450  mmiowb();
451  spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
452 }
453 
454 #ifdef PCIDMA
455 static int ni_ai_drain_dma(struct comedi_device *dev);
456 
457 /* DMA channel setup */
458 
459 /* negative channel means no channel */
460 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
461 {
462  unsigned bitfield;
463 
464  if (channel >= 0) {
465  bitfield =
466  (ni_stc_dma_channel_select_bitfield(channel) <<
467  AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
468  } else {
469  bitfield = 0;
470  }
471  ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
472 }
473 
474 /* negative channel means no channel */
475 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
476 {
477  unsigned bitfield;
478 
479  if (channel >= 0) {
480  bitfield =
481  (ni_stc_dma_channel_select_bitfield(channel) <<
482  AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
483  } else {
484  bitfield = 0;
485  }
486  ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
487 }
488 
489 /* negative mite_channel means no channel */
490 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
491  unsigned gpct_index,
492  int mite_channel)
493 {
494  unsigned bitfield;
495 
496  if (mite_channel >= 0) {
497  bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
498  } else {
499  bitfield = 0;
500  }
501  ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
502  bitfield);
503 }
504 
505 /* negative mite_channel means no channel */
506 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
507  int mite_channel)
508 {
509  unsigned long flags;
510 
511  spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
512  devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
513  if (mite_channel >= 0) {
514  /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
515  under the assumption the cdio dma selection works just like ai/ao/gpct.
516  Definitely works for dma channels 0 and 1. */
517  devpriv->cdio_dma_select_reg |=
518  (ni_stc_dma_channel_select_bitfield(mite_channel) <<
519  CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
520  }
521  ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
522  mmiowb();
523  spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
524 }
525 
526 static int ni_request_ai_mite_channel(struct comedi_device *dev)
527 {
528  unsigned long flags;
529 
530  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
531  BUG_ON(devpriv->ai_mite_chan);
532  devpriv->ai_mite_chan =
533  mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
534  if (devpriv->ai_mite_chan == NULL) {
535  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
536  comedi_error(dev,
537  "failed to reserve mite dma channel for analog input.");
538  return -EBUSY;
539  }
540  devpriv->ai_mite_chan->dir = COMEDI_INPUT;
541  ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
542  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
543  return 0;
544 }
545 
546 static int ni_request_ao_mite_channel(struct comedi_device *dev)
547 {
548  unsigned long flags;
549 
550  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
551  BUG_ON(devpriv->ao_mite_chan);
552  devpriv->ao_mite_chan =
553  mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
554  if (devpriv->ao_mite_chan == NULL) {
555  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
556  comedi_error(dev,
557  "failed to reserve mite dma channel for analog outut.");
558  return -EBUSY;
559  }
560  devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
561  ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
562  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
563  return 0;
564 }
565 
566 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
567  unsigned gpct_index,
568  enum comedi_io_direction direction)
569 {
570  unsigned long flags;
571  struct mite_channel *mite_chan;
572 
573  BUG_ON(gpct_index >= NUM_GPCT);
574  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
575  BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
576  mite_chan =
577  mite_request_channel(devpriv->mite,
578  devpriv->gpct_mite_ring[gpct_index]);
579  if (mite_chan == NULL) {
580  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
581  comedi_error(dev,
582  "failed to reserve mite dma channel for counter.");
583  return -EBUSY;
584  }
585  mite_chan->dir = direction;
586  ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
587  mite_chan);
588  ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
589  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
590  return 0;
591 }
592 
593 #endif /* PCIDMA */
594 
595 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
596 {
597 #ifdef PCIDMA
598  unsigned long flags;
599 
600  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
601  BUG_ON(devpriv->cdo_mite_chan);
602  devpriv->cdo_mite_chan =
603  mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
604  if (devpriv->cdo_mite_chan == NULL) {
605  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
606  comedi_error(dev,
607  "failed to reserve mite dma channel for correlated digital outut.");
608  return -EBUSY;
609  }
610  devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
611  ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
612  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
613 #endif /* PCIDMA */
614  return 0;
615 }
616 
617 static void ni_release_ai_mite_channel(struct comedi_device *dev)
618 {
619 #ifdef PCIDMA
620  unsigned long flags;
621 
622  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
623  if (devpriv->ai_mite_chan) {
624  ni_set_ai_dma_channel(dev, -1);
625  mite_release_channel(devpriv->ai_mite_chan);
626  devpriv->ai_mite_chan = NULL;
627  }
628  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
629 #endif /* PCIDMA */
630 }
631 
632 static void ni_release_ao_mite_channel(struct comedi_device *dev)
633 {
634 #ifdef PCIDMA
635  unsigned long flags;
636 
637  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
638  if (devpriv->ao_mite_chan) {
639  ni_set_ao_dma_channel(dev, -1);
640  mite_release_channel(devpriv->ao_mite_chan);
641  devpriv->ao_mite_chan = NULL;
642  }
643  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
644 #endif /* PCIDMA */
645 }
646 
647 #ifdef PCIDMA
648 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
649  unsigned gpct_index)
650 {
651  unsigned long flags;
652 
653  BUG_ON(gpct_index >= NUM_GPCT);
654  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
655  if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
656  struct mite_channel *mite_chan =
657  devpriv->counter_dev->counters[gpct_index].mite_chan;
658 
659  ni_set_gpct_dma_channel(dev, gpct_index, -1);
660  ni_tio_set_mite_channel(&devpriv->
661  counter_dev->counters[gpct_index],
662  NULL);
663  mite_release_channel(mite_chan);
664  }
665  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
666 }
667 #endif /* PCIDMA */
668 
669 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
670 {
671 #ifdef PCIDMA
672  unsigned long flags;
673 
674  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
675  if (devpriv->cdo_mite_chan) {
676  ni_set_cdo_dma_channel(dev, -1);
677  mite_release_channel(devpriv->cdo_mite_chan);
678  devpriv->cdo_mite_chan = NULL;
679  }
680  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
681 #endif /* PCIDMA */
682 }
683 
684 /* e-series boards use the second irq signals to generate dma requests for their counters */
685 #ifdef PCIDMA
686 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
687  unsigned gpct_index, short enable)
688 {
689  if (boardtype.reg_type & ni_reg_m_series_mask)
690  return;
691  switch (gpct_index) {
692  case 0:
693  if (enable) {
694  devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
695  Second_IRQ_A_Enable_Register);
696  } else {
697  devpriv->stc_writew(dev, 0,
698  Second_IRQ_A_Enable_Register);
699  }
700  break;
701  case 1:
702  if (enable) {
703  devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
704  Second_IRQ_B_Enable_Register);
705  } else {
706  devpriv->stc_writew(dev, 0,
707  Second_IRQ_B_Enable_Register);
708  }
709  break;
710  default:
711  BUG();
712  break;
713  }
714 }
715 #endif /* PCIDMA */
716 
717 static void ni_clear_ai_fifo(struct comedi_device *dev)
718 {
719  if (boardtype.reg_type == ni_reg_6143) {
720  /* Flush the 6143 data FIFO */
721  ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
722  ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
723  while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
724  } else {
725  devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
726  if (boardtype.reg_type == ni_reg_625x) {
727  ni_writeb(0, M_Offset_Static_AI_Control(0));
728  ni_writeb(1, M_Offset_Static_AI_Control(0));
729 #if 0
730  /* the NI example code does 3 convert pulses for 625x boards,
731  but that appears to be wrong in practice. */
732  devpriv->stc_writew(dev, AI_CONVERT_Pulse,
733  AI_Command_1_Register);
734  devpriv->stc_writew(dev, AI_CONVERT_Pulse,
735  AI_Command_1_Register);
736  devpriv->stc_writew(dev, AI_CONVERT_Pulse,
737  AI_Command_1_Register);
738 #endif
739  }
740  }
741 }
742 
743 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
744 {
745  devpriv->stc_writew(dev, data >> 16, reg);
746  devpriv->stc_writew(dev, data & 0xffff, reg + 1);
747 }
748 
749 static uint32_t win_in2(struct comedi_device *dev, int reg)
750 {
751  uint32_t bits;
752  bits = devpriv->stc_readw(dev, reg) << 16;
753  bits |= devpriv->stc_readw(dev, reg + 1);
754  return bits;
755 }
756 
757 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
758 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
759  int addr)
760 {
761  unsigned long flags;
762 
763  spin_lock_irqsave(&devpriv->window_lock, flags);
764  ni_writew(addr, AO_Window_Address_611x);
765  ni_writew(data, AO_Window_Data_611x);
766  spin_unlock_irqrestore(&devpriv->window_lock, flags);
767 }
768 
769 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
770  int addr)
771 {
772  unsigned long flags;
773 
774  spin_lock_irqsave(&devpriv->window_lock, flags);
775  ni_writew(addr, AO_Window_Address_611x);
776  ni_writel(data, AO_Window_Data_611x);
777  spin_unlock_irqrestore(&devpriv->window_lock, flags);
778 }
779 
780 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
781 {
782  unsigned long flags;
783  unsigned short data;
784 
785  spin_lock_irqsave(&devpriv->window_lock, flags);
786  ni_writew(addr, AO_Window_Address_611x);
787  data = ni_readw(AO_Window_Data_611x);
788  spin_unlock_irqrestore(&devpriv->window_lock, flags);
789  return data;
790 }
791 
792 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
793 * share registers (such as Interrupt_A_Register) without interfering with
794 * each other.
795 *
796 * NOTE: the switch/case statements are optimized out for a constant argument
797 * so this is actually quite fast--- If you must wrap another function around this
798 * make it inline to avoid a large speed penalty.
799 *
800 * value should only be 1 or 0.
801 */
802 static inline void ni_set_bits(struct comedi_device *dev, int reg,
803  unsigned bits, unsigned value)
804 {
805  unsigned bit_values;
806 
807  if (value)
808  bit_values = bits;
809  else
810  bit_values = 0;
811  ni_set_bitfield(dev, reg, bits, bit_values);
812 }
813 
814 static irqreturn_t ni_E_interrupt(int irq, void *d)
815 {
816  struct comedi_device *dev = d;
817  unsigned short a_status;
818  unsigned short b_status;
819  unsigned int ai_mite_status = 0;
820  unsigned int ao_mite_status = 0;
821  unsigned long flags;
822 #ifdef PCIDMA
823  struct mite_struct *mite = devpriv->mite;
824 #endif
825 
826  if (dev->attached == 0)
827  return IRQ_NONE;
828  smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
829 
830  /* lock to avoid race with comedi_poll */
831  spin_lock_irqsave(&dev->spinlock, flags);
832  a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
833  b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
834 #ifdef PCIDMA
835  if (mite) {
836  unsigned long flags_too;
837 
838  spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
839  if (devpriv->ai_mite_chan) {
840  ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
841  if (ai_mite_status & CHSR_LINKC)
842  writel(CHOR_CLRLC,
843  devpriv->mite->mite_io_addr +
844  MITE_CHOR(devpriv->
845  ai_mite_chan->channel));
846  }
847  if (devpriv->ao_mite_chan) {
848  ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
849  if (ao_mite_status & CHSR_LINKC)
850  writel(CHOR_CLRLC,
851  mite->mite_io_addr +
852  MITE_CHOR(devpriv->
853  ao_mite_chan->channel));
854  }
855  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
856  }
857 #endif
858  ack_a_interrupt(dev, a_status);
859  ack_b_interrupt(dev, b_status);
860  if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
861  handle_a_interrupt(dev, a_status, ai_mite_status);
862  if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
863  handle_b_interrupt(dev, b_status, ao_mite_status);
864  handle_gpct_interrupt(dev, 0);
865  handle_gpct_interrupt(dev, 1);
866  handle_cdio_interrupt(dev);
867 
868  spin_unlock_irqrestore(&dev->spinlock, flags);
869  return IRQ_HANDLED;
870 }
871 
872 #ifdef PCIDMA
873 static void ni_sync_ai_dma(struct comedi_device *dev)
874 {
875  struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
876  unsigned long flags;
877 
878  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
879  if (devpriv->ai_mite_chan)
880  mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
881  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
882 }
883 
884 static void mite_handle_b_linkc(struct mite_struct *mite,
885  struct comedi_device *dev)
886 {
887  struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
888  unsigned long flags;
889 
890  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
891  if (devpriv->ao_mite_chan) {
892  mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
893  }
894  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
895 }
896 
897 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
898 {
899  static const int timeout = 10000;
900  int i;
901  for (i = 0; i < timeout; i++) {
902  unsigned short b_status;
903 
904  b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
905  if (b_status & AO_FIFO_Half_Full_St)
906  break;
907  /* if we poll too often, the pci bus activity seems
908  to slow the dma transfer down */
909  udelay(10);
910  }
911  if (i == timeout) {
912  comedi_error(dev, "timed out waiting for dma load");
913  return -EPIPE;
914  }
915  return 0;
916 }
917 
918 #endif /* PCIDMA */
919 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
920 {
921  if (devpriv->aimode == AIMODE_SCAN) {
922 #ifdef PCIDMA
923  static const int timeout = 10;
924  int i;
925 
926  for (i = 0; i < timeout; i++) {
927  ni_sync_ai_dma(dev);
928  if ((s->async->events & COMEDI_CB_EOS))
929  break;
930  udelay(1);
931  }
932 #else
933  ni_handle_fifo_dregs(dev);
934  s->async->events |= COMEDI_CB_EOS;
935 #endif
936  }
937  /* handle special case of single scan using AI_End_On_End_Of_Scan */
938  if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
939  shutdown_ai_command(dev);
940  }
941 }
942 
943 static void shutdown_ai_command(struct comedi_device *dev)
944 {
945  struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
946 
947 #ifdef PCIDMA
948  ni_ai_drain_dma(dev);
949 #endif
950  ni_handle_fifo_dregs(dev);
951  get_last_sample_611x(dev);
952  get_last_sample_6143(dev);
953 
954  s->async->events |= COMEDI_CB_EOA;
955 }
956 
957 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
958 {
959  if (s->
960  async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
961  COMEDI_CB_EOA)) {
962  switch (s - dev->subdevices) {
963  case NI_AI_SUBDEV:
964  ni_ai_reset(dev, s);
965  break;
966  case NI_AO_SUBDEV:
967  ni_ao_reset(dev, s);
968  break;
969  case NI_GPCT0_SUBDEV:
970  case NI_GPCT1_SUBDEV:
971  ni_gpct_cancel(dev, s);
972  break;
973  case NI_DIO_SUBDEV:
974  ni_cdio_cancel(dev, s);
975  break;
976  default:
977  break;
978  }
979  }
980  comedi_event(dev, s);
981 }
982 
983 static void handle_gpct_interrupt(struct comedi_device *dev,
984  unsigned short counter_index)
985 {
986 #ifdef PCIDMA
987  struct comedi_subdevice *s;
988 
989  s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
990 
991  ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
992  s);
993  if (s->async->events)
994  ni_event(dev, s);
995 #endif
996 }
997 
998 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
999 {
1000  unsigned short ack = 0;
1001 
1002  if (a_status & AI_SC_TC_St) {
1003  ack |= AI_SC_TC_Interrupt_Ack;
1004  }
1005  if (a_status & AI_START1_St) {
1006  ack |= AI_START1_Interrupt_Ack;
1007  }
1008  if (a_status & AI_START_St) {
1009  ack |= AI_START_Interrupt_Ack;
1010  }
1011  if (a_status & AI_STOP_St) {
1012  /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1013  ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1014  }
1015  if (ack)
1016  devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1017 }
1018 
1019 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1020  unsigned ai_mite_status)
1021 {
1022  struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1023 
1024  /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1025  if (s->type == COMEDI_SUBD_UNUSED)
1026  return;
1027 
1028 #ifdef DEBUG_INTERRUPT
1029  printk
1030  ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1031  status, ai_mite_status);
1032  ni_mio_print_status_a(status);
1033 #endif
1034 #ifdef PCIDMA
1035  if (ai_mite_status & CHSR_LINKC) {
1036  ni_sync_ai_dma(dev);
1037  }
1038 
1039  if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1040  CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1041  CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1042  printk
1043  ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1044  ai_mite_status);
1045  /* mite_print_chsr(ai_mite_status); */
1046  s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1047  /* disable_irq(dev->irq); */
1048  }
1049 #endif
1050 
1051  /* test for all uncommon interrupt events at the same time */
1052  if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1053  AI_SC_TC_St | AI_START1_St)) {
1054  if (status == 0xffff) {
1055  printk
1056  ("ni_mio_common: a_status=0xffff. Card removed?\n");
1057  /* we probably aren't even running a command now,
1058  * so it's a good idea to be careful. */
1059  if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) {
1060  s->async->events |=
1061  COMEDI_CB_ERROR | COMEDI_CB_EOA;
1062  ni_event(dev, s);
1063  }
1064  return;
1065  }
1066  if (status & (AI_Overrun_St | AI_Overflow_St |
1067  AI_SC_TC_Error_St)) {
1068  printk("ni_mio_common: ai error a_status=%04x\n",
1069  status);
1070  ni_mio_print_status_a(status);
1071 
1072  shutdown_ai_command(dev);
1073 
1074  s->async->events |= COMEDI_CB_ERROR;
1075  if (status & (AI_Overrun_St | AI_Overflow_St))
1076  s->async->events |= COMEDI_CB_OVERFLOW;
1077 
1078  ni_event(dev, s);
1079 
1080  return;
1081  }
1082  if (status & AI_SC_TC_St) {
1083 #ifdef DEBUG_INTERRUPT
1084  printk("ni_mio_common: SC_TC interrupt\n");
1085 #endif
1086  if (!devpriv->ai_continuous) {
1087  shutdown_ai_command(dev);
1088  }
1089  }
1090  }
1091 #ifndef PCIDMA
1092  if (status & AI_FIFO_Half_Full_St) {
1093  int i;
1094  static const int timeout = 10;
1095  /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1096  *fail to get the fifo less than half full, so loop to be sure.*/
1097  for (i = 0; i < timeout; ++i) {
1098  ni_handle_fifo_half_full(dev);
1099  if ((devpriv->stc_readw(dev,
1100  AI_Status_1_Register) &
1101  AI_FIFO_Half_Full_St) == 0)
1102  break;
1103  }
1104  }
1105 #endif /* !PCIDMA */
1106 
1107  if ((status & AI_STOP_St)) {
1108  ni_handle_eos(dev, s);
1109  }
1110 
1111  ni_event(dev, s);
1112 
1113 #ifdef DEBUG_INTERRUPT
1114  status = devpriv->stc_readw(dev, AI_Status_1_Register);
1115  if (status & Interrupt_A_St) {
1116  printk
1117  ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1118  status);
1119  }
1120 #endif
1121 }
1122 
1123 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1124 {
1125  unsigned short ack = 0;
1126  if (b_status & AO_BC_TC_St) {
1127  ack |= AO_BC_TC_Interrupt_Ack;
1128  }
1129  if (b_status & AO_Overrun_St) {
1130  ack |= AO_Error_Interrupt_Ack;
1131  }
1132  if (b_status & AO_START_St) {
1133  ack |= AO_START_Interrupt_Ack;
1134  }
1135  if (b_status & AO_START1_St) {
1136  ack |= AO_START1_Interrupt_Ack;
1137  }
1138  if (b_status & AO_UC_TC_St) {
1139  ack |= AO_UC_TC_Interrupt_Ack;
1140  }
1141  if (b_status & AO_UI2_TC_St) {
1142  ack |= AO_UI2_TC_Interrupt_Ack;
1143  }
1144  if (b_status & AO_UPDATE_St) {
1145  ack |= AO_UPDATE_Interrupt_Ack;
1146  }
1147  if (ack)
1148  devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1149 }
1150 
1151 static void handle_b_interrupt(struct comedi_device *dev,
1152  unsigned short b_status, unsigned ao_mite_status)
1153 {
1154  struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1155  /* unsigned short ack=0; */
1156 #ifdef DEBUG_INTERRUPT
1157  printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1158  b_status, ao_mite_status);
1159  ni_mio_print_status_b(b_status);
1160 #endif
1161 
1162 #ifdef PCIDMA
1163  /* Currently, mite.c requires us to handle LINKC */
1164  if (ao_mite_status & CHSR_LINKC) {
1165  mite_handle_b_linkc(devpriv->mite, dev);
1166  }
1167 
1168  if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1169  CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1170  CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1171  printk
1172  ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1173  ao_mite_status);
1174  /* mite_print_chsr(ao_mite_status); */
1175  s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1176  }
1177 #endif
1178 
1179  if (b_status == 0xffff)
1180  return;
1181  if (b_status & AO_Overrun_St) {
1182  printk
1183  ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1184  b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1185  s->async->events |= COMEDI_CB_OVERFLOW;
1186  }
1187 
1188  if (b_status & AO_BC_TC_St) {
1189  MDPRINTK
1190  ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1191  b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1192  s->async->events |= COMEDI_CB_EOA;
1193  }
1194 #ifndef PCIDMA
1195  if (b_status & AO_FIFO_Request_St) {
1196  int ret;
1197 
1198  ret = ni_ao_fifo_half_empty(dev, s);
1199  if (!ret) {
1200  printk("ni_mio_common: AO buffer underrun\n");
1201  ni_set_bits(dev, Interrupt_B_Enable_Register,
1202  AO_FIFO_Interrupt_Enable |
1203  AO_Error_Interrupt_Enable, 0);
1204  s->async->events |= COMEDI_CB_OVERFLOW;
1205  }
1206  }
1207 #endif
1208 
1209  ni_event(dev, s);
1210 }
1211 
1212 #ifdef DEBUG_STATUS_A
1213 static const char *const status_a_strings[] = {
1214  "passthru0", "fifo", "G0_gate", "G0_TC",
1215  "stop", "start", "sc_tc", "start1",
1216  "start2", "sc_tc_error", "overflow", "overrun",
1217  "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1218 };
1219 
1220 static void ni_mio_print_status_a(int status)
1221 {
1222  int i;
1223 
1224  printk("A status:");
1225  for (i = 15; i >= 0; i--) {
1226  if (status & (1 << i)) {
1227  printk(" %s", status_a_strings[i]);
1228  }
1229  }
1230  printk("\n");
1231 }
1232 #endif
1233 
1234 #ifdef DEBUG_STATUS_B
1235 static const char *const status_b_strings[] = {
1236  "passthru1", "fifo", "G1_gate", "G1_TC",
1237  "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1238  "start1", "overrun", "start", "bc_tc_error",
1239  "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1240 };
1241 
1242 static void ni_mio_print_status_b(int status)
1243 {
1244  int i;
1245 
1246  printk("B status:");
1247  for (i = 15; i >= 0; i--) {
1248  if (status & (1 << i)) {
1249  printk(" %s", status_b_strings[i]);
1250  }
1251  }
1252  printk("\n");
1253 }
1254 #endif
1255 
1256 #ifndef PCIDMA
1257 
1258 static void ni_ao_fifo_load(struct comedi_device *dev,
1259  struct comedi_subdevice *s, int n)
1260 {
1261  struct comedi_async *async = s->async;
1262  struct comedi_cmd *cmd = &async->cmd;
1263  int chan;
1264  int i;
1265  short d;
1266  u32 packed_data;
1267  int range;
1268  int err = 1;
1269 
1270  chan = async->cur_chan;
1271  for (i = 0; i < n; i++) {
1272  err &= comedi_buf_get(async, &d);
1273  if (err == 0)
1274  break;
1275 
1276  range = CR_RANGE(cmd->chanlist[chan]);
1277 
1278  if (boardtype.reg_type & ni_reg_6xxx_mask) {
1279  packed_data = d & 0xffff;
1280  /* 6711 only has 16 bit wide ao fifo */
1281  if (boardtype.reg_type != ni_reg_6711) {
1282  err &= comedi_buf_get(async, &d);
1283  if (err == 0)
1284  break;
1285  chan++;
1286  i++;
1287  packed_data |= (d << 16) & 0xffff0000;
1288  }
1289  ni_writel(packed_data, DAC_FIFO_Data_611x);
1290  } else {
1291  ni_writew(d, DAC_FIFO_Data);
1292  }
1293  chan++;
1294  chan %= cmd->chanlist_len;
1295  }
1296  async->cur_chan = chan;
1297  if (err == 0) {
1298  async->events |= COMEDI_CB_OVERFLOW;
1299  }
1300 }
1301 
1302 /*
1303  * There's a small problem if the FIFO gets really low and we
1304  * don't have the data to fill it. Basically, if after we fill
1305  * the FIFO with all the data available, the FIFO is _still_
1306  * less than half full, we never clear the interrupt. If the
1307  * IRQ is in edge mode, we never get another interrupt, because
1308  * this one wasn't cleared. If in level mode, we get flooded
1309  * with interrupts that we can't fulfill, because nothing ever
1310  * gets put into the buffer.
1311  *
1312  * This kind of situation is recoverable, but it is easier to
1313  * just pretend we had a FIFO underrun, since there is a good
1314  * chance it will happen anyway. This is _not_ the case for
1315  * RT code, as RT code might purposely be running close to the
1316  * metal. Needs to be fixed eventually.
1317  */
1318 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1319  struct comedi_subdevice *s)
1320 {
1321  int n;
1322 
1323  n = comedi_buf_read_n_available(s->async);
1324  if (n == 0) {
1325  s->async->events |= COMEDI_CB_OVERFLOW;
1326  return 0;
1327  }
1328 
1329  n /= sizeof(short);
1330  if (n > boardtype.ao_fifo_depth / 2)
1331  n = boardtype.ao_fifo_depth / 2;
1332 
1333  ni_ao_fifo_load(dev, s, n);
1334 
1335  s->async->events |= COMEDI_CB_BLOCK;
1336 
1337  return 1;
1338 }
1339 
1340 static int ni_ao_prep_fifo(struct comedi_device *dev,
1341  struct comedi_subdevice *s)
1342 {
1343  int n;
1344 
1345  /* reset fifo */
1346  devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1347  if (boardtype.reg_type & ni_reg_6xxx_mask)
1348  ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1349 
1350  /* load some data */
1351  n = comedi_buf_read_n_available(s->async);
1352  if (n == 0)
1353  return 0;
1354 
1355  n /= sizeof(short);
1356  if (n > boardtype.ao_fifo_depth)
1357  n = boardtype.ao_fifo_depth;
1358 
1359  ni_ao_fifo_load(dev, s, n);
1360 
1361  return n;
1362 }
1363 
1364 static void ni_ai_fifo_read(struct comedi_device *dev,
1365  struct comedi_subdevice *s, int n)
1366 {
1367  struct comedi_async *async = s->async;
1368  int i;
1369 
1370  if (boardtype.reg_type == ni_reg_611x) {
1371  short data[2];
1372  u32 dl;
1373 
1374  for (i = 0; i < n / 2; i++) {
1375  dl = ni_readl(ADC_FIFO_Data_611x);
1376  /* This may get the hi/lo data in the wrong order */
1377  data[0] = (dl >> 16) & 0xffff;
1378  data[1] = dl & 0xffff;
1379  cfc_write_array_to_buffer(s, data, sizeof(data));
1380  }
1381  /* Check if there's a single sample stuck in the FIFO */
1382  if (n % 2) {
1383  dl = ni_readl(ADC_FIFO_Data_611x);
1384  data[0] = dl & 0xffff;
1385  cfc_write_to_buffer(s, data[0]);
1386  }
1387  } else if (boardtype.reg_type == ni_reg_6143) {
1388  short data[2];
1389  u32 dl;
1390 
1391  /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1392  for (i = 0; i < n / 2; i++) {
1393  dl = ni_readl(AIFIFO_Data_6143);
1394 
1395  data[0] = (dl >> 16) & 0xffff;
1396  data[1] = dl & 0xffff;
1397  cfc_write_array_to_buffer(s, data, sizeof(data));
1398  }
1399  if (n % 2) {
1400  /* Assume there is a single sample stuck in the FIFO */
1401  ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1402  dl = ni_readl(AIFIFO_Data_6143);
1403  data[0] = (dl >> 16) & 0xffff;
1404  cfc_write_to_buffer(s, data[0]);
1405  }
1406  } else {
1407  if (n > sizeof(devpriv->ai_fifo_buffer) /
1408  sizeof(devpriv->ai_fifo_buffer[0])) {
1409  comedi_error(dev, "bug! ai_fifo_buffer too small");
1410  async->events |= COMEDI_CB_ERROR;
1411  return;
1412  }
1413  for (i = 0; i < n; i++) {
1414  devpriv->ai_fifo_buffer[i] =
1415  ni_readw(ADC_FIFO_Data_Register);
1416  }
1417  cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1418  n *
1419  sizeof(devpriv->ai_fifo_buffer[0]));
1420  }
1421 }
1422 
1423 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1424 {
1425  int n;
1426  struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1427 
1428  n = boardtype.ai_fifo_depth / 2;
1429 
1430  ni_ai_fifo_read(dev, s, n);
1431 }
1432 #endif
1433 
1434 #ifdef PCIDMA
1435 static int ni_ai_drain_dma(struct comedi_device *dev)
1436 {
1437  int i;
1438  static const int timeout = 10000;
1439  unsigned long flags;
1440  int retval = 0;
1441 
1442  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1443  if (devpriv->ai_mite_chan) {
1444  for (i = 0; i < timeout; i++) {
1445  if ((devpriv->stc_readw(dev,
1446  AI_Status_1_Register) &
1447  AI_FIFO_Empty_St)
1448  && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1449  0)
1450  break;
1451  udelay(5);
1452  }
1453  if (i == timeout) {
1454  printk("ni_mio_common: wait for dma drain timed out\n");
1455  printk
1456  ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1457  mite_bytes_in_transit(devpriv->ai_mite_chan),
1458  devpriv->stc_readw(dev, AI_Status_1_Register));
1459  retval = -1;
1460  }
1461  }
1462  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1463 
1464  ni_sync_ai_dma(dev);
1465 
1466  return retval;
1467 }
1468 #endif
1469 /*
1470  Empties the AI fifo
1471 */
1472 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1473 {
1474  struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1475  short data[2];
1476  u32 dl;
1477  short fifo_empty;
1478  int i;
1479 
1480  if (boardtype.reg_type == ni_reg_611x) {
1481  while ((devpriv->stc_readw(dev,
1482  AI_Status_1_Register) &
1483  AI_FIFO_Empty_St) == 0) {
1484  dl = ni_readl(ADC_FIFO_Data_611x);
1485 
1486  /* This may get the hi/lo data in the wrong order */
1487  data[0] = (dl >> 16);
1488  data[1] = (dl & 0xffff);
1489  cfc_write_array_to_buffer(s, data, sizeof(data));
1490  }
1491  } else if (boardtype.reg_type == ni_reg_6143) {
1492  i = 0;
1493  while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1494  dl = ni_readl(AIFIFO_Data_6143);
1495 
1496  /* This may get the hi/lo data in the wrong order */
1497  data[0] = (dl >> 16);
1498  data[1] = (dl & 0xffff);
1499  cfc_write_array_to_buffer(s, data, sizeof(data));
1500  i += 2;
1501  }
1502  /* Check if stranded sample is present */
1503  if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1504  ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1505  dl = ni_readl(AIFIFO_Data_6143);
1506  data[0] = (dl >> 16) & 0xffff;
1507  cfc_write_to_buffer(s, data[0]);
1508  }
1509 
1510  } else {
1511  fifo_empty =
1512  devpriv->stc_readw(dev,
1513  AI_Status_1_Register) & AI_FIFO_Empty_St;
1514  while (fifo_empty == 0) {
1515  for (i = 0;
1516  i <
1517  sizeof(devpriv->ai_fifo_buffer) /
1518  sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1519  fifo_empty =
1520  devpriv->stc_readw(dev,
1521  AI_Status_1_Register) &
1522  AI_FIFO_Empty_St;
1523  if (fifo_empty)
1524  break;
1525  devpriv->ai_fifo_buffer[i] =
1526  ni_readw(ADC_FIFO_Data_Register);
1527  }
1528  cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1529  i *
1530  sizeof(devpriv->
1531  ai_fifo_buffer[0]));
1532  }
1533  }
1534 }
1535 
1536 static void get_last_sample_611x(struct comedi_device *dev)
1537 {
1538  struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1539  short data;
1540  u32 dl;
1541 
1542  if (boardtype.reg_type != ni_reg_611x)
1543  return;
1544 
1545  /* Check if there's a single sample stuck in the FIFO */
1546  if (ni_readb(XXX_Status) & 0x80) {
1547  dl = ni_readl(ADC_FIFO_Data_611x);
1548  data = (dl & 0xffff);
1549  cfc_write_to_buffer(s, data);
1550  }
1551 }
1552 
1553 static void get_last_sample_6143(struct comedi_device *dev)
1554 {
1555  struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1556  short data;
1557  u32 dl;
1558 
1559  if (boardtype.reg_type != ni_reg_6143)
1560  return;
1561 
1562  /* Check if there's a single sample stuck in the FIFO */
1563  if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1564  ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1565  dl = ni_readl(AIFIFO_Data_6143);
1566 
1567  /* This may get the hi/lo data in the wrong order */
1568  data = (dl >> 16) & 0xffff;
1569  cfc_write_to_buffer(s, data);
1570  }
1571 }
1572 
1573 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1574  void *data, unsigned int num_bytes,
1575  unsigned int chan_index)
1576 {
1577  struct comedi_async *async = s->async;
1578  unsigned int i;
1579  unsigned int length = num_bytes / bytes_per_sample(s);
1580  short *array = data;
1581  unsigned int *larray = data;
1582  for (i = 0; i < length; i++) {
1583 #ifdef PCIDMA
1584  if (s->subdev_flags & SDF_LSAMPL)
1585  larray[i] = le32_to_cpu(larray[i]);
1586  else
1587  array[i] = le16_to_cpu(array[i]);
1588 #endif
1589  if (s->subdev_flags & SDF_LSAMPL)
1590  larray[i] += devpriv->ai_offset[chan_index];
1591  else
1592  array[i] += devpriv->ai_offset[chan_index];
1593  chan_index++;
1594  chan_index %= async->cmd.chanlist_len;
1595  }
1596 }
1597 
1598 #ifdef PCIDMA
1599 
1600 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1601 {
1602  struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1603  int retval;
1604  unsigned long flags;
1605 
1606  retval = ni_request_ai_mite_channel(dev);
1607  if (retval)
1608  return retval;
1609 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1610 
1611  /* write alloc the entire buffer */
1612  comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1613 
1614  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1615  if (devpriv->ai_mite_chan == NULL) {
1616  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1617  return -EIO;
1618  }
1619 
1620  switch (boardtype.reg_type) {
1621  case ni_reg_611x:
1622  case ni_reg_6143:
1623  mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1624  break;
1625  case ni_reg_628x:
1626  mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1627  break;
1628  default:
1629  mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1630  break;
1631  }
1632  /*start the MITE */
1633  mite_dma_arm(devpriv->ai_mite_chan);
1634  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1635 
1636  return 0;
1637 }
1638 
1639 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1640 {
1641  struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1642  int retval;
1643  unsigned long flags;
1644 
1645  retval = ni_request_ao_mite_channel(dev);
1646  if (retval)
1647  return retval;
1648 
1649  /* read alloc the entire buffer */
1650  comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1651 
1652  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1653  if (devpriv->ao_mite_chan) {
1654  if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1655  mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1656  } else {
1657  /* doing 32 instead of 16 bit wide transfers from memory
1658  makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1659  mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1660  }
1661  mite_dma_arm(devpriv->ao_mite_chan);
1662  } else
1663  retval = -EIO;
1664  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1665 
1666  return retval;
1667 }
1668 
1669 #endif /* PCIDMA */
1670 
1671 /*
1672  used for both cancel ioctl and board initialization
1673 
1674  this is pretty harsh for a cancel, but it works...
1675  */
1676 
1677 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1678 {
1679  ni_release_ai_mite_channel(dev);
1680  /* ai configuration */
1681  devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1682  Joint_Reset_Register);
1683 
1684  ni_set_bits(dev, Interrupt_A_Enable_Register,
1685  AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1686  AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1687  AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1688  AI_FIFO_Interrupt_Enable, 0);
1689 
1690  ni_clear_ai_fifo(dev);
1691 
1692  if (boardtype.reg_type != ni_reg_6143)
1693  ni_writeb(0, Misc_Command);
1694 
1695  devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1696  devpriv->stc_writew(dev,
1697  AI_Start_Stop | AI_Mode_1_Reserved
1698  /*| AI_Trigger_Once */ ,
1699  AI_Mode_1_Register);
1700  devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1701  /* generate FIFO interrupts on non-empty */
1702  devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1703  if (boardtype.reg_type == ni_reg_611x) {
1704  devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1705  AI_SOC_Polarity |
1706  AI_LOCALMUX_CLK_Pulse_Width,
1707  AI_Personal_Register);
1708  devpriv->stc_writew(dev,
1709  AI_SCAN_IN_PROG_Output_Select(3) |
1710  AI_EXTMUX_CLK_Output_Select(0) |
1711  AI_LOCALMUX_CLK_Output_Select(2) |
1712  AI_SC_TC_Output_Select(3) |
1713  AI_CONVERT_Output_Select
1714  (AI_CONVERT_Output_Enable_High),
1715  AI_Output_Control_Register);
1716  } else if (boardtype.reg_type == ni_reg_6143) {
1717  devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1718  AI_SOC_Polarity |
1719  AI_LOCALMUX_CLK_Pulse_Width,
1720  AI_Personal_Register);
1721  devpriv->stc_writew(dev,
1722  AI_SCAN_IN_PROG_Output_Select(3) |
1723  AI_EXTMUX_CLK_Output_Select(0) |
1724  AI_LOCALMUX_CLK_Output_Select(2) |
1725  AI_SC_TC_Output_Select(3) |
1726  AI_CONVERT_Output_Select
1727  (AI_CONVERT_Output_Enable_Low),
1728  AI_Output_Control_Register);
1729  } else {
1730  unsigned ai_output_control_bits;
1731  devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1732  AI_SOC_Polarity |
1733  AI_CONVERT_Pulse_Width |
1734  AI_LOCALMUX_CLK_Pulse_Width,
1735  AI_Personal_Register);
1736  ai_output_control_bits =
1737  AI_SCAN_IN_PROG_Output_Select(3) |
1738  AI_EXTMUX_CLK_Output_Select(0) |
1739  AI_LOCALMUX_CLK_Output_Select(2) |
1740  AI_SC_TC_Output_Select(3);
1741  if (boardtype.reg_type == ni_reg_622x)
1742  ai_output_control_bits |=
1743  AI_CONVERT_Output_Select
1744  (AI_CONVERT_Output_Enable_High);
1745  else
1746  ai_output_control_bits |=
1747  AI_CONVERT_Output_Select
1748  (AI_CONVERT_Output_Enable_Low);
1749  devpriv->stc_writew(dev, ai_output_control_bits,
1750  AI_Output_Control_Register);
1751  }
1752  /* the following registers should not be changed, because there
1753  * are no backup registers in devpriv. If you want to change
1754  * any of these, add a backup register and other appropriate code:
1755  * AI_Mode_1_Register
1756  * AI_Mode_3_Register
1757  * AI_Personal_Register
1758  * AI_Output_Control_Register
1759  */
1760  devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1761 
1762  devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1763 
1764  return 0;
1765 }
1766 
1767 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1768 {
1769  unsigned long flags;
1770  int count;
1771 
1772  /* lock to avoid race with interrupt handler */
1773  spin_lock_irqsave(&dev->spinlock, flags);
1774 #ifndef PCIDMA
1775  ni_handle_fifo_dregs(dev);
1776 #else
1777  ni_sync_ai_dma(dev);
1778 #endif
1779  count = s->async->buf_write_count - s->async->buf_read_count;
1780  spin_unlock_irqrestore(&dev->spinlock, flags);
1781 
1782  return count;
1783 }
1784 
1785 static int ni_ai_insn_read(struct comedi_device *dev,
1786  struct comedi_subdevice *s, struct comedi_insn *insn,
1787  unsigned int *data)
1788 {
1789  int i, n;
1790  const unsigned int mask = (1 << boardtype.adbits) - 1;
1791  unsigned signbits;
1792  unsigned short d;
1793  unsigned long dl;
1794 
1795  ni_load_channelgain_list(dev, 1, &insn->chanspec);
1796 
1797  ni_clear_ai_fifo(dev);
1798 
1799  signbits = devpriv->ai_offset[0];
1800  if (boardtype.reg_type == ni_reg_611x) {
1801  for (n = 0; n < num_adc_stages_611x; n++) {
1802  devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1803  AI_Command_1_Register);
1804  udelay(1);
1805  }
1806  for (n = 0; n < insn->n; n++) {
1807  devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1808  AI_Command_1_Register);
1809  /* The 611x has screwy 32-bit FIFOs. */
1810  d = 0;
1811  for (i = 0; i < NI_TIMEOUT; i++) {
1812  if (ni_readb(XXX_Status) & 0x80) {
1813  d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1814  & 0xffff;
1815  break;
1816  }
1817  if (!(devpriv->stc_readw(dev,
1818  AI_Status_1_Register) &
1819  AI_FIFO_Empty_St)) {
1820  d = ni_readl(ADC_FIFO_Data_611x) &
1821  0xffff;
1822  break;
1823  }
1824  }
1825  if (i == NI_TIMEOUT) {
1826  printk
1827  ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1828  return -ETIME;
1829  }
1830  d += signbits;
1831  data[n] = d;
1832  }
1833  } else if (boardtype.reg_type == ni_reg_6143) {
1834  for (n = 0; n < insn->n; n++) {
1835  devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1836  AI_Command_1_Register);
1837 
1838  /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1839  dl = 0;
1840  for (i = 0; i < NI_TIMEOUT; i++) {
1841  if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1842  ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1843  dl = ni_readl(AIFIFO_Data_6143);
1844  break;
1845  }
1846  }
1847  if (i == NI_TIMEOUT) {
1848  printk
1849  ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1850  return -ETIME;
1851  }
1852  data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1853  }
1854  } else {
1855  for (n = 0; n < insn->n; n++) {
1856  devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1857  AI_Command_1_Register);
1858  for (i = 0; i < NI_TIMEOUT; i++) {
1859  if (!(devpriv->stc_readw(dev,
1860  AI_Status_1_Register) &
1861  AI_FIFO_Empty_St))
1862  break;
1863  }
1864  if (i == NI_TIMEOUT) {
1865  printk
1866  ("ni_mio_common: timeout in ni_ai_insn_read\n");
1867  return -ETIME;
1868  }
1869  if (boardtype.reg_type & ni_reg_m_series_mask) {
1870  data[n] =
1871  ni_readl(M_Offset_AI_FIFO_Data) & mask;
1872  } else {
1873  d = ni_readw(ADC_FIFO_Data_Register);
1874  d += signbits; /* subtle: needs to be short addition */
1875  data[n] = d;
1876  }
1877  }
1878  }
1879  return insn->n;
1880 }
1881 
1882 static void ni_prime_channelgain_list(struct comedi_device *dev)
1883 {
1884  int i;
1885  devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1886  for (i = 0; i < NI_TIMEOUT; ++i) {
1887  if (!(devpriv->stc_readw(dev,
1888  AI_Status_1_Register) &
1889  AI_FIFO_Empty_St)) {
1890  devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1891  return;
1892  }
1893  udelay(1);
1894  }
1895  printk("ni_mio_common: timeout loading channel/gain list\n");
1896 }
1897 
1898 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1899  unsigned int n_chan,
1900  unsigned int *list)
1901 {
1902  unsigned int chan, range, aref;
1903  unsigned int i;
1904  unsigned offset;
1905  unsigned int dither;
1906  unsigned range_code;
1907 
1908  devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1909 
1910 /* offset = 1 << (boardtype.adbits - 1); */
1911  if ((list[0] & CR_ALT_SOURCE)) {
1912  unsigned bypass_bits;
1913  chan = CR_CHAN(list[0]);
1914  range = CR_RANGE(list[0]);
1915  range_code = ni_gainlkup[boardtype.gainlkup][range];
1916  dither = ((list[0] & CR_ALT_FILTER) != 0);
1917  bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1918  bypass_bits |= chan;
1919  bypass_bits |=
1920  (devpriv->ai_calib_source) &
1921  (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1922  MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1923  MSeries_AI_Bypass_Mode_Mux_Mask |
1924  MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1925  bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1926  if (dither)
1927  bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1928  /* don't use 2's complement encoding */
1929  bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1930  ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1931  } else {
1932  ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1933  }
1934  offset = 0;
1935  for (i = 0; i < n_chan; i++) {
1936  unsigned config_bits = 0;
1937  chan = CR_CHAN(list[i]);
1938  aref = CR_AREF(list[i]);
1939  range = CR_RANGE(list[i]);
1940  dither = ((list[i] & CR_ALT_FILTER) != 0);
1941 
1942  range_code = ni_gainlkup[boardtype.gainlkup][range];
1943  devpriv->ai_offset[i] = offset;
1944  switch (aref) {
1945  case AREF_DIFF:
1946  config_bits |=
1947  MSeries_AI_Config_Channel_Type_Differential_Bits;
1948  break;
1949  case AREF_COMMON:
1950  config_bits |=
1951  MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1952  break;
1953  case AREF_GROUND:
1954  config_bits |=
1955  MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1956  break;
1957  case AREF_OTHER:
1958  break;
1959  }
1960  config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1961  config_bits |=
1962  MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
1963  config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1964  if (i == n_chan - 1)
1965  config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1966  if (dither)
1967  config_bits |= MSeries_AI_Config_Dither_Bit;
1968  /* don't use 2's complement encoding */
1969  config_bits |= MSeries_AI_Config_Polarity_Bit;
1970  ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1971  }
1972  ni_prime_channelgain_list(dev);
1973 }
1974 
1975 /*
1976  * Notes on the 6110 and 6111:
1977  * These boards a slightly different than the rest of the series, since
1978  * they have multiple A/D converters.
1979  * From the driver side, the configuration memory is a
1980  * little different.
1981  * Configuration Memory Low:
1982  * bits 15-9: same
1983  * bit 8: unipolar/bipolar (should be 0 for bipolar)
1984  * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1985  * 1001 gain=0.1 (+/- 50)
1986  * 1010 0.2
1987  * 1011 0.1
1988  * 0001 1
1989  * 0010 2
1990  * 0011 5
1991  * 0100 10
1992  * 0101 20
1993  * 0110 50
1994  * Configuration Memory High:
1995  * bits 12-14: Channel Type
1996  * 001 for differential
1997  * 000 for calibration
1998  * bit 11: coupling (this is not currently handled)
1999  * 1 AC coupling
2000  * 0 DC coupling
2001  * bits 0-2: channel
2002  * valid channels are 0-3
2003  */
2004 static void ni_load_channelgain_list(struct comedi_device *dev,
2005  unsigned int n_chan, unsigned int *list)
2006 {
2007  unsigned int chan, range, aref;
2008  unsigned int i;
2009  unsigned int hi, lo;
2010  unsigned offset;
2011  unsigned int dither;
2012 
2013  if (boardtype.reg_type & ni_reg_m_series_mask) {
2014  ni_m_series_load_channelgain_list(dev, n_chan, list);
2015  return;
2016  }
2017  if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
2018  && (boardtype.reg_type != ni_reg_6143)) {
2019  if (devpriv->changain_state
2020  && devpriv->changain_spec == list[0]) {
2021  /* ready to go. */
2022  return;
2023  }
2024  devpriv->changain_state = 1;
2025  devpriv->changain_spec = list[0];
2026  } else {
2027  devpriv->changain_state = 0;
2028  }
2029 
2030  devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2031 
2032  /* Set up Calibration mode if required */
2033  if (boardtype.reg_type == ni_reg_6143) {
2034  if ((list[0] & CR_ALT_SOURCE)
2035  && !devpriv->ai_calib_source_enabled) {
2036  /* Strobe Relay enable bit */
2037  ni_writew(devpriv->ai_calib_source |
2038  Calibration_Channel_6143_RelayOn,
2039  Calibration_Channel_6143);
2040  ni_writew(devpriv->ai_calib_source,
2041  Calibration_Channel_6143);
2042  devpriv->ai_calib_source_enabled = 1;
2043  msleep_interruptible(100); /* Allow relays to change */
2044  } else if (!(list[0] & CR_ALT_SOURCE)
2045  && devpriv->ai_calib_source_enabled) {
2046  /* Strobe Relay disable bit */
2047  ni_writew(devpriv->ai_calib_source |
2048  Calibration_Channel_6143_RelayOff,
2049  Calibration_Channel_6143);
2050  ni_writew(devpriv->ai_calib_source,
2051  Calibration_Channel_6143);
2052  devpriv->ai_calib_source_enabled = 0;
2053  msleep_interruptible(100); /* Allow relays to change */
2054  }
2055  }
2056 
2057  offset = 1 << (boardtype.adbits - 1);
2058  for (i = 0; i < n_chan; i++) {
2059  if ((boardtype.reg_type != ni_reg_6143)
2060  && (list[i] & CR_ALT_SOURCE)) {
2061  chan = devpriv->ai_calib_source;
2062  } else {
2063  chan = CR_CHAN(list[i]);
2064  }
2065  aref = CR_AREF(list[i]);
2066  range = CR_RANGE(list[i]);
2067  dither = ((list[i] & CR_ALT_FILTER) != 0);
2068 
2069  /* fix the external/internal range differences */
2070  range = ni_gainlkup[boardtype.gainlkup][range];
2071  if (boardtype.reg_type == ni_reg_611x)
2072  devpriv->ai_offset[i] = offset;
2073  else
2074  devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2075 
2076  hi = 0;
2077  if ((list[i] & CR_ALT_SOURCE)) {
2078  if (boardtype.reg_type == ni_reg_611x)
2079  ni_writew(CR_CHAN(list[i]) & 0x0003,
2080  Calibration_Channel_Select_611x);
2081  } else {
2082  if (boardtype.reg_type == ni_reg_611x)
2083  aref = AREF_DIFF;
2084  else if (boardtype.reg_type == ni_reg_6143)
2085  aref = AREF_OTHER;
2086  switch (aref) {
2087  case AREF_DIFF:
2088  hi |= AI_DIFFERENTIAL;
2089  break;
2090  case AREF_COMMON:
2091  hi |= AI_COMMON;
2092  break;
2093  case AREF_GROUND:
2094  hi |= AI_GROUND;
2095  break;
2096  case AREF_OTHER:
2097  break;
2098  }
2099  }
2100  hi |= AI_CONFIG_CHANNEL(chan);
2101 
2102  ni_writew(hi, Configuration_Memory_High);
2103 
2104  if (boardtype.reg_type != ni_reg_6143) {
2105  lo = range;
2106  if (i == n_chan - 1)
2107  lo |= AI_LAST_CHANNEL;
2108  if (dither)
2109  lo |= AI_DITHER;
2110 
2111  ni_writew(lo, Configuration_Memory_Low);
2112  }
2113  }
2114 
2115  /* prime the channel/gain list */
2116  if ((boardtype.reg_type != ni_reg_611x)
2117  && (boardtype.reg_type != ni_reg_6143)) {
2118  ni_prime_channelgain_list(dev);
2119  }
2120 }
2121 
2122 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2123  int round_mode)
2124 {
2125  int divider;
2126  switch (round_mode) {
2127  case TRIG_ROUND_NEAREST:
2128  default:
2129  divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2130  break;
2131  case TRIG_ROUND_DOWN:
2132  divider = (nanosec) / devpriv->clock_ns;
2133  break;
2134  case TRIG_ROUND_UP:
2135  divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2136  break;
2137  }
2138  return divider - 1;
2139 }
2140 
2141 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2142 {
2143  return devpriv->clock_ns * (timer + 1);
2144 }
2145 
2146 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2147  unsigned num_channels)
2148 {
2149  switch (boardtype.reg_type) {
2150  case ni_reg_611x:
2151  case ni_reg_6143:
2152  /* simultaneously-sampled inputs */
2153  return boardtype.ai_speed;
2154  break;
2155  default:
2156  /* multiplexed inputs */
2157  break;
2158  }
2159  return boardtype.ai_speed * num_channels;
2160 }
2161 
2162 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2163  struct comedi_cmd *cmd)
2164 {
2165  int err = 0;
2166  int tmp;
2167  unsigned int sources;
2168 
2169  /* Step 1 : check if triggers are trivially valid */
2170 
2171  if ((cmd->flags & CMDF_WRITE))
2172  cmd->flags &= ~CMDF_WRITE;
2173 
2174  err |= cfc_check_trigger_src(&cmd->start_src,
2175  TRIG_NOW | TRIG_INT | TRIG_EXT);
2176  err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2177  TRIG_TIMER | TRIG_EXT);
2178 
2179  sources = TRIG_TIMER | TRIG_EXT;
2180  if (boardtype.reg_type == ni_reg_611x ||
2181  boardtype.reg_type == ni_reg_6143)
2182  sources |= TRIG_NOW;
2183  err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2184 
2185  err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2186  err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2187 
2188  if (err)
2189  return 1;
2190 
2191  /* Step 2a : make sure trigger sources are unique */
2192 
2193  err |= cfc_check_trigger_is_unique(cmd->start_src);
2194  err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2195  err |= cfc_check_trigger_is_unique(cmd->convert_src);
2196  err |= cfc_check_trigger_is_unique(cmd->stop_src);
2197 
2198  /* Step 2b : and mutually compatible */
2199 
2200  if (err)
2201  return 2;
2202 
2203  /* step 3: make sure arguments are trivially compatible */
2204 
2205  if (cmd->start_src == TRIG_EXT) {
2206  /* external trigger */
2207  unsigned int tmp = CR_CHAN(cmd->start_arg);
2208 
2209  if (tmp > 16)
2210  tmp = 16;
2211  tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2212  if (cmd->start_arg != tmp) {
2213  cmd->start_arg = tmp;
2214  err++;
2215  }
2216  } else {
2217  if (cmd->start_arg != 0) {
2218  /* true for both TRIG_NOW and TRIG_INT */
2219  cmd->start_arg = 0;
2220  err++;
2221  }
2222  }
2223  if (cmd->scan_begin_src == TRIG_TIMER) {
2224  if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev,
2225  cmd->
2226  chanlist_len))
2227  {
2228  cmd->scan_begin_arg =
2229  ni_min_ai_scan_period_ns(dev, cmd->chanlist_len);
2230  err++;
2231  }
2232  if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {
2233  cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2234  err++;
2235  }
2236  } else if (cmd->scan_begin_src == TRIG_EXT) {
2237  /* external trigger */
2238  unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2239 
2240  if (tmp > 16)
2241  tmp = 16;
2242  tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2243  if (cmd->scan_begin_arg != tmp) {
2244  cmd->scan_begin_arg = tmp;
2245  err++;
2246  }
2247  } else { /* TRIG_OTHER */
2248  if (cmd->scan_begin_arg) {
2249  cmd->scan_begin_arg = 0;
2250  err++;
2251  }
2252  }
2253  if (cmd->convert_src == TRIG_TIMER) {
2254  if ((boardtype.reg_type == ni_reg_611x)
2255  || (boardtype.reg_type == ni_reg_6143)) {
2256  if (cmd->convert_arg != 0) {
2257  cmd->convert_arg = 0;
2258  err++;
2259  }
2260  } else {
2261  if (cmd->convert_arg < boardtype.ai_speed) {
2262  cmd->convert_arg = boardtype.ai_speed;
2263  err++;
2264  }
2265  if (cmd->convert_arg > devpriv->clock_ns * 0xffff) {
2266  cmd->convert_arg = devpriv->clock_ns * 0xffff;
2267  err++;
2268  }
2269  }
2270  } else if (cmd->convert_src == TRIG_EXT) {
2271  /* external trigger */
2272  unsigned int tmp = CR_CHAN(cmd->convert_arg);
2273 
2274  if (tmp > 16)
2275  tmp = 16;
2276  tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2277  if (cmd->convert_arg != tmp) {
2278  cmd->convert_arg = tmp;
2279  err++;
2280  }
2281  } else if (cmd->convert_src == TRIG_NOW) {
2282  if (cmd->convert_arg != 0) {
2283  cmd->convert_arg = 0;
2284  err++;
2285  }
2286  }
2287 
2288  if (cmd->scan_end_arg != cmd->chanlist_len) {
2289  cmd->scan_end_arg = cmd->chanlist_len;
2290  err++;
2291  }
2292  if (cmd->stop_src == TRIG_COUNT) {
2293  unsigned int max_count = 0x01000000;
2294 
2295  if (boardtype.reg_type == ni_reg_611x)
2296  max_count -= num_adc_stages_611x;
2297  if (cmd->stop_arg > max_count) {
2298  cmd->stop_arg = max_count;
2299  err++;
2300  }
2301  if (cmd->stop_arg < 1) {
2302  cmd->stop_arg = 1;
2303  err++;
2304  }
2305  } else {
2306  /* TRIG_NONE */
2307  if (cmd->stop_arg != 0) {
2308  cmd->stop_arg = 0;
2309  err++;
2310  }
2311  }
2312 
2313  if (err)
2314  return 3;
2315 
2316  /* step 4: fix up any arguments */
2317 
2318  if (cmd->scan_begin_src == TRIG_TIMER) {
2319  tmp = cmd->scan_begin_arg;
2320  cmd->scan_begin_arg =
2321  ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2322  cmd->scan_begin_arg,
2323  cmd->
2324  flags &
2325  TRIG_ROUND_MASK));
2326  if (tmp != cmd->scan_begin_arg)
2327  err++;
2328  }
2329  if (cmd->convert_src == TRIG_TIMER) {
2330  if ((boardtype.reg_type != ni_reg_611x)
2331  && (boardtype.reg_type != ni_reg_6143)) {
2332  tmp = cmd->convert_arg;
2333  cmd->convert_arg =
2334  ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2335  cmd->convert_arg,
2336  cmd->
2337  flags &
2338  TRIG_ROUND_MASK));
2339  if (tmp != cmd->convert_arg)
2340  err++;
2341  if (cmd->scan_begin_src == TRIG_TIMER &&
2342  cmd->scan_begin_arg <
2343  cmd->convert_arg * cmd->scan_end_arg) {
2344  cmd->scan_begin_arg =
2345  cmd->convert_arg * cmd->scan_end_arg;
2346  err++;
2347  }
2348  }
2349  }
2350 
2351  if (err)
2352  return 4;
2353 
2354  return 0;
2355 }
2356 
2357 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2358 {
2359  const struct comedi_cmd *cmd = &s->async->cmd;
2360  int timer;
2361  int mode1 = 0; /* mode1 is needed for both stop and convert */
2362  int mode2 = 0;
2363  int start_stop_select = 0;
2364  unsigned int stop_count;
2365  int interrupt_a_enable = 0;
2366 
2367  MDPRINTK("ni_ai_cmd\n");
2368  if (dev->irq == 0) {
2369  comedi_error(dev, "cannot run command without an irq");
2370  return -EIO;
2371  }
2372  ni_clear_ai_fifo(dev);
2373 
2374  ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2375 
2376  /* start configuration */
2377  devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2378 
2379  /* disable analog triggering for now, since it
2380  * interferes with the use of pfi0 */
2381  devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2382  devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2383  Analog_Trigger_Etc_Register);
2384 
2385  switch (cmd->start_src) {
2386  case TRIG_INT:
2387  case TRIG_NOW:
2388  devpriv->stc_writew(dev, AI_START2_Select(0) |
2389  AI_START1_Sync | AI_START1_Edge |
2390  AI_START1_Select(0),
2391  AI_Trigger_Select_Register);
2392  break;
2393  case TRIG_EXT:
2394  {
2395  int chan = CR_CHAN(cmd->start_arg);
2396  unsigned int bits = AI_START2_Select(0) |
2397  AI_START1_Sync | AI_START1_Select(chan + 1);
2398 
2399  if (cmd->start_arg & CR_INVERT)
2400  bits |= AI_START1_Polarity;
2401  if (cmd->start_arg & CR_EDGE)
2402  bits |= AI_START1_Edge;
2403  devpriv->stc_writew(dev, bits,
2404  AI_Trigger_Select_Register);
2405  break;
2406  }
2407  }
2408 
2409  mode2 &= ~AI_Pre_Trigger;
2410  mode2 &= ~AI_SC_Initial_Load_Source;
2411  mode2 &= ~AI_SC_Reload_Mode;
2412  devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2413 
2414  if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2415  || (boardtype.reg_type == ni_reg_6143)) {
2416  start_stop_select |= AI_STOP_Polarity;
2417  start_stop_select |= AI_STOP_Select(31); /* logic low */
2418  start_stop_select |= AI_STOP_Sync;
2419  } else {
2420  start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2421  }
2422  devpriv->stc_writew(dev, start_stop_select,
2423  AI_START_STOP_Select_Register);
2424 
2425  devpriv->ai_cmd2 = 0;
2426  switch (cmd->stop_src) {
2427  case TRIG_COUNT:
2428  stop_count = cmd->stop_arg - 1;
2429 
2430  if (boardtype.reg_type == ni_reg_611x) {
2431  /* have to take 3 stage adc pipeline into account */
2432  stop_count += num_adc_stages_611x;
2433  }
2434  /* stage number of scans */
2435  devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2436 
2437  mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2438  devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2439  /* load SC (Scan Count) */
2440  devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2441 
2442  devpriv->ai_continuous = 0;
2443  if (stop_count == 0) {
2444  devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2445  interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2446  /* this is required to get the last sample for chanlist_len > 1, not sure why */
2447  if (cmd->chanlist_len > 1)
2448  start_stop_select |=
2449  AI_STOP_Polarity | AI_STOP_Edge;
2450  }
2451  break;
2452  case TRIG_NONE:
2453  /* stage number of scans */
2454  devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2455 
2456  mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2457  devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2458 
2459  /* load SC (Scan Count) */
2460  devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2461 
2462  devpriv->ai_continuous = 1;
2463 
2464  break;
2465  }
2466 
2467  switch (cmd->scan_begin_src) {
2468  case TRIG_TIMER:
2469  /*
2470  stop bits for non 611x boards
2471  AI_SI_Special_Trigger_Delay=0
2472  AI_Pre_Trigger=0
2473  AI_START_STOP_Select_Register:
2474  AI_START_Polarity=0 (?) rising edge
2475  AI_START_Edge=1 edge triggered
2476  AI_START_Sync=1 (?)
2477  AI_START_Select=0 SI_TC
2478  AI_STOP_Polarity=0 rising edge
2479  AI_STOP_Edge=0 level
2480  AI_STOP_Sync=1
2481  AI_STOP_Select=19 external pin (configuration mem)
2482  */
2483  start_stop_select |= AI_START_Edge | AI_START_Sync;
2484  devpriv->stc_writew(dev, start_stop_select,
2485  AI_START_STOP_Select_Register);
2486 
2487  mode2 |= AI_SI_Reload_Mode(0);
2488  /* AI_SI_Initial_Load_Source=A */
2489  mode2 &= ~AI_SI_Initial_Load_Source;
2490  /* mode2 |= AI_SC_Reload_Mode; */
2491  devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2492 
2493  /* load SI */
2494  timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2495  TRIG_ROUND_NEAREST);
2496  devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2497  devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2498  break;
2499  case TRIG_EXT:
2500  if (cmd->scan_begin_arg & CR_EDGE)
2501  start_stop_select |= AI_START_Edge;
2502  /* AI_START_Polarity==1 is falling edge */
2503  if (cmd->scan_begin_arg & CR_INVERT)
2504  start_stop_select |= AI_START_Polarity;
2505  if (cmd->scan_begin_src != cmd->convert_src ||
2506  (cmd->scan_begin_arg & ~CR_EDGE) !=
2507  (cmd->convert_arg & ~CR_EDGE))
2508  start_stop_select |= AI_START_Sync;
2509  start_stop_select |=
2510  AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2511  devpriv->stc_writew(dev, start_stop_select,
2512  AI_START_STOP_Select_Register);
2513  break;
2514  }
2515 
2516  switch (cmd->convert_src) {
2517  case TRIG_TIMER:
2518  case TRIG_NOW:
2519  if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2520  timer = 1;
2521  else
2522  timer = ni_ns_to_timer(dev, cmd->convert_arg,
2523  TRIG_ROUND_NEAREST);
2524  devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2525  devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2526 
2527  /* AI_SI2_Reload_Mode = alternate */
2528  /* AI_SI2_Initial_Load_Source = A */
2529  mode2 &= ~AI_SI2_Initial_Load_Source;
2530  mode2 |= AI_SI2_Reload_Mode;
2531  devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2532 
2533  /* AI_SI2_Load */
2534  devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2535 
2536  mode2 |= AI_SI2_Reload_Mode; /* alternate */
2537  mode2 |= AI_SI2_Initial_Load_Source; /* B */
2538 
2539  devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2540  break;
2541  case TRIG_EXT:
2542  mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2543  if ((cmd->convert_arg & CR_INVERT) == 0)
2544  mode1 |= AI_CONVERT_Source_Polarity;
2545  devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2546 
2547  mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2548  devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2549 
2550  break;
2551  }
2552 
2553  if (dev->irq) {
2554 
2555  /* interrupt on FIFO, errors, SC_TC */
2556  interrupt_a_enable |= AI_Error_Interrupt_Enable |
2557  AI_SC_TC_Interrupt_Enable;
2558 
2559 #ifndef PCIDMA
2560  interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2561 #endif
2562 
2563  if (cmd->flags & TRIG_WAKE_EOS
2564  || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2565  /* wake on end-of-scan */
2566  devpriv->aimode = AIMODE_SCAN;
2567  } else {
2568  devpriv->aimode = AIMODE_HALF_FULL;
2569  }
2570 
2571  switch (devpriv->aimode) {
2572  case AIMODE_HALF_FULL:
2573  /*generate FIFO interrupts and DMA requests on half-full */
2574 #ifdef PCIDMA
2575  devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2576  AI_Mode_3_Register);
2577 #else
2578  devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2579  AI_Mode_3_Register);
2580 #endif
2581  break;
2582  case AIMODE_SAMPLE:
2583  /*generate FIFO interrupts on non-empty */
2584  devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2585  AI_Mode_3_Register);
2586  break;
2587  case AIMODE_SCAN:
2588 #ifdef PCIDMA
2589  devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2590  AI_Mode_3_Register);
2591 #else
2592  devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2593  AI_Mode_3_Register);
2594 #endif
2595  interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2596  break;
2597  default:
2598  break;
2599  }
2600 
2601  devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2602 
2603  ni_set_bits(dev, Interrupt_A_Enable_Register,
2604  interrupt_a_enable, 1);
2605 
2606  MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2607  devpriv->int_a_enable_reg);
2608  } else {
2609  /* interrupt on nothing */
2610  ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2611 
2612  /* XXX start polling if necessary */
2613  MDPRINTK("interrupting on nothing\n");
2614  }
2615 
2616  /* end configuration */
2617  devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2618 
2619  switch (cmd->scan_begin_src) {
2620  case TRIG_TIMER:
2621  devpriv->stc_writew(dev,
2622  AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2623  AI_SC_Arm, AI_Command_1_Register);
2624  break;
2625  case TRIG_EXT:
2626  /* XXX AI_SI_Arm? */
2627  devpriv->stc_writew(dev,
2628  AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2629  AI_SC_Arm, AI_Command_1_Register);
2630  break;
2631  }
2632 
2633 #ifdef PCIDMA
2634  {
2635  int retval = ni_ai_setup_MITE_dma(dev);
2636  if (retval)
2637  return retval;
2638  }
2639  /* mite_dump_regs(devpriv->mite); */
2640 #endif
2641 
2642  switch (cmd->start_src) {
2643  case TRIG_NOW:
2644  /* AI_START1_Pulse */
2645  devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2646  AI_Command_2_Register);
2647  s->async->inttrig = NULL;
2648  break;
2649  case TRIG_EXT:
2650  s->async->inttrig = NULL;
2651  break;
2652  case TRIG_INT:
2653  s->async->inttrig = &ni_ai_inttrig;
2654  break;
2655  }
2656 
2657  MDPRINTK("exit ni_ai_cmd\n");
2658 
2659  return 0;
2660 }
2661 
2662 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2663  unsigned int trignum)
2664 {
2665  if (trignum != 0)
2666  return -EINVAL;
2667 
2668  devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2669  AI_Command_2_Register);
2670  s->async->inttrig = NULL;
2671 
2672  return 1;
2673 }
2674 
2675 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2676  struct comedi_subdevice *s,
2677  struct comedi_insn *insn,
2678  unsigned int *data);
2679 
2680 static int ni_ai_insn_config(struct comedi_device *dev,
2681  struct comedi_subdevice *s,
2682  struct comedi_insn *insn, unsigned int *data)
2683 {
2684  if (insn->n < 1)
2685  return -EINVAL;
2686 
2687  switch (data[0]) {
2688  case INSN_CONFIG_ANALOG_TRIG:
2689  return ni_ai_config_analog_trig(dev, s, insn, data);
2690  case INSN_CONFIG_ALT_SOURCE:
2691  if (boardtype.reg_type & ni_reg_m_series_mask) {
2692  if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2693  MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2694  MSeries_AI_Bypass_Mode_Mux_Mask |
2695  MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2696  return -EINVAL;
2697  }
2698  devpriv->ai_calib_source = data[1];
2699  } else if (boardtype.reg_type == ni_reg_6143) {
2700  unsigned int calib_source;
2701 
2702  calib_source = data[1] & 0xf;
2703 
2704  if (calib_source > 0xF)
2705  return -EINVAL;
2706 
2707  devpriv->ai_calib_source = calib_source;
2708  ni_writew(calib_source, Calibration_Channel_6143);
2709  } else {
2710  unsigned int calib_source;
2711  unsigned int calib_source_adjust;
2712 
2713  calib_source = data[1] & 0xf;
2714  calib_source_adjust = (data[1] >> 4) & 0xff;
2715 
2716  if (calib_source >= 8)
2717  return -EINVAL;
2718  devpriv->ai_calib_source = calib_source;
2719  if (boardtype.reg_type == ni_reg_611x) {
2720  ni_writeb(calib_source_adjust,
2721  Cal_Gain_Select_611x);
2722  }
2723  }
2724  return 2;
2725  default:
2726  break;
2727  }
2728 
2729  return -EINVAL;
2730 }
2731 
2732 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2733  struct comedi_subdevice *s,
2734  struct comedi_insn *insn,
2735  unsigned int *data)
2736 {
2737  unsigned int a, b, modebits;
2738  int err = 0;
2739 
2740  /* data[1] is flags
2741  * data[2] is analog line
2742  * data[3] is set level
2743  * data[4] is reset level */
2744  if (!boardtype.has_analog_trig)
2745  return -EINVAL;
2746  if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2747  data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2748  err++;
2749  }
2750  if (data[2] >= boardtype.n_adchan) {
2751  data[2] = boardtype.n_adchan - 1;
2752  err++;
2753  }
2754  if (data[3] > 255) { /* a */
2755  data[3] = 255;
2756  err++;
2757  }
2758  if (data[4] > 255) { /* b */
2759  data[4] = 255;
2760  err++;
2761  }
2762  /*
2763  * 00 ignore
2764  * 01 set
2765  * 10 reset
2766  *
2767  * modes:
2768  * 1 level: +b- +a-
2769  * high mode 00 00 01 10
2770  * low mode 00 00 10 01
2771  * 2 level: (a<b)
2772  * hysteresis low mode 10 00 00 01
2773  * hysteresis high mode 01 00 00 10
2774  * middle mode 10 01 01 10
2775  */
2776 
2777  a = data[3];
2778  b = data[4];
2779  modebits = data[1] & 0xff;
2780  if (modebits & 0xf0) {
2781  /* two level mode */
2782  if (b < a) {
2783  /* swap order */
2784  a = data[4];
2785  b = data[3];
2786  modebits =
2787  ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2788  }
2789  devpriv->atrig_low = a;
2790  devpriv->atrig_high = b;
2791  switch (modebits) {
2792  case 0x81: /* low hysteresis mode */
2793  devpriv->atrig_mode = 6;
2794  break;
2795  case 0x42: /* high hysteresis mode */
2796  devpriv->atrig_mode = 3;
2797  break;
2798  case 0x96: /* middle window mode */
2799  devpriv->atrig_mode = 2;
2800  break;
2801  default:
2802  data[1] &= ~0xff;
2803  err++;
2804  }
2805  } else {
2806  /* one level mode */
2807  if (b != 0) {
2808  data[4] = 0;
2809  err++;
2810  }
2811  switch (modebits) {
2812  case 0x06: /* high window mode */
2813  devpriv->atrig_high = a;
2814  devpriv->atrig_mode = 0;
2815  break;
2816  case 0x09: /* low window mode */
2817  devpriv->atrig_low = a;
2818  devpriv->atrig_mode = 1;
2819  break;
2820  default:
2821  data[1] &= ~0xff;
2822  err++;
2823  }
2824  }
2825  if (err)
2826  return -EAGAIN;
2827  return 5;
2828 }
2829 
2830 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2831 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2832  void *data, unsigned int num_bytes,
2833  unsigned int chan_index)
2834 {
2835  struct comedi_async *async = s->async;
2836  unsigned int range;
2837  unsigned int i;
2838  unsigned int offset;
2839  unsigned int length = num_bytes / sizeof(short);
2840  short *array = data;
2841 
2842  offset = 1 << (boardtype.aobits - 1);
2843  for (i = 0; i < length; i++) {
2844  range = CR_RANGE(async->cmd.chanlist[chan_index]);
2845  if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2846  array[i] -= offset;
2847 #ifdef PCIDMA
2848  array[i] = cpu_to_le16(array[i]);
2849 #endif
2850  chan_index++;
2851  chan_index %= async->cmd.chanlist_len;
2852  }
2853 }
2854 
2855 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2856  struct comedi_subdevice *s,
2857  unsigned int chanspec[],
2858  unsigned int n_chans, int timed)
2859 {
2860  unsigned int range;
2861  unsigned int chan;
2862  unsigned int conf;
2863  int i;
2864  int invert = 0;
2865 
2866  if (timed) {
2867  for (i = 0; i < boardtype.n_aochan; ++i) {
2868  devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2869  ni_writeb(devpriv->ao_conf[i],
2870  M_Offset_AO_Config_Bank(i));
2871  ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2872  }
2873  }
2874  for (i = 0; i < n_chans; i++) {
2875  const struct comedi_krange *krange;
2876  chan = CR_CHAN(chanspec[i]);
2877  range = CR_RANGE(chanspec[i]);
2878  krange = s->range_table->range + range;
2879  invert = 0;
2880  conf = 0;
2881  switch (krange->max - krange->min) {
2882  case 20000000:
2883  conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2884  ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2885  break;
2886  case 10000000:
2887  conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2888  ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2889  break;
2890  case 4000000:
2891  conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2892  ni_writeb(MSeries_Attenuate_x5_Bit,
2893  M_Offset_AO_Reference_Attenuation(chan));
2894  break;
2895  case 2000000:
2896  conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2897  ni_writeb(MSeries_Attenuate_x5_Bit,
2898  M_Offset_AO_Reference_Attenuation(chan));
2899  break;
2900  default:
2901  printk("%s: bug! unhandled ao reference voltage\n",
2902  __func__);
2903  break;
2904  }
2905  switch (krange->max + krange->min) {
2906  case 0:
2907  conf |= MSeries_AO_DAC_Offset_0V_Bits;
2908  break;
2909  case 10000000:
2910  conf |= MSeries_AO_DAC_Offset_5V_Bits;
2911  break;
2912  default:
2913  printk("%s: bug! unhandled ao offset voltage\n",
2914  __func__);
2915  break;
2916  }
2917  if (timed)
2918  conf |= MSeries_AO_Update_Timed_Bit;
2919  ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2920  devpriv->ao_conf[chan] = conf;
2921  ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2922  }
2923  return invert;
2924 }
2925 
2926 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2927  struct comedi_subdevice *s,
2928  unsigned int chanspec[],
2929  unsigned int n_chans)
2930 {
2931  unsigned int range;
2932  unsigned int chan;
2933  unsigned int conf;
2934  int i;
2935  int invert = 0;
2936 
2937  for (i = 0; i < n_chans; i++) {
2938  chan = CR_CHAN(chanspec[i]);
2939  range = CR_RANGE(chanspec[i]);
2940  conf = AO_Channel(chan);
2941 
2942  if (boardtype.ao_unipolar) {
2943  if ((range & 1) == 0) {
2944  conf |= AO_Bipolar;
2945  invert = (1 << (boardtype.aobits - 1));
2946  } else {
2947  invert = 0;
2948  }
2949  if (range & 2)
2950  conf |= AO_Ext_Ref;
2951  } else {
2952  conf |= AO_Bipolar;
2953  invert = (1 << (boardtype.aobits - 1));
2954  }
2955 
2956  /* not all boards can deglitch, but this shouldn't hurt */
2957  if (chanspec[i] & CR_DEGLITCH)
2958  conf |= AO_Deglitch;
2959 
2960  /* analog reference */
2961  /* AREF_OTHER connects AO ground to AI ground, i think */
2962  conf |= (CR_AREF(chanspec[i]) ==
2963  AREF_OTHER) ? AO_Ground_Ref : 0;
2964 
2965  ni_writew(conf, AO_Configuration);
2966  devpriv->ao_conf[chan] = conf;
2967  }
2968  return invert;
2969 }
2970 
2971 static int ni_ao_config_chanlist(struct comedi_device *dev,
2972  struct comedi_subdevice *s,
2973  unsigned int chanspec[], unsigned int n_chans,
2974  int timed)
2975 {
2976  if (boardtype.reg_type & ni_reg_m_series_mask)
2977  return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2978  timed);
2979  else
2980  return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2981 }
2982 
2983 static int ni_ao_insn_read(struct comedi_device *dev,
2984  struct comedi_subdevice *s, struct comedi_insn *insn,
2985  unsigned int *data)
2986 {
2987  data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2988 
2989  return 1;
2990 }
2991 
2992 static int ni_ao_insn_write(struct comedi_device *dev,
2993  struct comedi_subdevice *s,
2994  struct comedi_insn *insn, unsigned int *data)
2995 {
2996  unsigned int chan = CR_CHAN(insn->chanspec);
2997  unsigned int invert;
2998 
2999  invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3000 
3001  devpriv->ao[chan] = data[0];
3002 
3003  if (boardtype.reg_type & ni_reg_m_series_mask) {
3004  ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3005  } else
3006  ni_writew(data[0] ^ invert,
3007  (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3008 
3009  return 1;
3010 }
3011 
3012 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3013  struct comedi_subdevice *s,
3014  struct comedi_insn *insn, unsigned int *data)
3015 {
3016  unsigned int chan = CR_CHAN(insn->chanspec);
3017  unsigned int invert;
3018 
3019  ao_win_out(1 << chan, AO_Immediate_671x);
3020  invert = 1 << (boardtype.aobits - 1);
3021 
3022  ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3023 
3024  devpriv->ao[chan] = data[0];
3025  ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3026 
3027  return 1;
3028 }
3029 
3030 static int ni_ao_insn_config(struct comedi_device *dev,
3031  struct comedi_subdevice *s,
3032  struct comedi_insn *insn, unsigned int *data)
3033 {
3034  switch (data[0]) {
3035  case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3036  switch (data[1]) {
3037  case COMEDI_OUTPUT:
3038  data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short);
3039  if (devpriv->mite)
3040  data[2] += devpriv->mite->fifo_size;
3041  break;
3042  case COMEDI_INPUT:
3043  data[2] = 0;
3044  break;
3045  default:
3046  return -EINVAL;
3047  break;
3048  }
3049  return 0;
3050  default:
3051  break;
3052  }
3053 
3054  return -EINVAL;
3055 }
3056 
3057 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3058  unsigned int trignum)
3059 {
3060  int ret;
3061  int interrupt_b_bits;
3062  int i;
3063  static const int timeout = 1000;
3064 
3065  if (trignum != 0)
3066  return -EINVAL;
3067 
3068  /* Null trig at beginning prevent ao start trigger from executing more than
3069  once per command (and doing things like trying to allocate the ao dma channel
3070  multiple times) */
3071  s->async->inttrig = NULL;
3072 
3073  ni_set_bits(dev, Interrupt_B_Enable_Register,
3074  AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3075  interrupt_b_bits = AO_Error_Interrupt_Enable;
3076 #ifdef PCIDMA
3077  devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3078  if (boardtype.reg_type & ni_reg_6xxx_mask)
3079  ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3080  ret = ni_ao_setup_MITE_dma(dev);
3081  if (ret)
3082  return ret;
3083  ret = ni_ao_wait_for_dma_load(dev);
3084  if (ret < 0)
3085  return ret;
3086 #else
3087  ret = ni_ao_prep_fifo(dev, s);
3088  if (ret == 0)
3089  return -EPIPE;
3090 
3091  interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3092 #endif
3093 
3094  devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3095  AO_Mode_3_Register);
3096  devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3097  /* wait for DACs to be loaded */
3098  for (i = 0; i < timeout; i++) {
3099  udelay(1);
3100  if ((devpriv->stc_readw(dev,
3101  Joint_Status_2_Register) &
3102  AO_TMRDACWRs_In_Progress_St) == 0)
3103  break;
3104  }
3105  if (i == timeout) {
3106  comedi_error(dev,
3107  "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3108  return -EIO;
3109  }
3110  /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3111  devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3112  Interrupt_B_Ack_Register);
3113 
3114  ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3115 
3116  devpriv->stc_writew(dev,
3117  devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3118  | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3119  AO_Command_1_Register);
3120 
3121  devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3122  AO_Command_2_Register);
3123 
3124  return 0;
3125 }
3126 
3127 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3128 {
3129  const struct comedi_cmd *cmd = &s->async->cmd;
3130  int bits;
3131  int i;
3132  unsigned trigvar;
3133 
3134  if (dev->irq == 0) {
3135  comedi_error(dev, "cannot run command without an irq");
3136  return -EIO;
3137  }
3138 
3139  devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3140 
3141  devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3142 
3143  if (boardtype.reg_type & ni_reg_6xxx_mask) {
3144  ao_win_out(CLEAR_WG, AO_Misc_611x);
3145 
3146  bits = 0;
3147  for (i = 0; i < cmd->chanlist_len; i++) {
3148  int chan;
3149 
3150  chan = CR_CHAN(cmd->chanlist[i]);
3151  bits |= 1 << chan;
3152  ao_win_out(chan, AO_Waveform_Generation_611x);
3153  }
3154  ao_win_out(bits, AO_Timed_611x);
3155  }
3156 
3157  ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3158 
3159  if (cmd->stop_src == TRIG_NONE) {
3160  devpriv->ao_mode1 |= AO_Continuous;
3161  devpriv->ao_mode1 &= ~AO_Trigger_Once;
3162  } else {
3163  devpriv->ao_mode1 &= ~AO_Continuous;
3164  devpriv->ao_mode1 |= AO_Trigger_Once;
3165  }
3166  devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3167  switch (cmd->start_src) {
3168  case TRIG_INT:
3169  case TRIG_NOW:
3170  devpriv->ao_trigger_select &=
3171  ~(AO_START1_Polarity | AO_START1_Select(-1));
3172  devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3173  devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3174  AO_Trigger_Select_Register);
3175  break;
3176  case TRIG_EXT:
3177  devpriv->ao_trigger_select =
3178  AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3179  if (cmd->start_arg & CR_INVERT)
3180  devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3181  if (cmd->start_arg & CR_EDGE)
3182  devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3183  devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3184  AO_Trigger_Select_Register);
3185  break;
3186  default:
3187  BUG();
3188  break;
3189  }
3190  devpriv->ao_mode3 &= ~AO_Trigger_Length;
3191  devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3192 
3193  devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3194  devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3195  devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3196  if (cmd->stop_src == TRIG_NONE) {
3197  devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3198  } else {
3199  devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3200  }
3201  devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3202  devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3203  devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3204  switch (cmd->stop_src) {
3205  case TRIG_COUNT:
3206  if (boardtype.reg_type & ni_reg_m_series_mask) {
3207  /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3208  devpriv->stc_writel(dev, cmd->stop_arg - 1,
3209  AO_UC_Load_A_Register);
3210  devpriv->stc_writew(dev, AO_UC_Load,
3211  AO_Command_1_Register);
3212  } else {
3213  devpriv->stc_writel(dev, cmd->stop_arg,
3214  AO_UC_Load_A_Register);
3215  devpriv->stc_writew(dev, AO_UC_Load,
3216  AO_Command_1_Register);
3217  devpriv->stc_writel(dev, cmd->stop_arg - 1,
3218  AO_UC_Load_A_Register);
3219  }
3220  break;
3221  case TRIG_NONE:
3222  devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3223  devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3224  devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3225  break;
3226  default:
3227  devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3228  devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3229  devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3230  }
3231 
3232  devpriv->ao_mode1 &=
3233  ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3234  AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3235  switch (cmd->scan_begin_src) {
3236  case TRIG_TIMER:
3237  devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3238  trigvar =
3239  ni_ns_to_timer(dev, cmd->scan_begin_arg,
3240  TRIG_ROUND_NEAREST);
3241  devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3242  devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3243  devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3244  break;
3245  case TRIG_EXT:
3246  devpriv->ao_mode1 |=
3247  AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3248  if (cmd->scan_begin_arg & CR_INVERT)
3249  devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3250  devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3251  break;
3252  default:
3253  BUG();
3254  break;
3255  }
3256  devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3257  devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3258  devpriv->ao_mode2 &=
3259  ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3260  devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3261 
3262  if (cmd->scan_end_arg > 1) {
3263  devpriv->ao_mode1 |= AO_Multiple_Channels;
3264  devpriv->stc_writew(dev,
3265  AO_Number_Of_Channels(cmd->scan_end_arg -
3266  1) |
3267  AO_UPDATE_Output_Select
3268  (AO_Update_Output_High_Z),
3269  AO_Output_Control_Register);
3270  } else {
3271  unsigned bits;
3272  devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3273  bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3274  if (boardtype.
3275  reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3276  bits |= AO_Number_Of_Channels(0);
3277  } else {
3278  bits |=
3279  AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3280  }
3281  devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3282  }
3283  devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3284 
3285  devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3286  AO_Command_1_Register);
3287 
3288  devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3289  devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3290 
3291  devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3292 #ifdef PCIDMA
3293  devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3294 #else
3295  devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3296 #endif
3297  devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3298  devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3299 
3300  bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3301  AO_TMRDACWR_Pulse_Width;
3302  if (boardtype.ao_fifo_depth)
3303  bits |= AO_FIFO_Enable;
3304  else
3305  bits |= AO_DMA_PIO_Control;
3306 #if 0
3307  /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3308  verified with bus analyzer. */
3309  if (boardtype.reg_type & ni_reg_m_series_mask)
3310  bits |= AO_Number_Of_DAC_Packages;
3311 #endif
3312  devpriv->stc_writew(dev, bits, AO_Personal_Register);
3313  /* enable sending of ao dma requests */
3314  devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3315 
3316  devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3317 
3318  if (cmd->stop_src == TRIG_COUNT) {
3319  devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3320  Interrupt_B_Ack_Register);
3321  ni_set_bits(dev, Interrupt_B_Enable_Register,
3322  AO_BC_TC_Interrupt_Enable, 1);
3323  }
3324 
3325  s->async->inttrig = &ni_ao_inttrig;
3326 
3327  return 0;
3328 }
3329 
3330 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3331  struct comedi_cmd *cmd)
3332 {
3333  int err = 0;
3334  int tmp;
3335 
3336  /* Step 1 : check if triggers are trivially valid */
3337 
3338  if ((cmd->flags & CMDF_WRITE) == 0)
3339  cmd->flags |= CMDF_WRITE;
3340 
3341  err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3342  err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3343  TRIG_TIMER | TRIG_EXT);
3344  err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3345  err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3346  err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3347 
3348  if (err)
3349  return 1;
3350 
3351  /* Step 2a : make sure trigger sources are unique */
3352 
3353  err |= cfc_check_trigger_is_unique(cmd->start_src);
3354  err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3355  err |= cfc_check_trigger_is_unique(cmd->stop_src);
3356 
3357  /* Step 2b : and mutually compatible */
3358 
3359  if (err)
3360  return 2;
3361 
3362  /* step 3: make sure arguments are trivially compatible */
3363 
3364  if (cmd->start_src == TRIG_EXT) {
3365  /* external trigger */
3366  unsigned int tmp = CR_CHAN(cmd->start_arg);
3367 
3368  if (tmp > 18)
3369  tmp = 18;
3370  tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3371  if (cmd->start_arg != tmp) {
3372  cmd->start_arg = tmp;
3373  err++;
3374  }
3375  } else {
3376  if (cmd->start_arg != 0) {
3377  /* true for both TRIG_NOW and TRIG_INT */
3378  cmd->start_arg = 0;
3379  err++;
3380  }
3381  }
3382  if (cmd->scan_begin_src == TRIG_TIMER) {
3383  if (cmd->scan_begin_arg < boardtype.ao_speed) {
3384  cmd->scan_begin_arg = boardtype.ao_speed;
3385  err++;
3386  }
3387  if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) { /* XXX check */
3388  cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
3389  err++;
3390  }
3391  }
3392  if (cmd->convert_arg != 0) {
3393  cmd->convert_arg = 0;
3394  err++;
3395  }
3396  if (cmd->scan_end_arg != cmd->chanlist_len) {
3397  cmd->scan_end_arg = cmd->chanlist_len;
3398  err++;
3399  }
3400  if (cmd->stop_src == TRIG_COUNT) { /* XXX check */
3401  if (cmd->stop_arg > 0x00ffffff) {
3402  cmd->stop_arg = 0x00ffffff;
3403  err++;
3404  }
3405  } else {
3406  /* TRIG_NONE */
3407  if (cmd->stop_arg != 0) {
3408  cmd->stop_arg = 0;
3409  err++;
3410  }
3411  }
3412 
3413  if (err)
3414  return 3;
3415 
3416  /* step 4: fix up any arguments */
3417  if (cmd->scan_begin_src == TRIG_TIMER) {
3418  tmp = cmd->scan_begin_arg;
3419  cmd->scan_begin_arg =
3420  ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3421  cmd->scan_begin_arg,
3422  cmd->
3423  flags &
3424  TRIG_ROUND_MASK));
3425  if (tmp != cmd->scan_begin_arg)
3426  err++;
3427  }
3428  if (err)
3429  return 4;
3430 
3431  /* step 5: fix up chanlist */
3432 
3433  if (err)
3434  return 5;
3435 
3436  return 0;
3437 }
3438 
3439 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3440 {
3441  /* devpriv->ao0p=0x0000; */
3442  /* ni_writew(devpriv->ao0p,AO_Configuration); */
3443 
3444  /* devpriv->ao1p=AO_Channel(1); */
3445  /* ni_writew(devpriv->ao1p,AO_Configuration); */
3446 
3447  ni_release_ao_mite_channel(dev);
3448 
3449  devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3450  devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3451  ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3452  devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3453  devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3454  devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3455  AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3456  devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3457  devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3458  devpriv->ao_cmd1 = 0;
3459  devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3460  devpriv->ao_cmd2 = 0;
3461  devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3462  devpriv->ao_mode1 = 0;
3463  devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3464  devpriv->ao_mode2 = 0;
3465  devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3466  if (boardtype.reg_type & ni_reg_m_series_mask)
3467  devpriv->ao_mode3 = AO_Last_Gate_Disable;
3468  else
3469  devpriv->ao_mode3 = 0;
3470  devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3471  devpriv->ao_trigger_select = 0;
3472  devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3473  AO_Trigger_Select_Register);
3474  if (boardtype.reg_type & ni_reg_6xxx_mask) {
3475  unsigned immediate_bits = 0;
3476  unsigned i;
3477  for (i = 0; i < s->n_chan; ++i) {
3478  immediate_bits |= 1 << i;
3479  }
3480  ao_win_out(immediate_bits, AO_Immediate_671x);
3481  ao_win_out(CLEAR_WG, AO_Misc_611x);
3482  }
3483  devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3484 
3485  return 0;
3486 }
3487 
3488 /* digital io */
3489 
3490 static int ni_dio_insn_config(struct comedi_device *dev,
3491  struct comedi_subdevice *s,
3492  struct comedi_insn *insn, unsigned int *data)
3493 {
3494 #ifdef DEBUG_DIO
3495  printk("ni_dio_insn_config() chan=%d io=%d\n",
3496  CR_CHAN(insn->chanspec), data[0]);
3497 #endif
3498  switch (data[0]) {
3499  case INSN_CONFIG_DIO_OUTPUT:
3500  s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3501  break;
3502  case INSN_CONFIG_DIO_INPUT:
3503  s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3504  break;
3505  case INSN_CONFIG_DIO_QUERY:
3506  data[1] =
3507  (s->
3508  io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3509  COMEDI_INPUT;
3510  return insn->n;
3511  break;
3512  default:
3513  return -EINVAL;
3514  }
3515 
3516  devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3517  devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3518  devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3519 
3520  return 1;
3521 }
3522 
3523 static int ni_dio_insn_bits(struct comedi_device *dev,
3524  struct comedi_subdevice *s,
3525  struct comedi_insn *insn, unsigned int *data)
3526 {
3527 #ifdef DEBUG_DIO
3528  printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3529 #endif
3530 
3531  if (data[0]) {
3532  /* Perform check to make sure we're not using the
3533  serial part of the dio */
3534  if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3535  && devpriv->serial_interval_ns)
3536  return -EBUSY;
3537 
3538  s->state &= ~data[0];
3539  s->state |= (data[0] & data[1]);
3540  devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3541  devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3542  devpriv->stc_writew(dev, devpriv->dio_output,
3543  DIO_Output_Register);
3544  }
3545  data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3546 
3547  return insn->n;
3548 }
3549 
3550 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3551  struct comedi_subdevice *s,
3552  struct comedi_insn *insn,
3553  unsigned int *data)
3554 {
3555 #ifdef DEBUG_DIO
3556  printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3557  CR_CHAN(insn->chanspec), data[0]);
3558 #endif
3559  switch (data[0]) {
3560  case INSN_CONFIG_DIO_OUTPUT:
3561  s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3562  break;
3563  case INSN_CONFIG_DIO_INPUT:
3564  s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3565  break;
3566  case INSN_CONFIG_DIO_QUERY:
3567  data[1] =
3568  (s->
3569  io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3570  COMEDI_INPUT;
3571  return insn->n;
3572  break;
3573  default:
3574  return -EINVAL;
3575  }
3576 
3577  ni_writel(s->io_bits, M_Offset_DIO_Direction);
3578 
3579  return 1;
3580 }
3581 
3582 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3583  struct comedi_subdevice *s,
3584  struct comedi_insn *insn,
3585  unsigned int *data)
3586 {
3587 #ifdef DEBUG_DIO
3588  printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3589  data[1]);
3590 #endif
3591 
3592  if (data[0]) {
3593  s->state &= ~data[0];
3594  s->state |= (data[0] & data[1]);
3595  ni_writel(s->state, M_Offset_Static_Digital_Output);
3596  }
3597  data[1] = ni_readl(M_Offset_Static_Digital_Input);
3598 
3599  return insn->n;
3600 }
3601 
3602 static int ni_cdio_cmdtest(struct comedi_device *dev,
3603  struct comedi_subdevice *s, struct comedi_cmd *cmd)
3604 {
3605  int err = 0;
3606  int tmp;
3607  unsigned i;
3608 
3609  /* Step 1 : check if triggers are trivially valid */
3610 
3611  err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3612  err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3613  err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3614  err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3615  err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3616 
3617  if (err)
3618  return 1;
3619 
3620  /* Step 2a : make sure trigger sources are unique */
3621  /* Step 2b : and mutually compatible */
3622 
3623  if (err)
3624  return 2;
3625 
3626  /* step 3: make sure arguments are trivially compatible */
3627  if (cmd->start_src == TRIG_INT) {
3628  if (cmd->start_arg != 0) {
3629  cmd->start_arg = 0;
3630  err++;
3631  }
3632  }
3633  if (cmd->scan_begin_src == TRIG_EXT) {
3634  tmp = cmd->scan_begin_arg;
3635  tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0,
3636  CR_INVERT);
3637  if (tmp != cmd->scan_begin_arg) {
3638  err++;
3639  }
3640  }
3641  if (cmd->convert_src == TRIG_NOW) {
3642  if (cmd->convert_arg) {
3643  cmd->convert_arg = 0;
3644  err++;
3645  }
3646  }
3647 
3648  if (cmd->scan_end_arg != cmd->chanlist_len) {
3649  cmd->scan_end_arg = cmd->chanlist_len;
3650  err++;
3651  }
3652 
3653  if (cmd->stop_src == TRIG_NONE) {
3654  if (cmd->stop_arg != 0) {
3655  cmd->stop_arg = 0;
3656  err++;
3657  }
3658  }
3659 
3660  if (err)
3661  return 3;
3662 
3663  /* step 4: fix up any arguments */
3664 
3665  if (err)
3666  return 4;
3667 
3668  /* step 5: check chanlist */
3669 
3670  for (i = 0; i < cmd->chanlist_len; ++i) {
3671  if (cmd->chanlist[i] != i)
3672  err = 1;
3673  }
3674 
3675  if (err)
3676  return 5;
3677 
3678  return 0;
3679 }
3680 
3681 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3682 {
3683  const struct comedi_cmd *cmd = &s->async->cmd;
3684  unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3685  int retval;
3686 
3687  ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3688  switch (cmd->scan_begin_src) {
3689  case TRIG_EXT:
3690  cdo_mode_bits |=
3691  CR_CHAN(cmd->scan_begin_arg) &
3692  CDO_Sample_Source_Select_Mask;
3693  break;
3694  default:
3695  BUG();
3696  break;
3697  }
3698  if (cmd->scan_begin_arg & CR_INVERT)
3699  cdo_mode_bits |= CDO_Polarity_Bit;
3700  ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3701  if (s->io_bits) {
3702  ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3703  ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3704  ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3705  } else {
3706  comedi_error(dev,
3707  "attempted to run digital output command with no lines configured as outputs");
3708  return -EIO;
3709  }
3710  retval = ni_request_cdo_mite_channel(dev);
3711  if (retval < 0) {
3712  return retval;
3713  }
3714  s->async->inttrig = &ni_cdo_inttrig;
3715  return 0;
3716 }
3717 
3718 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3719  unsigned int trignum)
3720 {
3721 #ifdef PCIDMA
3722  unsigned long flags;
3723 #endif
3724  int retval = 0;
3725  unsigned i;
3726  const unsigned timeout = 1000;
3727 
3728  s->async->inttrig = NULL;
3729 
3730  /* read alloc the entire buffer */
3731  comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3732 
3733 #ifdef PCIDMA
3734  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3735  if (devpriv->cdo_mite_chan) {
3736  mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3737  mite_dma_arm(devpriv->cdo_mite_chan);
3738  } else {
3739  comedi_error(dev, "BUG: no cdo mite channel?");
3740  retval = -EIO;
3741  }
3742  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3743  if (retval < 0)
3744  return retval;
3745 #endif
3746 /*
3747 * XXX not sure what interrupt C group does
3748 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3749 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3750 */
3751  for (i = 0; i < timeout; ++i) {
3752  if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3753  break;
3754  udelay(10);
3755  }
3756  if (i == timeout) {
3757  comedi_error(dev, "dma failed to fill cdo fifo!");
3758  ni_cdio_cancel(dev, s);
3759  return -EIO;
3760  }
3761  ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3762  CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3763  M_Offset_CDIO_Command);
3764  return retval;
3765 }
3766 
3767 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3768 {
3769  ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3770  CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3771  CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3772  M_Offset_CDIO_Command);
3773 /*
3774 * XXX not sure what interrupt C group does ni_writeb(0,
3775 * M_Offset_Interrupt_C_Enable);
3776 */
3777  ni_writel(0, M_Offset_CDO_Mask_Enable);
3778  ni_release_cdo_mite_channel(dev);
3779  return 0;
3780 }
3781 
3782 static void handle_cdio_interrupt(struct comedi_device *dev)
3783 {
3784  unsigned cdio_status;
3785  struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3786 #ifdef PCIDMA
3787  unsigned long flags;
3788 #endif
3789 
3790  if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3791  return;
3792  }
3793 #ifdef PCIDMA
3794  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3795  if (devpriv->cdo_mite_chan) {
3796  unsigned cdo_mite_status =
3797  mite_get_status(devpriv->cdo_mite_chan);
3798  if (cdo_mite_status & CHSR_LINKC) {
3799  writel(CHOR_CLRLC,
3800  devpriv->mite->mite_io_addr +
3801  MITE_CHOR(devpriv->cdo_mite_chan->channel));
3802  }
3803  mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3804  }
3805  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3806 #endif
3807 
3808  cdio_status = ni_readl(M_Offset_CDIO_Status);
3809  if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3810 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3811  ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3812  s->async->events |= COMEDI_CB_OVERFLOW;
3813  }
3814  if (cdio_status & CDO_FIFO_Empty_Bit) {
3815 /* printk("cdio fifo empty\n"); */
3816  ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3817  M_Offset_CDIO_Command);
3818 /* s->async->events |= COMEDI_CB_EOA; */
3819  }
3820  ni_event(dev, s);
3821 }
3822 
3823 static int ni_serial_insn_config(struct comedi_device *dev,
3824  struct comedi_subdevice *s,
3825  struct comedi_insn *insn, unsigned int *data)
3826 {
3827  int err = insn->n;
3828  unsigned char byte_out, byte_in = 0;
3829 
3830  if (insn->n != 2)
3831  return -EINVAL;
3832 
3833  switch (data[0]) {
3834  case INSN_CONFIG_SERIAL_CLOCK:
3835 
3836 #ifdef DEBUG_DIO
3837  printk("SPI serial clock Config cd\n", data[1]);
3838 #endif
3839  devpriv->serial_hw_mode = 1;
3840  devpriv->dio_control |= DIO_HW_Serial_Enable;
3841 
3842  if (data[1] == SERIAL_DISABLED) {
3843  devpriv->serial_hw_mode = 0;
3844  devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3845  DIO_Software_Serial_Control);
3846  data[1] = SERIAL_DISABLED;
3847  devpriv->serial_interval_ns = data[1];
3848  } else if (data[1] <= SERIAL_600NS) {
3849  /* Warning: this clock speed is too fast to reliably
3850  control SCXI. */
3851  devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3852  devpriv->clock_and_fout |= Slow_Internal_Timebase;
3853  devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3854  data[1] = SERIAL_600NS;
3855  devpriv->serial_interval_ns = data[1];
3856  } else if (data[1] <= SERIAL_1_2US) {
3857  devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3858  devpriv->clock_and_fout |= Slow_Internal_Timebase |
3859  DIO_Serial_Out_Divide_By_2;
3860  data[1] = SERIAL_1_2US;
3861  devpriv->serial_interval_ns = data[1];
3862  } else if (data[1] <= SERIAL_10US) {
3863  devpriv->dio_control |= DIO_HW_Serial_Timebase;
3864  devpriv->clock_and_fout |= Slow_Internal_Timebase |
3865  DIO_Serial_Out_Divide_By_2;
3866  /* Note: DIO_Serial_Out_Divide_By_2 only affects
3867  600ns/1.2us. If you turn divide_by_2 off with the
3868  slow clock, you will still get 10us, except then
3869  all your delays are wrong. */
3870  data[1] = SERIAL_10US;
3871  devpriv->serial_interval_ns = data[1];
3872  } else {
3873  devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3874  DIO_Software_Serial_Control);
3875  devpriv->serial_hw_mode = 0;
3876  data[1] = (data[1] / 1000) * 1000;
3877  devpriv->serial_interval_ns = data[1];
3878  }
3879 
3880  devpriv->stc_writew(dev, devpriv->dio_control,
3881  DIO_Control_Register);
3882  devpriv->stc_writew(dev, devpriv->clock_and_fout,
3883  Clock_and_FOUT_Register);
3884  return 1;
3885 
3886  break;
3887 
3888  case INSN_CONFIG_BIDIRECTIONAL_DATA:
3889 
3890  if (devpriv->serial_interval_ns == 0) {
3891  return -EINVAL;
3892  }
3893 
3894  byte_out = data[1] & 0xFF;
3895 
3896  if (devpriv->serial_hw_mode) {
3897  err = ni_serial_hw_readwrite8(dev, s, byte_out,
3898  &byte_in);
3899  } else if (devpriv->serial_interval_ns > 0) {
3900  err = ni_serial_sw_readwrite8(dev, s, byte_out,
3901  &byte_in);
3902  } else {
3903  printk("ni_serial_insn_config: serial disabled!\n");
3904  return -EINVAL;
3905  }
3906  if (err < 0)
3907  return err;
3908  data[1] = byte_in & 0xFF;
3909  return insn->n;
3910 
3911  break;
3912  default:
3913  return -EINVAL;
3914  }
3915 
3916 }
3917 
3918 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3919  struct comedi_subdevice *s,
3920  unsigned char data_out,
3921  unsigned char *data_in)
3922 {
3923  unsigned int status1;
3924  int err = 0, count = 20;
3925 
3926 #ifdef DEBUG_DIO
3927  printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3928 #endif
3929 
3930  devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3931  devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3932  devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3933 
3934  status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3935  if (status1 & DIO_Serial_IO_In_Progress_St) {
3936  err = -EBUSY;
3937  goto Error;
3938  }
3939 
3940  devpriv->dio_control |= DIO_HW_Serial_Start;
3941  devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3942  devpriv->dio_control &= ~DIO_HW_Serial_Start;
3943 
3944  /* Wait until STC says we're done, but don't loop infinitely. */
3945  while ((status1 =
3946  devpriv->stc_readw(dev,
3947  Joint_Status_1_Register)) &
3948  DIO_Serial_IO_In_Progress_St) {
3949  /* Delay one bit per loop */
3950  udelay((devpriv->serial_interval_ns + 999) / 1000);
3951  if (--count < 0) {
3952  printk
3953  ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3954  err = -ETIME;
3955  goto Error;
3956  }
3957  }
3958 
3959  /* Delay for last bit. This delay is absolutely necessary, because
3960  DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3961  udelay((devpriv->serial_interval_ns + 999) / 1000);
3962 
3963  if (data_in != NULL) {
3964  *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3965 #ifdef DEBUG_DIO
3966  printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3967 #endif
3968  }
3969 
3970 Error:
3971  devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3972 
3973  return err;
3974 }
3975 
3976 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3977  struct comedi_subdevice *s,
3978  unsigned char data_out,
3979  unsigned char *data_in)
3980 {
3981  unsigned char mask, input = 0;
3982 
3983 #ifdef DEBUG_DIO
3984  printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3985 #endif
3986 
3987  /* Wait for one bit before transfer */
3988  udelay((devpriv->serial_interval_ns + 999) / 1000);
3989 
3990  for (mask = 0x80; mask; mask >>= 1) {
3991  /* Output current bit; note that we cannot touch s->state
3992  because it is a per-subdevice field, and serial is
3993  a separate subdevice from DIO. */
3994  devpriv->dio_output &= ~DIO_SDOUT;
3995  if (data_out & mask) {
3996  devpriv->dio_output |= DIO_SDOUT;
3997  }
3998  devpriv->stc_writew(dev, devpriv->dio_output,
3999  DIO_Output_Register);
4000 
4001  /* Assert SDCLK (active low, inverted), wait for half of
4002  the delay, deassert SDCLK, and wait for the other half. */
4003  devpriv->dio_control |= DIO_Software_Serial_Control;
4004  devpriv->stc_writew(dev, devpriv->dio_control,
4005  DIO_Control_Register);
4006 
4007  udelay((devpriv->serial_interval_ns + 999) / 2000);
4008 
4009  devpriv->dio_control &= ~DIO_Software_Serial_Control;
4010  devpriv->stc_writew(dev, devpriv->dio_control,
4011  DIO_Control_Register);
4012 
4013  udelay((devpriv->serial_interval_ns + 999) / 2000);
4014 
4015  /* Input current bit */
4016  if (devpriv->stc_readw(dev,
4017  DIO_Parallel_Input_Register) & DIO_SDIN)
4018  {
4019 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4020  input |= mask;
4021  }
4022  }
4023 #ifdef DEBUG_DIO
4024  printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4025 #endif
4026  if (data_in)
4027  *data_in = input;
4028 
4029  return 0;
4030 }
4031 
4032 static void mio_common_detach(struct comedi_device *dev)
4033 {
4034  struct comedi_subdevice *s;
4035 
4036  if (dev->private) {
4037  if (devpriv->counter_dev) {
4038  ni_gpct_device_destroy(devpriv->counter_dev);
4039  }
4040  }
4041  if (dev->subdevices && boardtype.has_8255) {
4042  s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4043  subdev_8255_cleanup(dev, s);
4044  }
4045 }
4046 
4047 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4048 {
4049  int i;
4050 
4051  for (i = 0; i < s->n_chan; i++) {
4052  ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4053  AO_Configuration_2_67xx);
4054  }
4055  ao_win_out(0x0, AO_Later_Single_Point_Updates);
4056 }
4057 
4058 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4059 {
4060  unsigned stc_register;
4061  switch (reg) {
4062  case NITIO_G0_Autoincrement_Reg:
4063  stc_register = G_Autoincrement_Register(0);
4064  break;
4065  case NITIO_G1_Autoincrement_Reg:
4066  stc_register = G_Autoincrement_Register(1);
4067  break;
4068  case NITIO_G0_Command_Reg:
4069  stc_register = G_Command_Register(0);
4070  break;
4071  case NITIO_G1_Command_Reg:
4072  stc_register = G_Command_Register(1);
4073  break;
4074  case NITIO_G0_HW_Save_Reg:
4075  stc_register = G_HW_Save_Register(0);
4076  break;
4077  case NITIO_G1_HW_Save_Reg:
4078  stc_register = G_HW_Save_Register(1);
4079  break;
4080  case NITIO_G0_SW_Save_Reg:
4081  stc_register = G_Save_Register(0);
4082  break;
4083  case NITIO_G1_SW_Save_Reg:
4084  stc_register = G_Save_Register(1);
4085  break;
4086  case NITIO_G0_Mode_Reg:
4087  stc_register = G_Mode_Register(0);
4088  break;
4089  case NITIO_G1_Mode_Reg:
4090  stc_register = G_Mode_Register(1);
4091  break;
4092  case NITIO_G0_LoadA_Reg:
4093  stc_register = G_Load_A_Register(0);
4094  break;
4095  case NITIO_G1_LoadA_Reg:
4096  stc_register = G_Load_A_Register(1);
4097  break;
4098  case NITIO_G0_LoadB_Reg:
4099  stc_register = G_Load_B_Register(0);
4100  break;
4101  case NITIO_G1_LoadB_Reg:
4102  stc_register = G_Load_B_Register(1);
4103  break;
4104  case NITIO_G0_Input_Select_Reg:
4105  stc_register = G_Input_Select_Register(0);
4106  break;
4107  case NITIO_G1_Input_Select_Reg:
4108  stc_register = G_Input_Select_Register(1);
4109  break;
4110  case NITIO_G01_Status_Reg:
4111  stc_register = G_Status_Register;
4112  break;
4113  case NITIO_G01_Joint_Reset_Reg:
4114  stc_register = Joint_Reset_Register;
4115  break;
4116  case NITIO_G01_Joint_Status1_Reg:
4117  stc_register = Joint_Status_1_Register;
4118  break;
4119  case NITIO_G01_Joint_Status2_Reg:
4120  stc_register = Joint_Status_2_Register;
4121  break;
4122  case NITIO_G0_Interrupt_Acknowledge_Reg:
4123  stc_register = Interrupt_A_Ack_Register;
4124  break;
4125  case NITIO_G1_Interrupt_Acknowledge_Reg:
4126  stc_register = Interrupt_B_Ack_Register;
4127  break;
4128  case NITIO_G0_Status_Reg:
4129  stc_register = AI_Status_1_Register;
4130  break;
4131  case NITIO_G1_Status_Reg:
4132  stc_register = AO_Status_1_Register;
4133  break;
4134  case NITIO_G0_Interrupt_Enable_Reg:
4135  stc_register = Interrupt_A_Enable_Register;
4136  break;
4137  case NITIO_G1_Interrupt_Enable_Reg:
4138  stc_register = Interrupt_B_Enable_Register;
4139  break;
4140  default:
4141  printk("%s: unhandled register 0x%x in switch.\n",
4142  __func__, reg);
4143  BUG();
4144  return 0;
4145  break;
4146  }
4147  return stc_register;
4148 }
4149 
4150 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4151  enum ni_gpct_register reg)
4152 {
4153  struct comedi_device *dev = counter->counter_dev->dev;
4154  unsigned stc_register;
4155  /* bits in the join reset register which are relevant to counters */
4156  static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4157  static const unsigned gpct_interrupt_a_enable_mask =
4158  G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4159  static const unsigned gpct_interrupt_b_enable_mask =
4160  G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4161 
4162  switch (reg) {
4163  /* m-series-only registers */
4164  case NITIO_G0_Counting_Mode_Reg:
4165  ni_writew(bits, M_Offset_G0_Counting_Mode);
4166  break;
4167  case NITIO_G1_Counting_Mode_Reg:
4168  ni_writew(bits, M_Offset_G1_Counting_Mode);
4169  break;
4170  case NITIO_G0_Second_Gate_Reg:
4171  ni_writew(bits, M_Offset_G0_Second_Gate);
4172  break;
4173  case NITIO_G1_Second_Gate_Reg:
4174  ni_writew(bits, M_Offset_G1_Second_Gate);
4175  break;
4176  case NITIO_G0_DMA_Config_Reg:
4177  ni_writew(bits, M_Offset_G0_DMA_Config);
4178  break;
4179  case NITIO_G1_DMA_Config_Reg:
4180  ni_writew(bits, M_Offset_G1_DMA_Config);
4181  break;
4182  case NITIO_G0_ABZ_Reg:
4183  ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4184  break;
4185  case NITIO_G1_ABZ_Reg:
4186  ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4187  break;
4188 
4189  /* 32 bit registers */
4190  case NITIO_G0_LoadA_Reg:
4191  case NITIO_G1_LoadA_Reg:
4192  case NITIO_G0_LoadB_Reg:
4193  case NITIO_G1_LoadB_Reg:
4194  stc_register = ni_gpct_to_stc_register(reg);
4195  devpriv->stc_writel(dev, bits, stc_register);
4196  break;
4197 
4198  /* 16 bit registers */
4199  case NITIO_G0_Interrupt_Enable_Reg:
4200  BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4201  ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4202  gpct_interrupt_a_enable_mask, bits);
4203  break;
4204  case NITIO_G1_Interrupt_Enable_Reg:
4205  BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4206  ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4207  gpct_interrupt_b_enable_mask, bits);
4208  break;
4209  case NITIO_G01_Joint_Reset_Reg:
4210  BUG_ON(bits & ~gpct_joint_reset_mask);
4211  /* fall-through */
4212  default:
4213  stc_register = ni_gpct_to_stc_register(reg);
4214  devpriv->stc_writew(dev, bits, stc_register);
4215  }
4216 }
4217 
4218 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4219  enum ni_gpct_register reg)
4220 {
4221  struct comedi_device *dev = counter->counter_dev->dev;
4222  unsigned stc_register;
4223  switch (reg) {
4224  /* m-series only registers */
4225  case NITIO_G0_DMA_Status_Reg:
4226  return ni_readw(M_Offset_G0_DMA_Status);
4227  break;
4228  case NITIO_G1_DMA_Status_Reg:
4229  return ni_readw(M_Offset_G1_DMA_Status);
4230  break;
4231 
4232  /* 32 bit registers */
4233  case NITIO_G0_HW_Save_Reg:
4234  case NITIO_G1_HW_Save_Reg:
4235  case NITIO_G0_SW_Save_Reg:
4236  case NITIO_G1_SW_Save_Reg:
4237  stc_register = ni_gpct_to_stc_register(reg);
4238  return devpriv->stc_readl(dev, stc_register);
4239  break;
4240 
4241  /* 16 bit registers */
4242  default:
4243  stc_register = ni_gpct_to_stc_register(reg);
4244  return devpriv->stc_readw(dev, stc_register);
4245  break;
4246  }
4247  return 0;
4248 }
4249 
4250 static int ni_freq_out_insn_read(struct comedi_device *dev,
4251  struct comedi_subdevice *s,
4252  struct comedi_insn *insn, unsigned int *data)
4253 {
4254  data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4255  return 1;
4256 }
4257 
4258 static int ni_freq_out_insn_write(struct comedi_device *dev,
4259  struct comedi_subdevice *s,
4260  struct comedi_insn *insn, unsigned int *data)
4261 {
4262  devpriv->clock_and_fout &= ~FOUT_Enable;
4263  devpriv->stc_writew(dev, devpriv->clock_and_fout,
4264  Clock_and_FOUT_Register);
4265  devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4266  devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4267  devpriv->clock_and_fout |= FOUT_Enable;
4268  devpriv->stc_writew(dev, devpriv->clock_and_fout,
4269  Clock_and_FOUT_Register);
4270  return insn->n;
4271 }
4272 
4273 static int ni_set_freq_out_clock(struct comedi_device *dev,
4274  unsigned int clock_source)
4275 {
4276  switch (clock_source) {
4277  case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4278  devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4279  break;
4280  case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4281  devpriv->clock_and_fout |= FOUT_Timebase_Select;
4282  break;
4283  default:
4284  return -EINVAL;
4285  }
4286  devpriv->stc_writew(dev, devpriv->clock_and_fout,
4287  Clock_and_FOUT_Register);
4288  return 3;
4289 }
4290 
4291 static void ni_get_freq_out_clock(struct comedi_device *dev,
4292  unsigned int *clock_source,
4293  unsigned int *clock_period_ns)
4294 {
4295  if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4296  *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4297  *clock_period_ns = TIMEBASE_2_NS;
4298  } else {
4299  *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4300  *clock_period_ns = TIMEBASE_1_NS * 2;
4301  }
4302 }
4303 
4304 static int ni_freq_out_insn_config(struct comedi_device *dev,
4305  struct comedi_subdevice *s,
4306  struct comedi_insn *insn, unsigned int *data)
4307 {
4308  switch (data[0]) {
4309  case INSN_CONFIG_SET_CLOCK_SRC:
4310  return ni_set_freq_out_clock(dev, data[1]);
4311  break;
4312  case INSN_CONFIG_GET_CLOCK_SRC:
4313  ni_get_freq_out_clock(dev, &data[1], &data[2]);
4314  return 3;
4315  default:
4316  break;
4317  }
4318  return -EINVAL;
4319 }
4320 
4321 static int ni_alloc_private(struct comedi_device *dev)
4322 {
4323  int ret;
4324 
4325  ret = alloc_private(dev, sizeof(struct ni_private));
4326  if (ret < 0)
4327  return ret;
4328 
4329  spin_lock_init(&devpriv->window_lock);
4330  spin_lock_init(&devpriv->soft_reg_copy_lock);
4331  spin_lock_init(&devpriv->mite_channel_lock);
4332 
4333  return 0;
4334 };
4335 
4336 static int ni_E_init(struct comedi_device *dev)
4337 {
4338  struct comedi_subdevice *s;
4339  unsigned j;
4340  enum ni_gpct_variant counter_variant;
4341  int ret;
4342 
4343  if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4344  printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4345  return -EINVAL;
4346  }
4347 
4348  ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4349  if (ret)
4350  return ret;
4351 
4352  /* analog input subdevice */
4353 
4354  s = &dev->subdevices[NI_AI_SUBDEV];
4355  dev->read_subdev = s;
4356  if (boardtype.n_adchan) {
4357  s->type = COMEDI_SUBD_AI;
4358  s->subdev_flags =
4359  SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4360  if (boardtype.reg_type != ni_reg_611x)
4361  s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4362  if (boardtype.adbits > 16)
4363  s->subdev_flags |= SDF_LSAMPL;
4364  if (boardtype.reg_type & ni_reg_m_series_mask)
4365  s->subdev_flags |= SDF_SOFT_CALIBRATED;
4366  s->n_chan = boardtype.n_adchan;
4367  s->len_chanlist = 512;
4368  s->maxdata = (1 << boardtype.adbits) - 1;
4369  s->range_table = ni_range_lkup[boardtype.gainlkup];
4370  s->insn_read = &ni_ai_insn_read;
4371  s->insn_config = &ni_ai_insn_config;
4372  s->do_cmdtest = &ni_ai_cmdtest;
4373  s->do_cmd = &ni_ai_cmd;
4374  s->cancel = &ni_ai_reset;
4375  s->poll = &ni_ai_poll;
4376  s->munge = &ni_ai_munge;
4377 #ifdef PCIDMA
4378  s->async_dma_dir = DMA_FROM_DEVICE;
4379 #endif
4380  } else {
4381  s->type = COMEDI_SUBD_UNUSED;
4382  }
4383 
4384  /* analog output subdevice */
4385 
4386  s = &dev->subdevices[NI_AO_SUBDEV];
4387  if (boardtype.n_aochan) {
4388  s->type = COMEDI_SUBD_AO;
4389  s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4390  if (boardtype.reg_type & ni_reg_m_series_mask)
4391  s->subdev_flags |= SDF_SOFT_CALIBRATED;
4392  s->n_chan = boardtype.n_aochan;
4393  s->maxdata = (1 << boardtype.aobits) - 1;
4394  s->range_table = boardtype.ao_range_table;
4395  s->insn_read = &ni_ao_insn_read;
4396  if (boardtype.reg_type & ni_reg_6xxx_mask) {
4397  s->insn_write = &ni_ao_insn_write_671x;
4398  } else {
4399  s->insn_write = &ni_ao_insn_write;
4400  }
4401  s->insn_config = &ni_ao_insn_config;
4402 #ifdef PCIDMA
4403  if (boardtype.n_aochan) {
4404  s->async_dma_dir = DMA_TO_DEVICE;
4405 #else
4406  if (boardtype.ao_fifo_depth) {
4407 #endif
4408  dev->write_subdev = s;
4409  s->subdev_flags |= SDF_CMD_WRITE;
4410  s->do_cmd = &ni_ao_cmd;
4411  s->do_cmdtest = &ni_ao_cmdtest;
4412  s->len_chanlist = boardtype.n_aochan;
4413  if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4414  s->munge = ni_ao_munge;
4415  }
4416  s->cancel = &ni_ao_reset;
4417  } else {
4418  s->type = COMEDI_SUBD_UNUSED;
4419  }
4420  if ((boardtype.reg_type & ni_reg_67xx_mask))
4421  init_ao_67xx(dev, s);
4422 
4423  /* digital i/o subdevice */
4424 
4425  s = &dev->subdevices[NI_DIO_SUBDEV];
4426  s->type = COMEDI_SUBD_DIO;
4427  s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4428  s->maxdata = 1;
4429  s->io_bits = 0; /* all bits input */
4430  s->range_table = &range_digital;
4431  s->n_chan = boardtype.num_p0_dio_channels;
4432  if (boardtype.reg_type & ni_reg_m_series_mask) {
4433  s->subdev_flags |=
4434  SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4435  s->insn_bits = &ni_m_series_dio_insn_bits;
4436  s->insn_config = &ni_m_series_dio_insn_config;
4437  s->do_cmd = &ni_cdio_cmd;
4438  s->do_cmdtest = &ni_cdio_cmdtest;
4439  s->cancel = &ni_cdio_cancel;
4440  s->async_dma_dir = DMA_BIDIRECTIONAL;
4441  s->len_chanlist = s->n_chan;
4442 
4443  ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4444  ni_writel(s->io_bits, M_Offset_DIO_Direction);
4445  } else {
4446  s->insn_bits = &ni_dio_insn_bits;
4447  s->insn_config = &ni_dio_insn_config;
4448  devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4449  ni_writew(devpriv->dio_control, DIO_Control_Register);
4450  }
4451 
4452  /* 8255 device */
4453  s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4454  if (boardtype.has_8255) {
4455  subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4456  } else {
4457  s->type = COMEDI_SUBD_UNUSED;
4458  }
4459 
4460  /* formerly general purpose counter/timer device, but no longer used */
4461  s = &dev->subdevices[NI_UNUSED_SUBDEV];
4462  s->type = COMEDI_SUBD_UNUSED;
4463 
4464  /* calibration subdevice -- ai and ao */
4465  s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4466  s->type = COMEDI_SUBD_CALIB;
4467  if (boardtype.reg_type & ni_reg_m_series_mask) {
4468  /* internal PWM analog output used for AI nonlinearity calibration */
4469  s->subdev_flags = SDF_INTERNAL;
4470  s->insn_config = &ni_m_series_pwm_config;
4471  s->n_chan = 1;
4472  s->maxdata = 0;
4473  ni_writel(0x0, M_Offset_Cal_PWM);
4474  } else if (boardtype.reg_type == ni_reg_6143) {
4475  /* internal PWM analog output used for AI nonlinearity calibration */
4476  s->subdev_flags = SDF_INTERNAL;
4477  s->insn_config = &ni_6143_pwm_config;
4478  s->n_chan = 1;
4479  s->maxdata = 0;
4480  } else {
4481  s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4482  s->insn_read = &ni_calib_insn_read;
4483  s->insn_write = &ni_calib_insn_write;
4484  caldac_setup(dev, s);
4485  }
4486 
4487  /* EEPROM */
4488  s = &dev->subdevices[NI_EEPROM_SUBDEV];
4489  s->type = COMEDI_SUBD_MEMORY;
4490  s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4491  s->maxdata = 0xff;
4492  if (boardtype.reg_type & ni_reg_m_series_mask) {
4493  s->n_chan = M_SERIES_EEPROM_SIZE;
4494  s->insn_read = &ni_m_series_eeprom_insn_read;
4495  } else {
4496  s->n_chan = 512;
4497  s->insn_read = &ni_eeprom_insn_read;
4498  }
4499 
4500  /* PFI */
4501  s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4502  s->type = COMEDI_SUBD_DIO;
4503  s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4504  if (boardtype.reg_type & ni_reg_m_series_mask) {
4505  unsigned i;
4506  s->n_chan = 16;
4507  ni_writew(s->state, M_Offset_PFI_DO);
4508  for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4509  ni_writew(devpriv->pfi_output_select_reg[i],
4510  M_Offset_PFI_Output_Select(i + 1));
4511  }
4512  } else {
4513  s->n_chan = 10;
4514  }
4515  s->maxdata = 1;
4516  if (boardtype.reg_type & ni_reg_m_series_mask) {
4517  s->insn_bits = &ni_pfi_insn_bits;
4518  }
4519  s->insn_config = &ni_pfi_insn_config;
4520  ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4521 
4522  /* cs5529 calibration adc */
4523  s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4524  if (boardtype.reg_type & ni_reg_67xx_mask) {
4525  s->type = COMEDI_SUBD_AI;
4526  s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4527  /* one channel for each analog output channel */
4528  s->n_chan = boardtype.n_aochan;
4529  s->maxdata = (1 << 16) - 1;
4530  s->range_table = &range_unknown; /* XXX */
4531  s->insn_read = cs5529_ai_insn_read;
4532  s->insn_config = NULL;
4533  init_cs5529(dev);
4534  } else {
4535  s->type = COMEDI_SUBD_UNUSED;
4536  }
4537 
4538  /* Serial */
4539  s = &dev->subdevices[NI_SERIAL_SUBDEV];
4540  s->type = COMEDI_SUBD_SERIAL;
4541  s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4542  s->n_chan = 1;
4543  s->maxdata = 0xff;
4544  s->insn_config = ni_serial_insn_config;
4545  devpriv->serial_interval_ns = 0;
4546  devpriv->serial_hw_mode = 0;
4547 
4548  /* RTSI */
4549  s = &dev->subdevices[NI_RTSI_SUBDEV];
4550  s->type = COMEDI_SUBD_DIO;
4551  s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4552  s->n_chan = 8;
4553  s->maxdata = 1;
4554  s->insn_bits = ni_rtsi_insn_bits;
4555  s->insn_config = ni_rtsi_insn_config;
4556  ni_rtsi_init(dev);
4557 
4558  if (boardtype.reg_type & ni_reg_m_series_mask) {
4559  counter_variant = ni_gpct_variant_m_series;
4560  } else {
4561  counter_variant = ni_gpct_variant_e_series;
4562  }
4563  devpriv->counter_dev = ni_gpct_device_construct(dev,
4564  &ni_gpct_write_register,
4565  &ni_gpct_read_register,
4566  counter_variant,
4567  NUM_GPCT);
4568  /* General purpose counters */
4569  for (j = 0; j < NUM_GPCT; ++j) {
4570  s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4571  s->type = COMEDI_SUBD_COUNTER;
4572  s->subdev_flags =
4573  SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4574  /* | SDF_CMD_WRITE */ ;
4575  s->n_chan = 3;
4576  if (boardtype.reg_type & ni_reg_m_series_mask)
4577  s->maxdata = 0xffffffff;
4578  else
4579  s->maxdata = 0xffffff;
4580  s->insn_read = &ni_gpct_insn_read;
4581  s->insn_write = &ni_gpct_insn_write;
4582  s->insn_config = &ni_gpct_insn_config;
4583  s->do_cmd = &ni_gpct_cmd;
4584  s->len_chanlist = 1;
4585  s->do_cmdtest = &ni_gpct_cmdtest;
4586  s->cancel = &ni_gpct_cancel;
4587  s->async_dma_dir = DMA_BIDIRECTIONAL;
4588  s->private = &devpriv->counter_dev->counters[j];
4589 
4590  devpriv->counter_dev->counters[j].chip_index = 0;
4591  devpriv->counter_dev->counters[j].counter_index = j;
4592  ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4593  }
4594 
4595  /* Frequency output */
4596  s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4597  s->type = COMEDI_SUBD_COUNTER;
4598  s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4599  s->n_chan = 1;
4600  s->maxdata = 0xf;
4601  s->insn_read = &ni_freq_out_insn_read;
4602  s->insn_write = &ni_freq_out_insn_write;
4603  s->insn_config = &ni_freq_out_insn_config;
4604 
4605  /* ai configuration */
4606  s = &dev->subdevices[NI_AI_SUBDEV];
4607  ni_ai_reset(dev, s);
4608  if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4609  /* BEAM is this needed for PCI-6143 ?? */
4610  devpriv->clock_and_fout =
4611  Slow_Internal_Time_Divide_By_2 |
4612  Slow_Internal_Timebase |
4613  Clock_To_Board_Divide_By_2 |
4614  Clock_To_Board |
4615  AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4616  } else {
4617  devpriv->clock_and_fout =
4618  Slow_Internal_Time_Divide_By_2 |
4619  Slow_Internal_Timebase |
4620  Clock_To_Board_Divide_By_2 | Clock_To_Board;
4621  }
4622  devpriv->stc_writew(dev, devpriv->clock_and_fout,
4623  Clock_and_FOUT_Register);
4624 
4625  /* analog output configuration */
4626  s = &dev->subdevices[NI_AO_SUBDEV];
4627  ni_ao_reset(dev, s);
4628 
4629  if (dev->irq) {
4630  devpriv->stc_writew(dev,
4631  (IRQ_POLARITY ? Interrupt_Output_Polarity :
4632  0) | (Interrupt_Output_On_3_Pins & 0) |
4633  Interrupt_A_Enable | Interrupt_B_Enable |
4634  Interrupt_A_Output_Select(interrupt_pin
4635  (dev->irq)) |
4636  Interrupt_B_Output_Select(interrupt_pin
4637  (dev->irq)),
4638  Interrupt_Control_Register);
4639  }
4640 
4641  /* DMA setup */
4642  ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4643  ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4644 
4645  if (boardtype.reg_type & ni_reg_6xxx_mask) {
4646  ni_writeb(0, Magic_611x);
4647  } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4648  int channel;
4649  for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4650  ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4651  ni_writeb(0x0,
4652  M_Offset_AO_Reference_Attenuation(channel));
4653  }
4654  ni_writeb(0x0, M_Offset_AO_Calibration);
4655  }
4656 
4657  printk("\n");
4658  return 0;
4659 }
4660 
4661 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4662 {
4663  struct comedi_device *dev = (struct comedi_device *)arg;
4664 
4665  if (dir) {
4666  ni_writeb(data, Port_A + 2 * port);
4667  return 0;
4668  } else {
4669  return ni_readb(Port_A + 2 * port);
4670  }
4671 }
4672 
4673 /*
4674  presents the EEPROM as a subdevice
4675 */
4676 
4677 static int ni_eeprom_insn_read(struct comedi_device *dev,
4678  struct comedi_subdevice *s,
4679  struct comedi_insn *insn, unsigned int *data)
4680 {
4681  data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4682 
4683  return 1;
4684 }
4685 
4686 /*
4687  reads bytes out of eeprom
4688 */
4689 
4690 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4691 {
4692  int bit;
4693  int bitstring;
4694 
4695  bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4696  ni_writeb(0x04, Serial_Command);
4697  for (bit = 0x8000; bit; bit >>= 1) {
4698  ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4699  Serial_Command);
4700  ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4701  Serial_Command);
4702  }
4703  bitstring = 0;
4704  for (bit = 0x80; bit; bit >>= 1) {
4705  ni_writeb(0x04, Serial_Command);
4706  ni_writeb(0x05, Serial_Command);
4707  bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4708  }
4709  ni_writeb(0x00, Serial_Command);
4710 
4711  return bitstring;
4712 }
4713 
4714 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4715  struct comedi_subdevice *s,
4716  struct comedi_insn *insn,
4717  unsigned int *data)
4718 {
4719  data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4720 
4721  return 1;
4722 }
4723 
4724 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4725 {
4726  data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4727  data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4728  return 3;
4729 }
4730 
4731 static int ni_m_series_pwm_config(struct comedi_device *dev,
4732  struct comedi_subdevice *s,
4733  struct comedi_insn *insn, unsigned int *data)
4734 {
4735  unsigned up_count, down_count;
4736  switch (data[0]) {
4737  case INSN_CONFIG_PWM_OUTPUT:
4738  switch (data[1]) {
4739  case TRIG_ROUND_NEAREST:
4740  up_count =
4741  (data[2] +
4742  devpriv->clock_ns / 2) / devpriv->clock_ns;
4743  break;
4744  case TRIG_ROUND_DOWN:
4745  up_count = data[2] / devpriv->clock_ns;
4746  break;
4747  case TRIG_ROUND_UP:
4748  up_count =
4749  (data[2] + devpriv->clock_ns -
4750  1) / devpriv->clock_ns;
4751  break;
4752  default:
4753  return -EINVAL;
4754  break;
4755  }
4756  switch (data[3]) {
4757  case TRIG_ROUND_NEAREST:
4758  down_count =
4759  (data[4] +
4760  devpriv->clock_ns / 2) / devpriv->clock_ns;
4761  break;
4762  case TRIG_ROUND_DOWN:
4763  down_count = data[4] / devpriv->clock_ns;
4764  break;
4765  case TRIG_ROUND_UP:
4766  down_count =
4767  (data[4] + devpriv->clock_ns -
4768  1) / devpriv->clock_ns;
4769  break;
4770  default:
4771  return -EINVAL;
4772  break;
4773  }
4774  if (up_count * devpriv->clock_ns != data[2] ||
4775  down_count * devpriv->clock_ns != data[4]) {
4776  data[2] = up_count * devpriv->clock_ns;
4777  data[4] = down_count * devpriv->clock_ns;
4778  return -EAGAIN;
4779  }
4780  ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4781  MSeries_Cal_PWM_Low_Time_Bits(down_count),
4782  M_Offset_Cal_PWM);
4783  devpriv->pwm_up_count = up_count;
4784  devpriv->pwm_down_count = down_count;
4785  return 5;
4786  break;
4787  case INSN_CONFIG_GET_PWM_OUTPUT:
4788  return ni_get_pwm_config(dev, data);
4789  break;
4790  default:
4791  return -EINVAL;
4792  break;
4793  }
4794  return 0;
4795 }
4796 
4797 static int ni_6143_pwm_config(struct comedi_device *dev,
4798  struct comedi_subdevice *s,
4799  struct comedi_insn *insn, unsigned int *data)
4800 {
4801  unsigned up_count, down_count;
4802  switch (data[0]) {
4803  case INSN_CONFIG_PWM_OUTPUT:
4804  switch (data[1]) {
4805  case TRIG_ROUND_NEAREST:
4806  up_count =
4807  (data[2] +
4808  devpriv->clock_ns / 2) / devpriv->clock_ns;
4809  break;
4810  case TRIG_ROUND_DOWN:
4811  up_count = data[2] / devpriv->clock_ns;
4812  break;
4813  case TRIG_ROUND_UP:
4814  up_count =
4815  (data[2] + devpriv->clock_ns -
4816  1) / devpriv->clock_ns;
4817  break;
4818  default:
4819  return -EINVAL;
4820  break;
4821  }
4822  switch (data[3]) {
4823  case TRIG_ROUND_NEAREST:
4824  down_count =
4825  (data[4] +
4826  devpriv->clock_ns / 2) / devpriv->clock_ns;
4827  break;
4828  case TRIG_ROUND_DOWN:
4829  down_count = data[4] / devpriv->clock_ns;
4830  break;
4831  case TRIG_ROUND_UP:
4832  down_count =
4833  (data[4] + devpriv->clock_ns -
4834  1) / devpriv->clock_ns;
4835  break;
4836  default:
4837  return -EINVAL;
4838  break;
4839  }
4840  if (up_count * devpriv->clock_ns != data[2] ||
4841  down_count * devpriv->clock_ns != data[4]) {
4842  data[2] = up_count * devpriv->clock_ns;
4843  data[4] = down_count * devpriv->clock_ns;
4844  return -EAGAIN;
4845  }
4846  ni_writel(up_count, Calibration_HighTime_6143);
4847  devpriv->pwm_up_count = up_count;
4848  ni_writel(down_count, Calibration_LowTime_6143);
4849  devpriv->pwm_down_count = down_count;
4850  return 5;
4851  break;
4852  case INSN_CONFIG_GET_PWM_OUTPUT:
4853  return ni_get_pwm_config(dev, data);
4854  default:
4855  return -EINVAL;
4856  break;
4857  }
4858  return 0;
4859 }
4860 
4861 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4862 /*
4863  calibration subdevice
4864 */
4865 static int ni_calib_insn_write(struct comedi_device *dev,
4866  struct comedi_subdevice *s,
4867  struct comedi_insn *insn, unsigned int *data)
4868 {
4869  ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4870 
4871  return 1;
4872 }
4873 
4874 static int ni_calib_insn_read(struct comedi_device *dev,
4875  struct comedi_subdevice *s,
4876  struct comedi_insn *insn, unsigned int *data)
4877 {
4878  data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4879 
4880  return 1;
4881 }
4882 
4883 static int pack_mb88341(int addr, int val, int *bitstring);
4884 static int pack_dac8800(int addr, int val, int *bitstring);
4885 static int pack_dac8043(int addr, int val, int *bitstring);
4886 static int pack_ad8522(int addr, int val, int *bitstring);
4887 static int pack_ad8804(int addr, int val, int *bitstring);
4888 static int pack_ad8842(int addr, int val, int *bitstring);
4889 
4890 struct caldac_struct {
4891  int n_chans;
4892  int n_bits;
4893  int (*packbits) (int, int, int *);
4894 };
4895 
4896 static struct caldac_struct caldacs[] = {
4897  [mb88341] = {12, 8, pack_mb88341},
4898  [dac8800] = {8, 8, pack_dac8800},
4899  [dac8043] = {1, 12, pack_dac8043},
4900  [ad8522] = {2, 12, pack_ad8522},
4901  [ad8804] = {12, 8, pack_ad8804},
4902  [ad8842] = {8, 8, pack_ad8842},
4903  [ad8804_debug] = {16, 8, pack_ad8804},
4904 };
4905 
4906 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4907 {
4908  int i, j;
4909  int n_dacs;
4910  int n_chans = 0;
4911  int n_bits;
4912  int diffbits = 0;
4913  int type;
4914  int chan;
4915 
4916  type = boardtype.caldac[0];
4917  if (type == caldac_none)
4918  return;
4919  n_bits = caldacs[type].n_bits;
4920  for (i = 0; i < 3; i++) {
4921  type = boardtype.caldac[i];
4922  if (type == caldac_none)
4923  break;
4924  if (caldacs[type].n_bits != n_bits)
4925  diffbits = 1;
4926  n_chans += caldacs[type].n_chans;
4927  }
4928  n_dacs = i;
4929  s->n_chan = n_chans;
4930 
4931  if (diffbits) {
4932  unsigned int *maxdata_list;
4933 
4934  if (n_chans > MAX_N_CALDACS) {
4935  printk("BUG! MAX_N_CALDACS too small\n");
4936  }
4937  s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4938  chan = 0;
4939  for (i = 0; i < n_dacs; i++) {
4940  type = boardtype.caldac[i];
4941  for (j = 0; j < caldacs[type].n_chans; j++) {
4942  maxdata_list[chan] =
4943  (1 << caldacs[type].n_bits) - 1;
4944  chan++;
4945  }
4946  }
4947 
4948  for (chan = 0; chan < s->n_chan; chan++)
4949  ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4950  } else {
4951  type = boardtype.caldac[0];
4952  s->maxdata = (1 << caldacs[type].n_bits) - 1;
4953 
4954  for (chan = 0; chan < s->n_chan; chan++)
4955  ni_write_caldac(dev, i, s->maxdata / 2);
4956  }
4957 }
4958 
4959 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4960 {
4961  unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4962  int i;
4963  int type;
4964 
4965  /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
4966  if (devpriv->caldacs[addr] == val)
4967  return;
4968  devpriv->caldacs[addr] = val;
4969 
4970  for (i = 0; i < 3; i++) {
4971  type = boardtype.caldac[i];
4972  if (type == caldac_none)
4973  break;
4974  if (addr < caldacs[type].n_chans) {
4975  bits = caldacs[type].packbits(addr, val, &bitstring);
4976  loadbit = SerDacLd(i);
4977  /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
4978  break;
4979  }
4980  addr -= caldacs[type].n_chans;
4981  }
4982 
4983  for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4984  ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
4985  udelay(1);
4986  ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4987  udelay(1);
4988  }
4989  ni_writeb(loadbit, Serial_Command);
4990  udelay(1);
4991  ni_writeb(0, Serial_Command);
4992 }
4993 
4994 static int pack_mb88341(int addr, int val, int *bitstring)
4995 {
4996  /*
4997  Fujitsu MB 88341
4998  Note that address bits are reversed. Thanks to
4999  Ingo Keen for noticing this.
5000 
5001  Note also that the 88341 expects address values from
5002  1-12, whereas we use channel numbers 0-11. The NI
5003  docs use 1-12, also, so be careful here.
5004  */
5005  addr++;
5006  *bitstring = ((addr & 0x1) << 11) |
5007  ((addr & 0x2) << 9) |
5008  ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5009  return 12;
5010 }
5011 
5012 static int pack_dac8800(int addr, int val, int *bitstring)
5013 {
5014  *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5015  return 11;
5016 }
5017 
5018 static int pack_dac8043(int addr, int val, int *bitstring)
5019 {
5020  *bitstring = val & 0xfff;
5021  return 12;
5022 }
5023 
5024 static int pack_ad8522(int addr, int val, int *bitstring)
5025 {
5026  *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5027  return 16;
5028 }
5029 
5030 static int pack_ad8804(int addr, int val, int *bitstring)
5031 {
5032  *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5033  return 12;
5034 }
5035 
5036 static int pack_ad8842(int addr, int val, int *bitstring)
5037 {
5038  *bitstring = ((addr + 1) << 8) | (val & 0xff);
5039  return 12;
5040 }
5041 
5042 #if 0
5043 /*
5044  * Read the GPCTs current value.
5045  */
5046 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5047 {
5048  unsigned int hi1, hi2, lo;
5049 
5050  devpriv->gpct_command[chan] &= ~G_Save_Trace;
5051  devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5052  G_Command_Register(chan));
5053 
5054  devpriv->gpct_command[chan] |= G_Save_Trace;
5055  devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5056  G_Command_Register(chan));
5057 
5058  /* This procedure is used because the two registers cannot
5059  * be read atomically. */
5060  do {
5061  hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5062  lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5063  hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5064  } while (hi1 != hi2);
5065 
5066  return (hi1 << 16) | lo;
5067 }
5068 
5069 static void GPCT_Reset(struct comedi_device *dev, int chan)
5070 {
5071  int temp_ack_reg = 0;
5072 
5073  /* printk("GPCT_Reset..."); */
5074  devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5075 
5076  switch (chan) {
5077  case 0:
5078  devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5079  ni_set_bits(dev, Interrupt_A_Enable_Register,
5080  G0_TC_Interrupt_Enable, 0);
5081  ni_set_bits(dev, Interrupt_A_Enable_Register,
5082  G0_Gate_Interrupt_Enable, 0);
5083  temp_ack_reg |= G0_Gate_Error_Confirm;
5084  temp_ack_reg |= G0_TC_Error_Confirm;
5085  temp_ack_reg |= G0_TC_Interrupt_Ack;
5086  temp_ack_reg |= G0_Gate_Interrupt_Ack;
5087  devpriv->stc_writew(dev, temp_ack_reg,
5088  Interrupt_A_Ack_Register);
5089 
5090  /* problem...this interferes with the other ctr... */
5091  devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5092  devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5093  Analog_Trigger_Etc_Register);
5094  break;
5095  case 1:
5096  devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5097  ni_set_bits(dev, Interrupt_B_Enable_Register,
5098  G1_TC_Interrupt_Enable, 0);
5099  ni_set_bits(dev, Interrupt_B_Enable_Register,
5100  G0_Gate_Interrupt_Enable, 0);
5101  temp_ack_reg |= G1_Gate_Error_Confirm;
5102  temp_ack_reg |= G1_TC_Error_Confirm;
5103  temp_ack_reg |= G1_TC_Interrupt_Ack;
5104  temp_ack_reg |= G1_Gate_Interrupt_Ack;
5105  devpriv->stc_writew(dev, temp_ack_reg,
5106  Interrupt_B_Ack_Register);
5107 
5108  devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5109  devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5110  Analog_Trigger_Etc_Register);
5111  break;
5112  }
5113 
5114  devpriv->gpct_mode[chan] = 0;
5115  devpriv->gpct_input_select[chan] = 0;
5116  devpriv->gpct_command[chan] = 0;
5117 
5118  devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5119 
5120  devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5121  G_Mode_Register(chan));
5122  devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5123  G_Input_Select_Register(chan));
5124  devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5125 
5126  /* printk("exit GPCT_Reset\n"); */
5127 }
5128 
5129 #endif
5130 
5131 static int ni_gpct_insn_config(struct comedi_device *dev,
5132  struct comedi_subdevice *s,
5133  struct comedi_insn *insn, unsigned int *data)
5134 {
5135  struct ni_gpct *counter = s->private;
5136  return ni_tio_insn_config(counter, insn, data);
5137 }
5138 
5139 static int ni_gpct_insn_read(struct comedi_device *dev,
5140  struct comedi_subdevice *s,
5141  struct comedi_insn *insn, unsigned int *data)
5142 {
5143  struct ni_gpct *counter = s->private;
5144  return ni_tio_rinsn(counter, insn, data);
5145 }
5146 
5147 static int ni_gpct_insn_write(struct comedi_device *dev,
5148  struct comedi_subdevice *s,
5149  struct comedi_insn *insn, unsigned int *data)
5150 {
5151  struct ni_gpct *counter = s->private;
5152  return ni_tio_winsn(counter, insn, data);
5153 }
5154 
5155 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5156 {
5157  int retval;
5158 #ifdef PCIDMA
5159  struct ni_gpct *counter = s->private;
5160 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5161 
5162  retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5163  COMEDI_INPUT);
5164  if (retval) {
5165  comedi_error(dev,
5166  "no dma channel available for use by counter");
5167  return retval;
5168  }
5169  ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5170  ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5171  retval = ni_tio_cmd(counter, s->async);
5172 #else
5173  retval = -ENOTSUPP;
5174 #endif
5175  return retval;
5176 }
5177 
5178 static int ni_gpct_cmdtest(struct comedi_device *dev,
5179  struct comedi_subdevice *s, struct comedi_cmd *cmd)
5180 {
5181 #ifdef PCIDMA
5182  struct ni_gpct *counter = s->private;
5183 
5184  return ni_tio_cmdtest(counter, cmd);
5185 #else
5186  return -ENOTSUPP;
5187 #endif
5188 }
5189 
5190 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5191 {
5192 #ifdef PCIDMA
5193  struct ni_gpct *counter = s->private;
5194  int retval;
5195 
5196  retval = ni_tio_cancel(counter);
5197  ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5198  ni_release_gpct_mite_channel(dev, counter->counter_index);
5199  return retval;
5200 #else
5201  return 0;
5202 #endif
5203 }
5204 
5205 /*
5206  *
5207  * Programmable Function Inputs
5208  *
5209  */
5210 
5211 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5212  unsigned source)
5213 {
5214  unsigned pfi_reg_index;
5215  unsigned array_offset;
5216  if ((source & 0x1f) != source)
5217  return -EINVAL;
5218  pfi_reg_index = 1 + chan / 3;
5219  array_offset = pfi_reg_index - 1;
5220  devpriv->pfi_output_select_reg[array_offset] &=
5221  ~MSeries_PFI_Output_Select_Mask(chan);
5222  devpriv->pfi_output_select_reg[array_offset] |=
5223  MSeries_PFI_Output_Select_Bits(chan, source);
5224  ni_writew(devpriv->pfi_output_select_reg[array_offset],
5225  M_Offset_PFI_Output_Select(pfi_reg_index));
5226  return 2;
5227 }
5228 
5229 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5230  unsigned source)
5231 {
5232  /* pre-m-series boards have fixed signals on pfi pins */
5233  if (source != ni_old_get_pfi_routing(dev, chan))
5234  return -EINVAL;
5235  return 2;
5236 }
5237 
5238 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5239  unsigned source)
5240 {
5241  if (boardtype.reg_type & ni_reg_m_series_mask)
5242  return ni_m_series_set_pfi_routing(dev, chan, source);
5243  else
5244  return ni_old_set_pfi_routing(dev, chan, source);
5245 }
5246 
5247 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5248  unsigned chan)
5249 {
5250  const unsigned array_offset = chan / 3;
5251  return MSeries_PFI_Output_Select_Source(chan,
5252  devpriv->
5253  pfi_output_select_reg
5254  [array_offset]);
5255 }
5256 
5257 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5258 {
5259  /* pre-m-series boards have fixed signals on pfi pins */
5260  switch (chan) {
5261  case 0:
5262  return NI_PFI_OUTPUT_AI_START1;
5263  break;
5264  case 1:
5265  return NI_PFI_OUTPUT_AI_START2;
5266  break;
5267  case 2:
5268  return NI_PFI_OUTPUT_AI_CONVERT;
5269  break;
5270  case 3:
5271  return NI_PFI_OUTPUT_G_SRC1;
5272  break;
5273  case 4:
5274  return NI_PFI_OUTPUT_G_GATE1;
5275  break;
5276  case 5:
5277  return NI_PFI_OUTPUT_AO_UPDATE_N;
5278  break;
5279  case 6:
5280  return NI_PFI_OUTPUT_AO_START1;
5281  break;
5282  case 7:
5283  return NI_PFI_OUTPUT_AI_START_PULSE;
5284  break;
5285  case 8:
5286  return NI_PFI_OUTPUT_G_SRC0;
5287  break;
5288  case 9:
5289  return NI_PFI_OUTPUT_G_GATE0;
5290  break;
5291  default:
5292  printk("%s: bug, unhandled case in switch.\n", __func__);
5293  break;
5294  }
5295  return 0;
5296 }
5297 
5298 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5299 {
5300  if (boardtype.reg_type & ni_reg_m_series_mask)
5301  return ni_m_series_get_pfi_routing(dev, chan);
5302  else
5303  return ni_old_get_pfi_routing(dev, chan);
5304 }
5305 
5306 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5307  enum ni_pfi_filter_select filter)
5308 {
5309  unsigned bits;
5310  if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5311  return -ENOTSUPP;
5312  }
5313  bits = ni_readl(M_Offset_PFI_Filter);
5314  bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5315  bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5316  ni_writel(bits, M_Offset_PFI_Filter);
5317  return 0;
5318 }
5319 
5320 static int ni_pfi_insn_bits(struct comedi_device *dev,
5321  struct comedi_subdevice *s,
5322  struct comedi_insn *insn, unsigned int *data)
5323 {
5324  if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5325  return -ENOTSUPP;
5326  }
5327  if (data[0]) {
5328  s->state &= ~data[0];
5329  s->state |= (data[0] & data[1]);
5330  ni_writew(s->state, M_Offset_PFI_DO);
5331  }
5332  data[1] = ni_readw(M_Offset_PFI_DI);
5333  return insn->n;
5334 }
5335 
5336 static int ni_pfi_insn_config(struct comedi_device *dev,
5337  struct comedi_subdevice *s,
5338  struct comedi_insn *insn, unsigned int *data)
5339 {
5340  unsigned int chan;
5341 
5342  if (insn->n < 1)
5343  return -EINVAL;
5344 
5345  chan = CR_CHAN(insn->chanspec);
5346 
5347  switch (data[0]) {
5348  case COMEDI_OUTPUT:
5349  ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5350  break;
5351  case COMEDI_INPUT:
5352  ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5353  break;
5354  case INSN_CONFIG_DIO_QUERY:
5355  data[1] =
5356  (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5357  COMEDI_OUTPUT : COMEDI_INPUT;
5358  return 0;
5359  break;
5360  case INSN_CONFIG_SET_ROUTING:
5361  return ni_set_pfi_routing(dev, chan, data[1]);
5362  break;
5363  case INSN_CONFIG_GET_ROUTING:
5364  data[1] = ni_get_pfi_routing(dev, chan);
5365  break;
5366  case INSN_CONFIG_FILTER:
5367  return ni_config_filter(dev, chan, data[1]);
5368  break;
5369  default:
5370  return -EINVAL;
5371  }
5372  return 0;
5373 }
5374 
5375 /*
5376  *
5377  * NI RTSI Bus Functions
5378  *
5379  */
5380 static void ni_rtsi_init(struct comedi_device *dev)
5381 {
5382  /* Initialises the RTSI bus signal switch to a default state */
5383 
5384  /* Set clock mode to internal */
5385  devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5386  if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5387  printk("ni_set_master_clock failed, bug?");
5388  }
5389  /* default internal lines routing to RTSI bus lines */
5390  devpriv->rtsi_trig_a_output_reg =
5391  RTSI_Trig_Output_Bits(0,
5392  NI_RTSI_OUTPUT_ADR_START1) |
5393  RTSI_Trig_Output_Bits(1,
5394  NI_RTSI_OUTPUT_ADR_START2) |
5395  RTSI_Trig_Output_Bits(2,
5396  NI_RTSI_OUTPUT_SCLKG) |
5397  RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5398  devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5399  RTSI_Trig_A_Output_Register);
5400  devpriv->rtsi_trig_b_output_reg =
5401  RTSI_Trig_Output_Bits(4,
5402  NI_RTSI_OUTPUT_DA_START1) |
5403  RTSI_Trig_Output_Bits(5,
5404  NI_RTSI_OUTPUT_G_SRC0) |
5405  RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5406  if (boardtype.reg_type & ni_reg_m_series_mask)
5407  devpriv->rtsi_trig_b_output_reg |=
5408  RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5409  devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5410  RTSI_Trig_B_Output_Register);
5411 
5412 /*
5413 * Sets the source and direction of the 4 on board lines
5414 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5415 */
5416 }
5417 
5418 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5419  struct comedi_subdevice *s,
5420  struct comedi_insn *insn, unsigned int *data)
5421 {
5422  data[1] = 0;
5423 
5424  return insn->n;
5425 }
5426 
5427 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5428  * given an arbitrary frequency input clock */
5429 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5430  unsigned *freq_divider,
5431  unsigned *freq_multiplier,
5432  unsigned *actual_period_ns)
5433 {
5434  unsigned div;
5435  unsigned best_div = 1;
5436  static const unsigned max_div = 0x10;
5437  unsigned mult;
5438  unsigned best_mult = 1;
5439  static const unsigned max_mult = 0x100;
5440  static const unsigned pico_per_nano = 1000;
5441 
5442  const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5443  /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5444  * 20 MHz for most timing clocks */
5445  static const unsigned target_picosec = 12500;
5446  static const unsigned fudge_factor_80_to_20Mhz = 4;
5447  int best_period_picosec = 0;
5448  for (div = 1; div <= max_div; ++div) {
5449  for (mult = 1; mult <= max_mult; ++mult) {
5450  unsigned new_period_ps =
5451  (reference_picosec * div) / mult;
5452  if (abs(new_period_ps - target_picosec) <
5453  abs(best_period_picosec - target_picosec)) {
5454  best_period_picosec = new_period_ps;
5455  best_div = div;
5456  best_mult = mult;
5457  }
5458  }
5459  }
5460  if (best_period_picosec == 0) {
5461  printk("%s: bug, failed to find pll parameters\n", __func__);
5462  return -EIO;
5463  }
5464  *freq_divider = best_div;
5465  *freq_multiplier = best_mult;
5466  *actual_period_ns =
5467  (best_period_picosec * fudge_factor_80_to_20Mhz +
5468  (pico_per_nano / 2)) / pico_per_nano;
5469  return 0;
5470 }
5471 
5472 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5473 {
5474  if (boardtype.reg_type & ni_reg_m_series_mask)
5475  return 8;
5476  else
5477  return 7;
5478 }
5479 
5480 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5481  unsigned source, unsigned period_ns)
5482 {
5483  static const unsigned min_period_ns = 50;
5484  static const unsigned max_period_ns = 1000;
5485  static const unsigned timeout = 1000;
5486  unsigned pll_control_bits;
5487  unsigned freq_divider;
5488  unsigned freq_multiplier;
5489  unsigned i;
5490  int retval;
5491  if (source == NI_MIO_PLL_PXI10_CLOCK)
5492  period_ns = 100;
5493  /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5494  if (period_ns < min_period_ns || period_ns > max_period_ns) {
5495  printk
5496  ("%s: you must specify an input clock frequency between %i and %i nanosec "
5497  "for the phased-lock loop.\n", __func__,
5498  min_period_ns, max_period_ns);
5499  return -EINVAL;
5500  }
5501  devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5502  devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5503  RTSI_Trig_Direction_Register);
5504  pll_control_bits =
5505  MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5506  devpriv->clock_and_fout2 |=
5507  MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5508  devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5509  switch (source) {
5510  case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5511  devpriv->clock_and_fout2 |=
5512  MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5513  retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5514  &freq_multiplier,
5515  &devpriv->clock_ns);
5516  if (retval < 0)
5517  return retval;
5518  break;
5519  case NI_MIO_PLL_PXI10_CLOCK:
5520  /* pxi clock is 10MHz */
5521  devpriv->clock_and_fout2 |=
5522  MSeries_PLL_In_Source_Select_PXI_Clock10;
5523  retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5524  &freq_multiplier,
5525  &devpriv->clock_ns);
5526  if (retval < 0)
5527  return retval;
5528  break;
5529  default:
5530  {
5531  unsigned rtsi_channel;
5532  static const unsigned max_rtsi_channel = 7;
5533  for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5534  ++rtsi_channel) {
5535  if (source ==
5536  NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5537  devpriv->clock_and_fout2 |=
5538  MSeries_PLL_In_Source_Select_RTSI_Bits
5539  (rtsi_channel);
5540  break;
5541  }
5542  }
5543  if (rtsi_channel > max_rtsi_channel)
5544  return -EINVAL;
5545  retval = ni_mseries_get_pll_parameters(period_ns,
5546  &freq_divider,
5547  &freq_multiplier,
5548  &devpriv->
5549  clock_ns);
5550  if (retval < 0)
5551  return retval;
5552  }
5553  break;
5554  }
5555  ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5556  pll_control_bits |=
5557  MSeries_PLL_Divisor_Bits(freq_divider) |
5558  MSeries_PLL_Multiplier_Bits(freq_multiplier);
5559 
5560  /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5561  * freq_divider, freq_multiplier, pll_control_bits); */
5562  /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5563  ni_writew(pll_control_bits, M_Offset_PLL_Control);
5564  devpriv->clock_source = source;
5565  /* it seems to typically take a few hundred microseconds for PLL to lock */
5566  for (i = 0; i < timeout; ++i) {
5567  if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5568  break;
5569  }
5570  udelay(1);
5571  }
5572  if (i == timeout) {
5573  printk
5574  ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5575  __func__, source, period_ns);
5576  return -ETIMEDOUT;
5577  }
5578  return 3;
5579 }
5580 
5581 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5582  unsigned period_ns)
5583 {
5584  if (source == NI_MIO_INTERNAL_CLOCK) {
5585  devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5586  devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5587  RTSI_Trig_Direction_Register);
5588  devpriv->clock_ns = TIMEBASE_1_NS;
5589  if (boardtype.reg_type & ni_reg_m_series_mask) {
5590  devpriv->clock_and_fout2 &=
5591  ~(MSeries_Timebase1_Select_Bit |
5592  MSeries_Timebase3_Select_Bit);
5593  ni_writew(devpriv->clock_and_fout2,
5594  M_Offset_Clock_and_Fout2);
5595  ni_writew(0, M_Offset_PLL_Control);
5596  }
5597  devpriv->clock_source = source;
5598  } else {
5599  if (boardtype.reg_type & ni_reg_m_series_mask) {
5600  return ni_mseries_set_pll_master_clock(dev, source,
5601  period_ns);
5602  } else {
5603  if (source == NI_MIO_RTSI_CLOCK) {
5604  devpriv->rtsi_trig_direction_reg |=
5605  Use_RTSI_Clock_Bit;
5606  devpriv->stc_writew(dev,
5607  devpriv->
5608  rtsi_trig_direction_reg,
5609  RTSI_Trig_Direction_Register);
5610  if (period_ns == 0) {
5611  printk
5612  ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5613  __func__);
5614  return -EINVAL;
5615  } else {
5616  devpriv->clock_ns = period_ns;
5617  }
5618  devpriv->clock_source = source;
5619  } else
5620  return -EINVAL;
5621  }
5622  }
5623  return 3;
5624 }
5625 
5626 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5627  unsigned source)
5628 {
5629  if (chan >= num_configurable_rtsi_channels(dev)) {
5630  if (chan == old_RTSI_clock_channel) {
5631  if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5632  return 1;
5633  else {
5634  printk
5635  ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5636  __func__, chan, old_RTSI_clock_channel);
5637  return 0;
5638  }
5639  }
5640  return 0;
5641  }
5642  switch (source) {
5643  case NI_RTSI_OUTPUT_ADR_START1:
5644  case NI_RTSI_OUTPUT_ADR_START2:
5645  case NI_RTSI_OUTPUT_SCLKG:
5646  case NI_RTSI_OUTPUT_DACUPDN:
5647  case NI_RTSI_OUTPUT_DA_START1:
5648  case NI_RTSI_OUTPUT_G_SRC0:
5649  case NI_RTSI_OUTPUT_G_GATE0:
5650  case NI_RTSI_OUTPUT_RGOUT0:
5651  case NI_RTSI_OUTPUT_RTSI_BRD_0:
5652  return 1;
5653  break;
5654  case NI_RTSI_OUTPUT_RTSI_OSC:
5655  if (boardtype.reg_type & ni_reg_m_series_mask)
5656  return 1;
5657  else
5658  return 0;
5659  break;
5660  default:
5661  return 0;
5662  break;
5663  }
5664 }
5665 
5666 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5667  unsigned source)
5668 {
5669  if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5670  return -EINVAL;
5671  if (chan < 4) {
5672  devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5673  devpriv->rtsi_trig_a_output_reg |=
5674  RTSI_Trig_Output_Bits(chan, source);
5675  devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5676  RTSI_Trig_A_Output_Register);
5677  } else if (chan < 8) {
5678  devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5679  devpriv->rtsi_trig_b_output_reg |=
5680  RTSI_Trig_Output_Bits(chan, source);
5681  devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5682  RTSI_Trig_B_Output_Register);
5683  }
5684  return 2;
5685 }
5686 
5687 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5688 {
5689  if (chan < 4) {
5690  return RTSI_Trig_Output_Source(chan,
5691  devpriv->rtsi_trig_a_output_reg);
5692  } else if (chan < num_configurable_rtsi_channels(dev)) {
5693  return RTSI_Trig_Output_Source(chan,
5694  devpriv->rtsi_trig_b_output_reg);
5695  } else {
5696  if (chan == old_RTSI_clock_channel)
5697  return NI_RTSI_OUTPUT_RTSI_OSC;
5698  printk("%s: bug! should never get here?\n", __func__);
5699  return 0;
5700  }
5701 }
5702 
5703 static int ni_rtsi_insn_config(struct comedi_device *dev,
5704  struct comedi_subdevice *s,
5705  struct comedi_insn *insn, unsigned int *data)
5706 {
5707  unsigned int chan = CR_CHAN(insn->chanspec);
5708  switch (data[0]) {
5709  case INSN_CONFIG_DIO_OUTPUT:
5710  if (chan < num_configurable_rtsi_channels(dev)) {
5711  devpriv->rtsi_trig_direction_reg |=
5712  RTSI_Output_Bit(chan,
5713  (boardtype.
5714  reg_type & ni_reg_m_series_mask) !=
5715  0);
5716  } else if (chan == old_RTSI_clock_channel) {
5717  devpriv->rtsi_trig_direction_reg |=
5718  Drive_RTSI_Clock_Bit;
5719  }
5720  devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5721  RTSI_Trig_Direction_Register);
5722  break;
5723  case INSN_CONFIG_DIO_INPUT:
5724  if (chan < num_configurable_rtsi_channels(dev)) {
5725  devpriv->rtsi_trig_direction_reg &=
5726  ~RTSI_Output_Bit(chan,
5727  (boardtype.
5728  reg_type & ni_reg_m_series_mask)
5729  != 0);
5730  } else if (chan == old_RTSI_clock_channel) {
5731  devpriv->rtsi_trig_direction_reg &=
5732  ~Drive_RTSI_Clock_Bit;
5733  }
5734  devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5735  RTSI_Trig_Direction_Register);
5736  break;
5737  case INSN_CONFIG_DIO_QUERY:
5738  if (chan < num_configurable_rtsi_channels(dev)) {
5739  data[1] =
5740  (devpriv->rtsi_trig_direction_reg &
5741  RTSI_Output_Bit(chan,
5742  (boardtype.reg_type &
5743  ni_reg_m_series_mask)
5744  != 0)) ? INSN_CONFIG_DIO_OUTPUT :
5745  INSN_CONFIG_DIO_INPUT;
5746  } else if (chan == old_RTSI_clock_channel) {
5747  data[1] =
5748  (devpriv->rtsi_trig_direction_reg &
5749  Drive_RTSI_Clock_Bit)
5750  ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5751  }
5752  return 2;
5753  break;
5754  case INSN_CONFIG_SET_CLOCK_SRC:
5755  return ni_set_master_clock(dev, data[1], data[2]);
5756  break;
5757  case INSN_CONFIG_GET_CLOCK_SRC:
5758  data[1] = devpriv->clock_source;
5759  data[2] = devpriv->clock_ns;
5760  return 3;
5761  break;
5762  case INSN_CONFIG_SET_ROUTING:
5763  return ni_set_rtsi_routing(dev, chan, data[1]);
5764  break;
5765  case INSN_CONFIG_GET_ROUTING:
5766  data[1] = ni_get_rtsi_routing(dev, chan);
5767  return 2;
5768  break;
5769  default:
5770  return -EINVAL;
5771  break;
5772  }
5773  return 1;
5774 }
5775 
5776 static int cs5529_wait_for_idle(struct comedi_device *dev)
5777 {
5778  unsigned short status;
5779  const int timeout = HZ;
5780  int i;
5781 
5782  for (i = 0; i < timeout; i++) {
5783  status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5784  if ((status & CSS_ADC_BUSY) == 0) {
5785  break;
5786  }
5787  set_current_state(TASK_INTERRUPTIBLE);
5788  if (schedule_timeout(1)) {
5789  return -EIO;
5790  }
5791  }
5792 /* printk("looped %i times waiting for idle\n", i); */
5793  if (i == timeout) {
5794  printk("%s: %s: timeout\n", __FILE__, __func__);
5795  return -ETIME;
5796  }
5797  return 0;
5798 }
5799 
5800 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5801 {
5802  static const int timeout = 100;
5803  int i;
5804 
5805  ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5806  /* give time for command to start being serially clocked into cs5529.
5807  * this insures that the CSS_ADC_BUSY bit will get properly
5808  * set before we exit this function.
5809  */
5810  for (i = 0; i < timeout; i++) {
5811  if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5812  break;
5813  udelay(1);
5814  }
5815 /* printk("looped %i times writing command to cs5529\n", i); */
5816  if (i == timeout) {
5817  comedi_error(dev, "possible problem - never saw adc go busy?");
5818  }
5819 }
5820 
5821 /* write to cs5529 register */
5822 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5823  unsigned int reg_select_bits)
5824 {
5825  ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5826  CAL_ADC_Config_Data_High_Word_67xx);
5827  ni_ao_win_outw(dev, (value & 0xffff),
5828  CAL_ADC_Config_Data_Low_Word_67xx);
5829  reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5830  cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5831  if (cs5529_wait_for_idle(dev))
5832  comedi_error(dev, "time or signal in cs5529_config_write()");
5833 }
5834 
5835 #ifdef NI_CS5529_DEBUG
5836 /* read from cs5529 register */
5837 static unsigned int cs5529_config_read(struct comedi_device *dev,
5838  unsigned int reg_select_bits)
5839 {
5840  unsigned int value;
5841 
5842  reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5843  cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5844  if (cs5529_wait_for_idle(dev))
5845  comedi_error(dev, "timeout or signal in cs5529_config_read()");
5846  value = (ni_ao_win_inw(dev,
5847  CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5848  0xff0000;
5849  value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5850  return value;
5851 }
5852 #endif
5853 
5854 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5855 {
5856  int retval;
5857  unsigned short status;
5858 
5859  cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5860  retval = cs5529_wait_for_idle(dev);
5861  if (retval) {
5862  comedi_error(dev,
5863  "timeout or signal in cs5529_do_conversion()");
5864  return -ETIME;
5865  }
5866  status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5867  if (status & CSS_OSC_DETECT) {
5868  printk
5869  ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5870  return -EIO;
5871  }
5872  if (status & CSS_OVERRANGE) {
5873  printk
5874  ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5875  }
5876  if (data) {
5877  *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5878  /* cs5529 returns 16 bit signed data in bipolar mode */
5879  *data ^= (1 << 15);
5880  }
5881  return 0;
5882 }
5883 
5884 static int cs5529_ai_insn_read(struct comedi_device *dev,
5885  struct comedi_subdevice *s,
5886  struct comedi_insn *insn, unsigned int *data)
5887 {
5888  int n, retval;
5889  unsigned short sample;
5890  unsigned int channel_select;
5891  const unsigned int INTERNAL_REF = 0x1000;
5892 
5893  /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5894  * do nothing. bit 12 seems to chooses internal reference voltage, bit
5895  * 13 causes the adc input to go overrange (maybe reads external reference?) */
5896  if (insn->chanspec & CR_ALT_SOURCE)
5897  channel_select = INTERNAL_REF;
5898  else
5899  channel_select = CR_CHAN(insn->chanspec);
5900  ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5901 
5902  for (n = 0; n < insn->n; n++) {
5903  retval = cs5529_do_conversion(dev, &sample);
5904  if (retval < 0)
5905  return retval;
5906  data[n] = sample;
5907  }
5908  return insn->n;
5909 }
5910 
5911 static int init_cs5529(struct comedi_device *dev)
5912 {
5913  unsigned int config_bits =
5914  CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5915 
5916 #if 1
5917  /* do self-calibration */
5918  cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5919  CSCMD_CONFIG_REGISTER);
5920  /* need to force a conversion for calibration to run */
5921  cs5529_do_conversion(dev, NULL);
5922 #else
5923  /* force gain calibration to 1 */
5924  cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5925  cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5926  CSCMD_CONFIG_REGISTER);
5927  if (cs5529_wait_for_idle(dev))
5928  comedi_error(dev, "timeout or signal in init_cs5529()\n");
5929 #endif
5930 #ifdef NI_CS5529_DEBUG
5931  printk("config: 0x%x\n", cs5529_config_read(dev,
5932  CSCMD_CONFIG_REGISTER));
5933  printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
5934  printk("offset: 0x%x\n", cs5529_config_read(dev,
5935  CSCMD_OFFSET_REGISTER));
5936 #endif
5937  return 0;
5938 }
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