31 #include <linux/pci.h>
32 #include <linux/slab.h>
33 #include <linux/module.h>
43 #define CARD_NAME "NeoMagic 256AV/ZX"
44 #define DRIVER_NAME "NM256"
50 "{NeoMagic,NM256ZX}}");
58 static int playback_bufsize = 16;
59 static int capture_bufsize = 16;
60 static bool force_ac97;
61 static int buffer_top;
62 static bool use_cache;
63 static bool vaio_hack;
64 static bool reset_workaround;
65 static bool reset_workaround_2;
80 MODULE_PARM_DESC(use_cache,
"Enable the cache for coefficient table access.");
84 MODULE_PARM_DESC(reset_workaround,
"Enable AC97 RESET workaround for some laptops.");
86 MODULE_PARM_DESC(reset_workaround_2,
"Enable extended AC97 RESET workaround for some other laptops.");
99 #define NM_SIGNATURE 0x4e4d0000
101 #define NM_SIG_MASK 0xffff0000
104 #define NM_PORT2_SIZE 4096
107 #define NM_MIXER_OFFSET 0x600
110 #define NM_MAX_PLAYBACK_COEF_SIZE 0x5000
111 #define NM_MAX_RECORD_COEF_SIZE 0x1260
114 #define NM_INT_REG 0xa04
116 #define NM_PLAYBACK_INT 0x40
117 #define NM_RECORD_INT 0x100
118 #define NM_MISC_INT_1 0x4000
119 #define NM_MISC_INT_2 0x1
120 #define NM_ACK_INT(chip, X) snd_nm256_writew(chip, NM_INT_REG, (X) << 1)
123 #define NM_MIXER_STATUS_OFFSET 0xa04
124 #define NM_MIXER_READY_MASK 0x0800
125 #define NM_MIXER_PRESENCE 0xa06
126 #define NM_PRESENCE_MASK 0x0050
127 #define NM_PRESENCE_VALUE 0x0040
133 #define NM2_PLAYBACK_INT 0x10000
134 #define NM2_RECORD_INT 0x80000
135 #define NM2_MISC_INT_1 0x8
136 #define NM2_MISC_INT_2 0x2
137 #define NM2_ACK_INT(chip, X) snd_nm256_writel(chip, NM_INT_REG, (X))
140 #define NM2_MIXER_STATUS_OFFSET 0xa06
141 #define NM2_MIXER_READY_MASK 0x0800
144 #define NM_PLAYBACK_REG_OFFSET 0x0
146 #define NM_RECORD_REG_OFFSET 0x200
149 #define NM_RATE_REG_OFFSET 2
152 #define NM_RATE_STEREO 1
153 #define NM_RATE_BITS_16 2
154 #define NM_RATE_MASK 0xf0
157 #define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1)
158 #define NM_PLAYBACK_ENABLE_FLAG 1
159 #define NM_PLAYBACK_ONESHOT 2
160 #define NM_PLAYBACK_FREERUN 4
163 #define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18)
164 #define NM_AUDIO_MUTE_LEFT 0x8000
165 #define NM_AUDIO_MUTE_RIGHT 0x0080
168 #define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0)
169 #define NM_RECORD_ENABLE_FLAG 1
170 #define NM_RECORD_FREERUN 2
173 #define NM_COEFF_START_OFFSET 0x1c
174 #define NM_COEFF_END_OFFSET 0x20
177 #define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4)
178 #define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10)
179 #define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc)
180 #define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8)
182 #define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4)
183 #define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14)
184 #define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc)
185 #define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8)
319 #ifdef CONFIG_SND_DEBUG
334 snd_nm256_get_start_offset(
int which)
338 offset += coefficient_sizes[which];
343 snd_nm256_load_one_coefficient(
struct nm256 *chip,
int stream,
u32 port,
int which)
346 u16 offset = snd_nm256_get_start_offset(which);
347 u16 size = coefficient_sizes[which];
349 snd_nm256_write_buffer(chip, coefficients + offset, coeff_buf, size);
350 snd_nm256_writel(chip, port, coeff_buf);
354 snd_nm256_writel(chip, port + 4, coeff_buf + size);
358 snd_nm256_load_coefficient(
struct nm256 *chip,
int stream,
int number)
368 if (snd_nm256_readb(chip, poffset) & 1) {
369 snd_printd(
"NM256: Engine was enabled while loading coefficients!\n");
379 snd_nm256_load_one_coefficient(chip, stream, addr, number);
383 snd_nm256_write_buffer(chip, coefficients, chip->
all_coeff_buf,
388 u32 offset = snd_nm256_get_start_offset(number);
390 snd_nm256_writel(chip, addr, base + offset);
393 snd_nm256_writel(chip, addr + 4, base + end_offset);
399 static unsigned int samplerates[8] = {
400 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
412 snd_nm256_fixed_rate(
unsigned int rate)
415 for (i = 0; i <
ARRAY_SIZE(samplerates); i++) {
416 if (rate == samplerates[i])
431 int rate_index = snd_nm256_fixed_rate(runtime->
rate);
432 unsigned char ratebits = (rate_index << 4) &
NM_RATE_MASK;
444 runtime->
rate = samplerates[rate_index];
446 switch (substream->
stream) {
448 snd_nm256_load_coefficient(chip, 0, rate_index);
449 snd_nm256_writeb(chip,
454 snd_nm256_load_coefficient(chip, 1, rate_index);
455 snd_nm256_writeb(chip,
463 static int snd_nm256_acquire_irq(
struct nm256 *chip)
468 KBUILD_MODNAME, chip)) {
473 chip->
irq = chip->
pci->irq;
481 static void snd_nm256_release_irq(
struct nm256 *chip)
505 #define snd_nm256_playback_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_PBUFFER_WMARK)
506 #define snd_nm256_capture_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_RBUFFER_WMARK)
542 snd_nm256_playback_stop(
struct nm256 *chip)
552 snd_nm256_capture_stop(
struct nm256 *chip)
575 snd_nm256_playback_start(chip, s, substream);
584 snd_nm256_playback_stop(chip);
611 snd_nm256_capture_start(chip, s, substream);
618 snd_nm256_capture_stop(chip);
642 s->
dma_size = frames_to_bytes(runtime, substream->
runtime->buffer_size);
649 snd_nm256_set_format(chip, s, substream);
670 return bytes_to_frames(substream->
runtime, curp);
684 return bytes_to_frames(substream->
runtime, curp);
701 count = frames_to_bytes(runtime, count);
702 pos = frames_to_bytes(runtime, pos);
716 count = frames_to_bytes(runtime, count);
717 pos = frames_to_bytes(runtime, pos);
735 count = frames_to_bytes(runtime, count);
736 pos = frames_to_bytes(runtime, pos);
751 snd_nm256_playback_update(
struct nm256 *chip)
766 snd_nm256_capture_update(
struct nm256 *chip)
796 .buffer_bytes_max = 128 * 1024,
797 .period_bytes_min = 256,
798 .period_bytes_max = 128 * 1024,
815 .buffer_bytes_max = 128 * 1024,
816 .period_bytes_min = 256,
817 .period_bytes_max = 128 * 1024,
841 runtime->
hw.buffer_bytes_max = s->
bufsize;
842 runtime->
hw.period_bytes_max = s->
bufsize / 2;
858 if (snd_nm256_acquire_irq(chip) < 0)
861 substream, &snd_nm256_playback);
870 if (snd_nm256_acquire_irq(chip) < 0)
873 substream, &snd_nm256_capture);
885 snd_nm256_release_irq(chip);
895 snd_nm256_release_irq(chip);
902 static struct snd_pcm_ops snd_nm256_playback_ops = {
903 .open = snd_nm256_playback_open,
904 .close = snd_nm256_playback_close,
906 .hw_params = snd_nm256_pcm_hw_params,
907 .prepare = snd_nm256_pcm_prepare,
908 .trigger = snd_nm256_playback_trigger,
909 .pointer = snd_nm256_playback_pointer,
911 .copy = snd_nm256_playback_copy,
912 .silence = snd_nm256_playback_silence,
917 static struct snd_pcm_ops snd_nm256_capture_ops = {
918 .open = snd_nm256_capture_open,
919 .close = snd_nm256_capture_close,
921 .hw_params = snd_nm256_pcm_hw_params,
922 .prepare = snd_nm256_pcm_prepare,
923 .trigger = snd_nm256_capture_trigger,
924 .pointer = snd_nm256_capture_pointer,
926 .copy = snd_nm256_capture_copy,
937 for (i = 0; i < 2; i++) {
963 snd_nm256_init_chip(
struct nm256 *chip)
966 snd_nm256_writeb(chip, 0x0, 0x11);
967 snd_nm256_writew(chip, 0x214, 0);
975 snd_nm256_intr_check(
struct nm256 *chip)
991 snd_nm256_playback_stop(chip);
993 snd_nm256_capture_stop(chip);
1010 snd_nm256_interrupt(
int irq,
void *
dev_id)
1020 return snd_nm256_intr_check(chip);
1028 status &= ~NM_PLAYBACK_INT;
1030 snd_nm256_playback_update(chip);
1034 status &= ~NM_RECORD_INT;
1036 snd_nm256_capture_update(chip);
1040 status &= ~NM_MISC_INT_1;
1042 snd_printd(
"NM256: Got misc interrupt #1\n");
1044 cbyte = snd_nm256_readb(chip, 0x400);
1045 snd_nm256_writeb(chip, 0x400, cbyte | 2);
1049 status &= ~NM_MISC_INT_2;
1051 snd_printd(
"NM256: Got misc interrupt #2\n");
1052 cbyte = snd_nm256_readb(chip, 0x400);
1053 snd_nm256_writeb(chip, 0x400, cbyte & ~2);
1058 snd_printd(
"NM256: Fire in the hole! Unknown status 0x%x\n",
1075 snd_nm256_interrupt_zx(
int irq,
void *dev_id)
1085 return snd_nm256_intr_check(chip);
1093 status &= ~NM2_PLAYBACK_INT;
1095 snd_nm256_playback_update(chip);
1099 status &= ~NM2_RECORD_INT;
1101 snd_nm256_capture_update(chip);
1105 status &= ~NM2_MISC_INT_1;
1107 snd_printd(
"NM256: Got misc interrupt #1\n");
1108 cbyte = snd_nm256_readb(chip, 0x400);
1109 snd_nm256_writeb(chip, 0x400, cbyte | 2);
1113 status &= ~NM2_MISC_INT_2;
1115 snd_printd(
"NM256: Got misc interrupt #2\n");
1116 cbyte = snd_nm256_readb(chip, 0x400);
1117 snd_nm256_writeb(chip, 0x400, cbyte & ~2);
1122 snd_printd(
"NM256: Fire in the hole! Unknown status 0x%x\n",
1141 snd_nm256_ac97_ready(
struct nm256 *chip)
1153 while (timeout-- > 0) {
1154 if ((snd_nm256_readw(chip, testaddr) & testb) == 0)
1195 static int nm256_ac97_idx(
unsigned short reg)
1198 for (i = 0; i <
ARRAY_SIZE(nm256_ac97_init_val); i++)
1199 if (nm256_ac97_init_val[i].reg == reg)
1209 static unsigned short
1210 snd_nm256_ac97_read(
struct snd_ac97 *ac97,
unsigned short reg)
1213 int idx = nm256_ac97_idx(reg);
1223 snd_nm256_ac97_write(
struct snd_ac97 *ac97,
1224 unsigned short reg,
unsigned short val)
1228 int idx = nm256_ac97_idx(reg);
1236 snd_nm256_ac97_ready(chip);
1239 while (tries-- > 0) {
1240 snd_nm256_writew(chip, base + reg, val);
1242 if (snd_nm256_ac97_ready(chip)) {
1248 snd_printd(
"nm256: ac97 codec not ready..\n");
1270 snd_nm256_ac97_reset(
struct snd_ac97 *ac97)
1275 snd_nm256_writeb(chip, 0x6c0, 1);
1278 snd_nm256_writeb(chip, 0x6cc, 0x87);
1282 snd_nm256_writeb(chip, 0x6cc, 0x80);
1283 snd_nm256_writeb(chip, 0x6cc, 0x0);
1287 for (i = 0; i <
ARRAY_SIZE(nm256_ac97_init_val); i++) {
1291 snd_nm256_ac97_write(ac97, nm256_ac97_init_val[i].reg,
1292 nm256_ac97_init_val[i].
value);
1299 snd_nm256_mixer(
struct nm256 *chip)
1305 .reset = snd_nm256_ac97_reset,
1306 .write = snd_nm256_ac97_write,
1307 .read = snd_nm256_ac97_read,
1318 memset(&ac97, 0,
sizeof(ac97));
1326 if (! (chip->
ac97->id & (0xf0000000))) {
1340 snd_nm256_peek_for_sig(
struct nm256 *chip)
1345 unsigned long pointer_found = chip->
buffer_end - 0x1400;
1361 if (pointer == 0xffffffff ||
1368 pointer_found = pointer;
1380 #ifdef CONFIG_PM_SLEEP
1385 static int nm256_suspend(
struct device *
dev)
1392 snd_pcm_suspend_all(chip->
pcm);
1393 snd_ac97_suspend(chip->
ac97);
1401 static int nm256_resume(
struct device *
dev)
1415 "disabling device\n");
1421 snd_nm256_init_chip(chip);
1424 snd_ac97_resume(chip->
ac97);
1426 for (i = 0; i < 2; i++) {
1430 snd_nm256_set_format(chip, s, s->
substream);
1441 #define NM256_PM_OPS &nm256_pm
1443 #define NM256_PM_OPS NULL
1446 static int snd_nm256_free(
struct nm256 *chip)
1449 snd_nm256_playback_stop(chip);
1451 snd_nm256_capture_stop(chip);
1469 static int snd_nm256_dev_free(
struct snd_device *device)
1472 return snd_nm256_free(chip);
1477 struct nm256 **chip_ret)
1482 .dev_free = snd_nm256_dev_free,
1542 "passing in the module parameter\n");
1545 "cs423x drivers instead.\n");
1556 if (snd_nm256_readb(chip, 0xa0b) != 0)
1561 chip->
interrupt = snd_nm256_interrupt_zx;
1573 if (buffer_top >= chip->
buffer_size && buffer_top < chip->buffer_end)
1577 if ((err = snd_nm256_peek_for_sig(chip)) < 0)
1622 snd_nm256_init_chip(chip);
1635 snd_nm256_free(chip);
1642 static struct snd_pci_quirk nm256_quirks[]
__devinitdata = {
1644 SND_PCI_QUIRK(0x103c, 0x0007,
"HP omnibook 4150",
NM_BLACKLISTED),
1659 const struct snd_pci_quirk *
q;
1661 q = snd_pci_quirk_lookup(pci, nm256_quirks);
1667 "Loading stopped\n");
1670 reset_workaround_2 = 1;
1673 reset_workaround = 1;
1699 buffer_top = 0x25a800;
1701 if (playback_bufsize < 4)
1702 playback_bufsize = 4;
1703 if (playback_bufsize > 128)
1704 playback_bufsize = 128;
1705 if (capture_bufsize < 4)
1706 capture_bufsize = 4;
1707 if (capture_bufsize > 128)
1708 capture_bufsize = 128;
1709 if ((err = snd_nm256_create(card, pci, &chip)) < 0) {
1715 if (reset_workaround) {
1720 if (reset_workaround_2) {
1725 if ((err = snd_nm256_pcm(chip, 0)) < 0 ||
1726 (err = snd_nm256_mixer(chip)) < 0) {
1741 pci_set_drvdata(pci, card);
1748 pci_set_drvdata(pci,
NULL);
1753 .name = KBUILD_MODNAME,
1754 .id_table = snd_nm256_ids,
1755 .probe = snd_nm256_probe,