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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/device.h>#include <linux/signal.h>#include <linux/platform_device.h>#include <linux/clk.h>#include <linux/of_platform.h>#include <linux/of_gpio.h>#include <mach/hardware.h>#include <linux/platform_data/usb-ohci-pxa27x.h>#include <linux/platform_data/usb-pxa3xx-ulpi.h>Go to the source code of this file.
Data Structures | |
| struct | pxa27x_ohci |
Macros | |
| #define | UHCREV (0x0000) /* UHC HCI Spec Revision */ |
| #define | UHCHCON (0x0004) /* UHC Host Control Register */ |
| #define | UHCCOMS (0x0008) /* UHC Command Status Register */ |
| #define | UHCINTS (0x000C) /* UHC Interrupt Status Register */ |
| #define | UHCINTE (0x0010) /* UHC Interrupt Enable */ |
| #define | UHCINTD (0x0014) /* UHC Interrupt Disable */ |
| #define | UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */ |
| #define | UHCPCED (0x001C) /* UHC Period Current Endpt Descr */ |
| #define | UHCCHED (0x0020) /* UHC Control Head Endpt Descr */ |
| #define | UHCCCED (0x0024) /* UHC Control Current Endpt Descr */ |
| #define | UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */ |
| #define | UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */ |
| #define | UHCDHEAD (0x0030) /* UHC Done Head */ |
| #define | UHCFMI (0x0034) /* UHC Frame Interval */ |
| #define | UHCFMR (0x0038) /* UHC Frame Remaining */ |
| #define | UHCFMN (0x003C) /* UHC Frame Number */ |
| #define | UHCPERS (0x0040) /* UHC Periodic Start */ |
| #define | UHCLS (0x0044) /* UHC Low Speed Threshold */ |
| #define | UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */ |
| #define | UHCRHDA_NOCP (1 << 12) /* No over current protection */ |
| #define | UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */ |
| #define | UHCRHDA_POTPGT(x) (((x) & 0xff) << 24) /* Power On To Power Good Time */ |
| #define | UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */ |
| #define | UHCRHS (0x0050) /* UHC Root Hub Status */ |
| #define | UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */ |
| #define | UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */ |
| #define | UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */ |
| #define | UHCSTAT (0x0060) /* UHC Status Register */ |
| #define | UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ |
| #define | UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ |
| #define | UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ |
| #define | UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ |
| #define | UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ |
| #define | UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ |
| #define | UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ |
| #define | UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ |
| #define | UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ |
| #define | UHCHR (0x0064) /* UHC Reset Register */ |
| #define | UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ |
| #define | UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ |
| #define | UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ |
| #define | UHCHR_PCPL (1 << 7) /* Power control polarity low */ |
| #define | UHCHR_PSPL (1 << 6) /* Power sense polarity low */ |
| #define | UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ |
| #define | UHCHR_UIT (1 << 4) /* USB Interrupt Test */ |
| #define | UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ |
| #define | UHCHR_CGR (1 << 2) /* Clock Generation Reset */ |
| #define | UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ |
| #define | UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ |
| #define | UHCHIE (0x0068) /* UHC Interrupt Enable Register*/ |
| #define | UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ |
| #define | UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ |
| #define | UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ |
| #define | UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ |
| #define | UHCHIE_TAIE |
| #define | UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ |
| #define | UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ |
| #define | UHCHIT (0x006C) /* UHC Interrupt Test register */ |
| #define | PXA_UHC_MAX_PORTNUM 3 |
| #define | to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd) |
| #define | pxa27x_clear_otgph() do {} while (0) |
Functions | |
| int | usb_disabled (void) |
| int | usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev) |
| void | usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev) |
| MODULE_ALIAS ("platform:pxa27x-ohci") | |
| #define pxa27x_clear_otgph | ( | void | ) | do {} while (0) |
Definition at line 212 of file ohci-pxa27x.c.
| #define PXA_UHC_MAX_PORTNUM 3 |
Definition at line 101 of file ohci-pxa27x.c.
| #define to_pxa27x_ohci | ( | hcd | ) | (struct pxa27x_ohci *)hcd_to_ohci(hcd) |
Definition at line 112 of file ohci-pxa27x.c.
| #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */ |
Definition at line 46 of file ohci-pxa27x.c.
| #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */ |
Definition at line 45 of file ohci-pxa27x.c.
| #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */ |
Definition at line 44 of file ohci-pxa27x.c.
| #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */ |
Definition at line 43 of file ohci-pxa27x.c.
| #define UHCCOMS (0x0008) /* UHC Command Status Register */ |
Definition at line 37 of file ohci-pxa27x.c.
| #define UHCDHEAD (0x0030) /* UHC Done Head */ |
Definition at line 47 of file ohci-pxa27x.c.
| #define UHCFMI (0x0034) /* UHC Frame Interval */ |
Definition at line 48 of file ohci-pxa27x.c.
| #define UHCFMN (0x003C) /* UHC Frame Number */ |
Definition at line 50 of file ohci-pxa27x.c.
| #define UHCFMR (0x0038) /* UHC Frame Remaining */ |
Definition at line 49 of file ohci-pxa27x.c.
| #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */ |
Definition at line 41 of file ohci-pxa27x.c.
| #define UHCHCON (0x0004) /* UHC Host Control Register */ |
Definition at line 36 of file ohci-pxa27x.c.
| #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/ |
Definition at line 90 of file ohci-pxa27x.c.
| #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ |
Definition at line 96 of file ohci-pxa27x.c.
Definition at line 97 of file ohci-pxa27x.c.
| #define UHCHIE_TAIE |
Definition at line 95 of file ohci-pxa27x.c.
| #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ |
Definition at line 92 of file ohci-pxa27x.c.
Definition at line 94 of file ohci-pxa27x.c.
Definition at line 93 of file ohci-pxa27x.c.
Definition at line 91 of file ohci-pxa27x.c.
| #define UHCHIT (0x006C) /* UHC Interrupt Test register */ |
Definition at line 99 of file ohci-pxa27x.c.
| #define UHCHR (0x0064) /* UHC Reset Register */ |
Definition at line 77 of file ohci-pxa27x.c.
Definition at line 86 of file ohci-pxa27x.c.
| #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ |
Definition at line 87 of file ohci-pxa27x.c.
| #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ |
Definition at line 88 of file ohci-pxa27x.c.
Definition at line 81 of file ohci-pxa27x.c.
Definition at line 82 of file ohci-pxa27x.c.
| #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ |
Definition at line 85 of file ohci-pxa27x.c.
| #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ |
Definition at line 83 of file ohci-pxa27x.c.
| #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ |
Definition at line 80 of file ohci-pxa27x.c.
| #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ |
Definition at line 79 of file ohci-pxa27x.c.
| #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ |
Definition at line 78 of file ohci-pxa27x.c.
| #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ |
Definition at line 84 of file ohci-pxa27x.c.
| #define UHCINTD (0x0014) /* UHC Interrupt Disable */ |
Definition at line 40 of file ohci-pxa27x.c.
| #define UHCINTE (0x0010) /* UHC Interrupt Enable */ |
Definition at line 39 of file ohci-pxa27x.c.
| #define UHCINTS (0x000C) /* UHC Interrupt Status Register */ |
Definition at line 38 of file ohci-pxa27x.c.
| #define UHCLS (0x0044) /* UHC Low Speed Threshold */ |
Definition at line 52 of file ohci-pxa27x.c.
| #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */ |
Definition at line 42 of file ohci-pxa27x.c.
| #define UHCPERS (0x0040) /* UHC Periodic Start */ |
Definition at line 51 of file ohci-pxa27x.c.
| #define UHCREV (0x0000) /* UHC HCI Spec Revision */ |
Definition at line 35 of file ohci-pxa27x.c.
| #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */ |
Definition at line 54 of file ohci-pxa27x.c.
Definition at line 55 of file ohci-pxa27x.c.
| #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */ |
Definition at line 56 of file ohci-pxa27x.c.
Definition at line 57 of file ohci-pxa27x.c.
| #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */ |
Definition at line 60 of file ohci-pxa27x.c.
| #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */ |
Definition at line 62 of file ohci-pxa27x.c.
| #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */ |
Definition at line 63 of file ohci-pxa27x.c.
| #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */ |
Definition at line 64 of file ohci-pxa27x.c.
| #define UHCRHS (0x0050) /* UHC Root Hub Status */ |
Definition at line 61 of file ohci-pxa27x.c.
| #define UHCSTAT (0x0060) /* UHC Status Register */ |
Definition at line 66 of file ohci-pxa27x.c.
| #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ |
Definition at line 74 of file ohci-pxa27x.c.
| #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ |
Definition at line 73 of file ohci-pxa27x.c.
| #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ |
Definition at line 75 of file ohci-pxa27x.c.
| #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ |
Definition at line 68 of file ohci-pxa27x.c.
| #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ |
Definition at line 69 of file ohci-pxa27x.c.
| #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ |
Definition at line 70 of file ohci-pxa27x.c.
Definition at line 72 of file ohci-pxa27x.c.
Definition at line 71 of file ohci-pxa27x.c.
Definition at line 67 of file ohci-pxa27x.c.
| MODULE_ALIAS | ( | "platform:pxa27x-ohci" | ) |
| int usb_hcd_pxa27x_probe | ( | const struct hc_driver * | driver, |
| struct platform_device * | pdev | ||
| ) |
usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs Context: !in_interrupt()
Allocates basic resources for this USB host controller, and then invokes the start() method for the HCD associated with it through the hotplug entry's driver_data.
Definition at line 353 of file ohci-pxa27x.c.
| void usb_hcd_pxa27x_remove | ( | struct usb_hcd * | hcd, |
| struct platform_device * | pdev | ||
| ) |
usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs : USB Host Controller being removed Context: !in_interrupt()
Reverses the effect of usb_hcd_pxa27x_probe(), first invoking the HCD's stop() method. It is always called from a thread context, normally "rmmod", "apmd", or something similar.
Definition at line 459 of file ohci-pxa27x.c.
1.8.2