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parport_ip32.c
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1 /* Low-level parallel port routines for built-in port on SGI IP32
2  *
3  * Author: Arnaud Giersch <[email protected]>
4  *
5  * Based on parport_pc.c by
6  * Phil Blundell, Tim Waugh, Jose Renau, David Campbell,
7  * Andrea Arcangeli, et al.
8  *
9  * Thanks to Ilya A. Volynets-Evenbakh for his help.
10  *
11  * Copyright (C) 2005, 2006 Arnaud Giersch.
12  *
13  * This program is free software; you can redistribute it and/or modify it
14  * under the terms of the GNU General Public License as published by the Free
15  * Software Foundation; either version 2 of the License, or (at your option)
16  * any later version.
17  *
18  * This program is distributed in the hope that it will be useful, but WITHOUT
19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21  * more details.
22  *
23  * You should have received a copy of the GNU General Public License along
24  * with this program; if not, write to the Free Software Foundation, Inc., 59
25  * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26  */
27 
28 /* Current status:
29  *
30  * Basic SPP and PS2 modes are supported.
31  * Support for parallel port IRQ is present.
32  * Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are
33  * supported.
34  * SPP/ECP FIFO can be driven in PIO or DMA mode. PIO mode can work with
35  * or without interrupt support.
36  *
37  * Hardware ECP mode is not fully implemented (ecp_read_data and
38  * ecp_write_addr are actually missing).
39  *
40  * To do:
41  *
42  * Fully implement ECP mode.
43  * EPP and ECP mode need to be tested. I currently do not own any
44  * peripheral supporting these extended mode, and cannot test them.
45  * If DMA mode works well, decide if support for PIO FIFO modes should be
46  * dropped.
47  * Use the io{read,write} family functions when they become available in
48  * the linux-mips.org tree. Note: the MIPS specific functions readsb()
49  * and writesb() are to be translated by ioread8_rep() and iowrite8_rep()
50  * respectively.
51  */
52 
53 /* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an
54  * IEEE 1284 parallel port driven by a Texas Instrument TL16PIR552PH chip[1].
55  * This chip supports SPP, bidirectional, EPP and ECP modes. It has a 16 byte
56  * FIFO buffer and supports DMA transfers.
57  *
58  * [1] http://focus.ti.com/docs/prod/folders/print/tl16pir552.html
59  *
60  * Theoretically, we could simply use the parport_pc module. It is however
61  * not so simple. The parport_pc code assumes that the parallel port
62  * registers are port-mapped. On the O2, they are memory-mapped.
63  * Furthermore, each register is replicated on 256 consecutive addresses (as
64  * it is for the built-in serial ports on the same chip).
65  */
66 
67 /*--- Some configuration defines ---------------------------------------*/
68 
69 /* DEBUG_PARPORT_IP32
70  * 0 disable debug
71  * 1 standard level: pr_debug1 is enabled
72  * 2 parport_ip32_dump_state is enabled
73  * >=3 verbose level: pr_debug is enabled
74  */
75 #if !defined(DEBUG_PARPORT_IP32)
76 # define DEBUG_PARPORT_IP32 0 /* 0 (disabled) for production */
77 #endif
78 
79 /*----------------------------------------------------------------------*/
80 
81 /* Setup DEBUG macros. This is done before any includes, just in case we
82  * activate pr_debug() with DEBUG_PARPORT_IP32 >= 3.
83  */
84 #if DEBUG_PARPORT_IP32 == 1
85 # warning DEBUG_PARPORT_IP32 == 1
86 #elif DEBUG_PARPORT_IP32 == 2
87 # warning DEBUG_PARPORT_IP32 == 2
88 #elif DEBUG_PARPORT_IP32 >= 3
89 # warning DEBUG_PARPORT_IP32 >= 3
90 # if !defined(DEBUG)
91 # define DEBUG /* enable pr_debug() in kernel.h */
92 # endif
93 #endif
94 
95 #include <linux/completion.h>
96 #include <linux/delay.h>
97 #include <linux/dma-mapping.h>
98 #include <linux/err.h>
99 #include <linux/init.h>
100 #include <linux/interrupt.h>
101 #include <linux/jiffies.h>
102 #include <linux/kernel.h>
103 #include <linux/module.h>
104 #include <linux/parport.h>
105 #include <linux/sched.h>
106 #include <linux/slab.h>
107 #include <linux/spinlock.h>
108 #include <linux/stddef.h>
109 #include <linux/types.h>
110 #include <asm/io.h>
111 #include <asm/ip32/ip32_ints.h>
112 #include <asm/ip32/mace.h>
113 
114 /*--- Global variables -------------------------------------------------*/
115 
116 /* Verbose probing on by default for debugging. */
117 #if DEBUG_PARPORT_IP32 >= 1
118 # define DEFAULT_VERBOSE_PROBING 1
119 #else
120 # define DEFAULT_VERBOSE_PROBING 0
121 #endif
122 
123 /* Default prefix for printk */
124 #define PPIP32 "parport_ip32: "
125 
126 /*
127  * These are the module parameters:
128  * @features: bit mask of features to enable/disable
129  * (all enabled by default)
130  * @verbose_probing: log chit-chat during initialization
131  */
132 #define PARPORT_IP32_ENABLE_IRQ (1U << 0)
133 #define PARPORT_IP32_ENABLE_DMA (1U << 1)
134 #define PARPORT_IP32_ENABLE_SPP (1U << 2)
135 #define PARPORT_IP32_ENABLE_EPP (1U << 3)
136 #define PARPORT_IP32_ENABLE_ECP (1U << 4)
137 static unsigned int features = ~0U;
138 static bool verbose_probing = DEFAULT_VERBOSE_PROBING;
139 
140 /* We do not support more than one port. */
141 static struct parport *this_port = NULL;
142 
143 /* Timing constants for FIFO modes. */
144 #define FIFO_NFAULT_TIMEOUT 100 /* milliseconds */
145 #define FIFO_POLLING_INTERVAL 50 /* microseconds */
146 
147 /*--- I/O register definitions -----------------------------------------*/
148 
168 struct parport_ip32_regs {
169  void __iomem *data;
170  void __iomem *dsr;
171  void __iomem *dcr;
172  void __iomem *eppAddr;
173  void __iomem *eppData0;
174  void __iomem *eppData1;
175  void __iomem *eppData2;
176  void __iomem *eppData3;
177  void __iomem *ecpAFifo;
178  void __iomem *fifo;
179  void __iomem *cnfgA;
180  void __iomem *cnfgB;
181  void __iomem *ecr;
182 };
183 
184 /* Device Status Register */
185 #define DSR_nBUSY (1U << 7) /* PARPORT_STATUS_BUSY */
186 #define DSR_nACK (1U << 6) /* PARPORT_STATUS_ACK */
187 #define DSR_PERROR (1U << 5) /* PARPORT_STATUS_PAPEROUT */
188 #define DSR_SELECT (1U << 4) /* PARPORT_STATUS_SELECT */
189 #define DSR_nFAULT (1U << 3) /* PARPORT_STATUS_ERROR */
190 #define DSR_nPRINT (1U << 2) /* specific to TL16PIR552 */
191 /* #define DSR_reserved (1U << 1) */
192 #define DSR_TIMEOUT (1U << 0) /* EPP timeout */
193 
194 /* Device Control Register */
195 /* #define DCR_reserved (1U << 7) | (1U << 6) */
196 #define DCR_DIR (1U << 5) /* direction */
197 #define DCR_IRQ (1U << 4) /* interrupt on nAck */
198 #define DCR_SELECT (1U << 3) /* PARPORT_CONTROL_SELECT */
199 #define DCR_nINIT (1U << 2) /* PARPORT_CONTROL_INIT */
200 #define DCR_AUTOFD (1U << 1) /* PARPORT_CONTROL_AUTOFD */
201 #define DCR_STROBE (1U << 0) /* PARPORT_CONTROL_STROBE */
202 
203 /* ECP Configuration Register A */
204 #define CNFGA_IRQ (1U << 7)
205 #define CNFGA_ID_MASK ((1U << 6) | (1U << 5) | (1U << 4))
206 #define CNFGA_ID_SHIFT 4
207 #define CNFGA_ID_16 (00U << CNFGA_ID_SHIFT)
208 #define CNFGA_ID_8 (01U << CNFGA_ID_SHIFT)
209 #define CNFGA_ID_32 (02U << CNFGA_ID_SHIFT)
210 /* #define CNFGA_reserved (1U << 3) */
211 #define CNFGA_nBYTEINTRANS (1U << 2)
212 #define CNFGA_PWORDLEFT ((1U << 1) | (1U << 0))
213 
214 /* ECP Configuration Register B */
215 #define CNFGB_COMPRESS (1U << 7)
216 #define CNFGB_INTRVAL (1U << 6)
217 #define CNFGB_IRQ_MASK ((1U << 5) | (1U << 4) | (1U << 3))
218 #define CNFGB_IRQ_SHIFT 3
219 #define CNFGB_DMA_MASK ((1U << 2) | (1U << 1) | (1U << 0))
220 #define CNFGB_DMA_SHIFT 0
221 
222 /* Extended Control Register */
223 #define ECR_MODE_MASK ((1U << 7) | (1U << 6) | (1U << 5))
224 #define ECR_MODE_SHIFT 5
225 #define ECR_MODE_SPP (00U << ECR_MODE_SHIFT)
226 #define ECR_MODE_PS2 (01U << ECR_MODE_SHIFT)
227 #define ECR_MODE_PPF (02U << ECR_MODE_SHIFT)
228 #define ECR_MODE_ECP (03U << ECR_MODE_SHIFT)
229 #define ECR_MODE_EPP (04U << ECR_MODE_SHIFT)
230 /* #define ECR_MODE_reserved (05U << ECR_MODE_SHIFT) */
231 #define ECR_MODE_TST (06U << ECR_MODE_SHIFT)
232 #define ECR_MODE_CFG (07U << ECR_MODE_SHIFT)
233 #define ECR_nERRINTR (1U << 4)
234 #define ECR_DMAEN (1U << 3)
235 #define ECR_SERVINTR (1U << 2)
236 #define ECR_F_FULL (1U << 1)
237 #define ECR_F_EMPTY (1U << 0)
238 
239 /*--- Private data -----------------------------------------------------*/
240 
246 enum parport_ip32_irq_mode { PARPORT_IP32_IRQ_FWD, PARPORT_IP32_IRQ_HERE };
247 
262 struct parport_ip32_private {
263  struct parport_ip32_regs regs;
264  unsigned int dcr_cache;
265  unsigned int dcr_writable;
266  unsigned int pword;
267  unsigned int fifo_depth;
268  unsigned int readIntrThreshold;
269  unsigned int writeIntrThreshold;
270  enum parport_ip32_irq_mode irq_mode;
271  struct completion irq_complete;
272 };
273 
274 /*--- Debug code -------------------------------------------------------*/
275 
276 /*
277  * pr_debug1 - print debug messages
278  *
279  * This is like pr_debug(), but is defined for %DEBUG_PARPORT_IP32 >= 1
280  */
281 #if DEBUG_PARPORT_IP32 >= 1
282 # define pr_debug1(...) printk(KERN_DEBUG __VA_ARGS__)
283 #else /* DEBUG_PARPORT_IP32 < 1 */
284 # define pr_debug1(...) do { } while (0)
285 #endif
286 
287 /*
288  * pr_trace, pr_trace1 - trace function calls
289  * @p: pointer to &struct parport
290  * @fmt: printk format string
291  * @...: parameters for format string
292  *
293  * Macros used to trace function calls. The given string is formatted after
294  * function name. pr_trace() uses pr_debug(), and pr_trace1() uses
295  * pr_debug1(). __pr_trace() is the low-level macro and is not to be used
296  * directly.
297  */
298 #define __pr_trace(pr, p, fmt, ...) \
299  pr("%s: %s" fmt "\n", \
300  ({ const struct parport *__p = (p); \
301  __p ? __p->name : "parport_ip32"; }), \
302  __func__ , ##__VA_ARGS__)
303 #define pr_trace(p, fmt, ...) __pr_trace(pr_debug, p, fmt , ##__VA_ARGS__)
304 #define pr_trace1(p, fmt, ...) __pr_trace(pr_debug1, p, fmt , ##__VA_ARGS__)
305 
306 /*
307  * __pr_probe, pr_probe - print message if @verbose_probing is true
308  * @p: pointer to &struct parport
309  * @fmt: printk format string
310  * @...: parameters for format string
311  *
312  * For new lines, use pr_probe(). Use __pr_probe() for continued lines.
313  */
314 #define __pr_probe(...) \
315  do { if (verbose_probing) printk(__VA_ARGS__); } while (0)
316 #define pr_probe(p, fmt, ...) \
317  __pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__)
318 
319 /*
320  * parport_ip32_dump_state - print register status of parport
321  * @p: pointer to &struct parport
322  * @str: string to add in message
323  * @show_ecp_config: shall we dump ECP configuration registers too?
324  *
325  * This function is only here for debugging purpose, and should be used with
326  * care. Reading the parallel port registers may have undesired side effects.
327  * Especially if @show_ecp_config is true, the parallel port is resetted.
328  * This function is only defined if %DEBUG_PARPORT_IP32 >= 2.
329  */
330 #if DEBUG_PARPORT_IP32 >= 2
331 static void parport_ip32_dump_state(struct parport *p, char *str,
332  unsigned int show_ecp_config)
333 {
334  struct parport_ip32_private * const priv = p->physport->private_data;
335  unsigned int i;
336 
337  printk(KERN_DEBUG PPIP32 "%s: state (%s):\n", p->name, str);
338  {
339  static const char ecr_modes[8][4] = {"SPP", "PS2", "PPF",
340  "ECP", "EPP", "???",
341  "TST", "CFG"};
342  unsigned int ecr = readb(priv->regs.ecr);
343  printk(KERN_DEBUG PPIP32 " ecr=0x%02x", ecr);
344  printk(" %s",
345  ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]);
346  if (ecr & ECR_nERRINTR)
347  printk(",nErrIntrEn");
348  if (ecr & ECR_DMAEN)
349  printk(",dmaEn");
350  if (ecr & ECR_SERVINTR)
351  printk(",serviceIntr");
352  if (ecr & ECR_F_FULL)
353  printk(",f_full");
354  if (ecr & ECR_F_EMPTY)
355  printk(",f_empty");
356  printk("\n");
357  }
358  if (show_ecp_config) {
359  unsigned int oecr, cnfgA, cnfgB;
360  oecr = readb(priv->regs.ecr);
361  writeb(ECR_MODE_PS2, priv->regs.ecr);
362  writeb(ECR_MODE_CFG, priv->regs.ecr);
363  cnfgA = readb(priv->regs.cnfgA);
364  cnfgB = readb(priv->regs.cnfgB);
365  writeb(ECR_MODE_PS2, priv->regs.ecr);
366  writeb(oecr, priv->regs.ecr);
367  printk(KERN_DEBUG PPIP32 " cnfgA=0x%02x", cnfgA);
368  printk(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses");
369  switch (cnfgA & CNFGA_ID_MASK) {
370  case CNFGA_ID_8:
371  printk(",8 bits");
372  break;
373  case CNFGA_ID_16:
374  printk(",16 bits");
375  break;
376  case CNFGA_ID_32:
377  printk(",32 bits");
378  break;
379  default:
380  printk(",unknown ID");
381  break;
382  }
383  if (!(cnfgA & CNFGA_nBYTEINTRANS))
384  printk(",ByteInTrans");
385  if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8)
386  printk(",%d byte%s left", cnfgA & CNFGA_PWORDLEFT,
387  ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : "");
388  printk("\n");
389  printk(KERN_DEBUG PPIP32 " cnfgB=0x%02x", cnfgB);
390  printk(" irq=%u,dma=%u",
391  (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT,
392  (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT);
393  printk(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL));
394  if (cnfgB & CNFGB_COMPRESS)
395  printk(",compress");
396  printk("\n");
397  }
398  for (i = 0; i < 2; i++) {
399  unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr);
400  printk(KERN_DEBUG PPIP32 " dcr(%s)=0x%02x",
401  i ? "soft" : "hard", dcr);
402  printk(" %s", (dcr & DCR_DIR) ? "rev" : "fwd");
403  if (dcr & DCR_IRQ)
404  printk(",ackIntEn");
405  if (!(dcr & DCR_SELECT))
406  printk(",nSelectIn");
407  if (dcr & DCR_nINIT)
408  printk(",nInit");
409  if (!(dcr & DCR_AUTOFD))
410  printk(",nAutoFD");
411  if (!(dcr & DCR_STROBE))
412  printk(",nStrobe");
413  printk("\n");
414  }
415 #define sep (f++ ? ',' : ' ')
416  {
417  unsigned int f = 0;
418  unsigned int dsr = readb(priv->regs.dsr);
419  printk(KERN_DEBUG PPIP32 " dsr=0x%02x", dsr);
420  if (!(dsr & DSR_nBUSY))
421  printk("%cBusy", sep);
422  if (dsr & DSR_nACK)
423  printk("%cnAck", sep);
424  if (dsr & DSR_PERROR)
425  printk("%cPError", sep);
426  if (dsr & DSR_SELECT)
427  printk("%cSelect", sep);
428  if (dsr & DSR_nFAULT)
429  printk("%cnFault", sep);
430  if (!(dsr & DSR_nPRINT))
431  printk("%c(Print)", sep);
432  if (dsr & DSR_TIMEOUT)
433  printk("%cTimeout", sep);
434  printk("\n");
435  }
436 #undef sep
437 }
438 #else /* DEBUG_PARPORT_IP32 < 2 */
439 #define parport_ip32_dump_state(...) do { } while (0)
440 #endif
441 
442 /*
443  * CHECK_EXTRA_BITS - track and log extra bits
444  * @p: pointer to &struct parport
445  * @b: byte to inspect
446  * @m: bit mask of authorized bits
447  *
448  * This is used to track and log extra bits that should not be there in
449  * parport_ip32_write_control() and parport_ip32_frob_control(). It is only
450  * defined if %DEBUG_PARPORT_IP32 >= 1.
451  */
452 #if DEBUG_PARPORT_IP32 >= 1
453 #define CHECK_EXTRA_BITS(p, b, m) \
454  do { \
455  unsigned int __b = (b), __m = (m); \
456  if (__b & ~__m) \
457  pr_debug1(PPIP32 "%s: extra bits in %s(%s): " \
458  "0x%02x/0x%02x\n", \
459  (p)->name, __func__, #b, __b, __m); \
460  } while (0)
461 #else /* DEBUG_PARPORT_IP32 < 1 */
462 #define CHECK_EXTRA_BITS(...) do { } while (0)
463 #endif
464 
465 /*--- IP32 parallel port DMA operations --------------------------------*/
466 
478 struct parport_ip32_dma_data {
479  enum dma_data_direction dir;
480  dma_addr_t buf;
481  dma_addr_t next;
482  size_t len;
483  size_t left;
484  unsigned int ctx;
485  unsigned int irq_on;
486  spinlock_t lock;
487 };
488 static struct parport_ip32_dma_data parport_ip32_dma;
489 
497 static void parport_ip32_dma_setup_context(unsigned int limit)
498 {
499  unsigned long flags;
500 
501  spin_lock_irqsave(&parport_ip32_dma.lock, flags);
502  if (parport_ip32_dma.left > 0) {
503  /* Note: ctxreg is "volatile" here only because
504  * mace->perif.ctrl.parport.context_a and context_b are
505  * "volatile". */
506  volatile u64 __iomem *ctxreg = (parport_ip32_dma.ctx == 0) ?
507  &mace->perif.ctrl.parport.context_a :
508  &mace->perif.ctrl.parport.context_b;
509  u64 count;
510  u64 ctxval;
511  if (parport_ip32_dma.left <= limit) {
512  count = parport_ip32_dma.left;
513  ctxval = MACEPAR_CONTEXT_LASTFLAG;
514  } else {
515  count = limit;
516  ctxval = 0;
517  }
518 
519  pr_trace(NULL,
520  "(%u): 0x%04x:0x%04x, %u -> %u%s",
521  limit,
522  (unsigned int)parport_ip32_dma.buf,
523  (unsigned int)parport_ip32_dma.next,
524  (unsigned int)count,
525  parport_ip32_dma.ctx, ctxval ? "*" : "");
526 
527  ctxval |= parport_ip32_dma.next &
528  MACEPAR_CONTEXT_BASEADDR_MASK;
529  ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) &
530  MACEPAR_CONTEXT_DATALEN_MASK;
531  writeq(ctxval, ctxreg);
532  parport_ip32_dma.next += count;
533  parport_ip32_dma.left -= count;
534  parport_ip32_dma.ctx ^= 1U;
535  }
536  /* If there is nothing more to send, disable IRQs to avoid to
537  * face an IRQ storm which can lock the machine. Disable them
538  * only once. */
539  if (parport_ip32_dma.left == 0 && parport_ip32_dma.irq_on) {
540  pr_debug(PPIP32 "IRQ off (ctx)\n");
541  disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
542  disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
543  parport_ip32_dma.irq_on = 0;
544  }
545  spin_unlock_irqrestore(&parport_ip32_dma.lock, flags);
546 }
547 
553 static irqreturn_t parport_ip32_dma_interrupt(int irq, void *dev_id)
554 {
555  if (parport_ip32_dma.left)
556  pr_trace(NULL, "(%d): ctx=%d", irq, parport_ip32_dma.ctx);
557  parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
558  return IRQ_HANDLED;
559 }
560 
561 #if DEBUG_PARPORT_IP32
562 static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id)
563 {
564  pr_trace1(NULL, "(%d)", irq);
565  return IRQ_HANDLED;
566 }
567 #endif
568 
578 static int parport_ip32_dma_start(enum dma_data_direction dir,
579  void *addr, size_t count)
580 {
581  unsigned int limit;
582  u64 ctrl;
583 
584  pr_trace(NULL, "(%d, %lu)", dir, (unsigned long)count);
585 
586  /* FIXME - add support for DMA_FROM_DEVICE. In this case, buffer must
587  * be 64 bytes aligned. */
588  BUG_ON(dir != DMA_TO_DEVICE);
589 
590  /* Reset DMA controller */
591  ctrl = MACEPAR_CTLSTAT_RESET;
592  writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
593 
594  /* DMA IRQs should normally be enabled */
595  if (!parport_ip32_dma.irq_on) {
596  WARN_ON(1);
597  enable_irq(MACEISA_PAR_CTXA_IRQ);
598  enable_irq(MACEISA_PAR_CTXB_IRQ);
599  parport_ip32_dma.irq_on = 1;
600  }
601 
602  /* Prepare DMA pointers */
603  parport_ip32_dma.dir = dir;
604  parport_ip32_dma.buf = dma_map_single(NULL, addr, count, dir);
605  parport_ip32_dma.len = count;
606  parport_ip32_dma.next = parport_ip32_dma.buf;
607  parport_ip32_dma.left = parport_ip32_dma.len;
608  parport_ip32_dma.ctx = 0;
609 
610  /* Setup DMA direction and first two contexts */
611  ctrl = (dir == DMA_TO_DEVICE) ? 0 : MACEPAR_CTLSTAT_DIRECTION;
612  writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
613  /* Single transfer should not cross a 4K page boundary */
614  limit = MACEPAR_CONTEXT_DATA_BOUND -
615  (parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1));
616  parport_ip32_dma_setup_context(limit);
617  parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
618 
619  /* Real start of DMA transfer */
620  ctrl |= MACEPAR_CTLSTAT_ENABLE;
621  writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
622 
623  return 0;
624 }
625 
632 static void parport_ip32_dma_stop(void)
633 {
634  u64 ctx_a;
635  u64 ctx_b;
636  u64 ctrl;
637  u64 diag;
638  size_t res[2]; /* {[0] = res_a, [1] = res_b} */
639 
640  pr_trace(NULL, "()");
641 
642  /* Disable IRQs */
643  spin_lock_irq(&parport_ip32_dma.lock);
644  if (parport_ip32_dma.irq_on) {
645  pr_debug(PPIP32 "IRQ off (stop)\n");
646  disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
647  disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
648  parport_ip32_dma.irq_on = 0;
649  }
650  spin_unlock_irq(&parport_ip32_dma.lock);
651  /* Force IRQ synchronization, even if the IRQs were disabled
652  * elsewhere. */
653  synchronize_irq(MACEISA_PAR_CTXA_IRQ);
654  synchronize_irq(MACEISA_PAR_CTXB_IRQ);
655 
656  /* Stop DMA transfer */
657  ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
658  ctrl &= ~MACEPAR_CTLSTAT_ENABLE;
659  writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
660 
661  /* Adjust residue (parport_ip32_dma.left) */
662  ctx_a = readq(&mace->perif.ctrl.parport.context_a);
663  ctx_b = readq(&mace->perif.ctrl.parport.context_b);
664  ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
665  diag = readq(&mace->perif.ctrl.parport.diagnostic);
666  res[0] = (ctrl & MACEPAR_CTLSTAT_CTXA_VALID) ?
667  1 + ((ctx_a & MACEPAR_CONTEXT_DATALEN_MASK) >>
668  MACEPAR_CONTEXT_DATALEN_SHIFT) :
669  0;
670  res[1] = (ctrl & MACEPAR_CTLSTAT_CTXB_VALID) ?
671  1 + ((ctx_b & MACEPAR_CONTEXT_DATALEN_MASK) >>
672  MACEPAR_CONTEXT_DATALEN_SHIFT) :
673  0;
674  if (diag & MACEPAR_DIAG_DMACTIVE)
675  res[(diag & MACEPAR_DIAG_CTXINUSE) != 0] =
676  1 + ((diag & MACEPAR_DIAG_CTRMASK) >>
677  MACEPAR_DIAG_CTRSHIFT);
678  parport_ip32_dma.left += res[0] + res[1];
679 
680  /* Reset DMA controller, and re-enable IRQs */
681  ctrl = MACEPAR_CTLSTAT_RESET;
682  writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
683  pr_debug(PPIP32 "IRQ on (stop)\n");
684  enable_irq(MACEISA_PAR_CTXA_IRQ);
685  enable_irq(MACEISA_PAR_CTXB_IRQ);
686  parport_ip32_dma.irq_on = 1;
687 
688  dma_unmap_single(NULL, parport_ip32_dma.buf, parport_ip32_dma.len,
689  parport_ip32_dma.dir);
690 }
691 
697 static inline size_t parport_ip32_dma_get_residue(void)
698 {
699  return parport_ip32_dma.left;
700 }
701 
707 static int parport_ip32_dma_register(void)
708 {
709  int err;
710 
711  spin_lock_init(&parport_ip32_dma.lock);
712  parport_ip32_dma.irq_on = 1;
713 
714  /* Reset DMA controller */
715  writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat);
716 
717  /* Request IRQs */
718  err = request_irq(MACEISA_PAR_CTXA_IRQ, parport_ip32_dma_interrupt,
719  0, "parport_ip32", NULL);
720  if (err)
721  goto fail_a;
722  err = request_irq(MACEISA_PAR_CTXB_IRQ, parport_ip32_dma_interrupt,
723  0, "parport_ip32", NULL);
724  if (err)
725  goto fail_b;
726 #if DEBUG_PARPORT_IP32
727  /* FIXME - what is this IRQ for? */
728  err = request_irq(MACEISA_PAR_MERR_IRQ, parport_ip32_merr_interrupt,
729  0, "parport_ip32", NULL);
730  if (err)
731  goto fail_merr;
732 #endif
733  return 0;
734 
735 #if DEBUG_PARPORT_IP32
736 fail_merr:
737  free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
738 #endif
739 fail_b:
740  free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
741 fail_a:
742  return err;
743 }
744 
748 static void parport_ip32_dma_unregister(void)
749 {
750 #if DEBUG_PARPORT_IP32
751  free_irq(MACEISA_PAR_MERR_IRQ, NULL);
752 #endif
753  free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
754  free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
755 }
756 
757 /*--- Interrupt handlers and associates --------------------------------*/
758 
763 static inline void parport_ip32_wakeup(struct parport *p)
764 {
765  struct parport_ip32_private * const priv = p->physport->private_data;
766  complete(&priv->irq_complete);
767 }
768 
777 static irqreturn_t parport_ip32_interrupt(int irq, void *dev_id)
778 {
779  struct parport * const p = dev_id;
780  struct parport_ip32_private * const priv = p->physport->private_data;
781  enum parport_ip32_irq_mode irq_mode = priv->irq_mode;
782 
783  switch (irq_mode) {
784  case PARPORT_IP32_IRQ_FWD:
785  return parport_irq_handler(irq, dev_id);
786 
787  case PARPORT_IP32_IRQ_HERE:
788  parport_ip32_wakeup(p);
789  break;
790  }
791 
792  return IRQ_HANDLED;
793 }
794 
795 /*--- Some utility function to manipulate ECR register -----------------*/
796 
801 static inline unsigned int parport_ip32_read_econtrol(struct parport *p)
802 {
803  struct parport_ip32_private * const priv = p->physport->private_data;
804  return readb(priv->regs.ecr);
805 }
806 
812 static inline void parport_ip32_write_econtrol(struct parport *p,
813  unsigned int c)
814 {
815  struct parport_ip32_private * const priv = p->physport->private_data;
816  writeb(c, priv->regs.ecr);
817 }
818 
828 static inline void parport_ip32_frob_econtrol(struct parport *p,
829  unsigned int mask,
830  unsigned int val)
831 {
832  unsigned int c;
833  c = (parport_ip32_read_econtrol(p) & ~mask) ^ val;
834  parport_ip32_write_econtrol(p, c);
835 }
836 
845 static void parport_ip32_set_mode(struct parport *p, unsigned int mode)
846 {
847  unsigned int omode;
848 
849  mode &= ECR_MODE_MASK;
850  omode = parport_ip32_read_econtrol(p) & ECR_MODE_MASK;
851 
852  if (!(mode == ECR_MODE_SPP || mode == ECR_MODE_PS2
853  || omode == ECR_MODE_SPP || omode == ECR_MODE_PS2)) {
854  /* We have to go through PS2 mode */
855  unsigned int ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
856  parport_ip32_write_econtrol(p, ecr);
857  }
858  parport_ip32_write_econtrol(p, mode | ECR_nERRINTR | ECR_SERVINTR);
859 }
860 
861 /*--- Basic functions needed for parport -------------------------------*/
862 
867 static inline unsigned char parport_ip32_read_data(struct parport *p)
868 {
869  struct parport_ip32_private * const priv = p->physport->private_data;
870  return readb(priv->regs.data);
871 }
872 
878 static inline void parport_ip32_write_data(struct parport *p, unsigned char d)
879 {
880  struct parport_ip32_private * const priv = p->physport->private_data;
881  writeb(d, priv->regs.data);
882 }
883 
888 static inline unsigned char parport_ip32_read_status(struct parport *p)
889 {
890  struct parport_ip32_private * const priv = p->physport->private_data;
891  return readb(priv->regs.dsr);
892 }
893 
898 static inline unsigned int __parport_ip32_read_control(struct parport *p)
899 {
900  struct parport_ip32_private * const priv = p->physport->private_data;
901  return priv->dcr_cache; /* use soft copy */
902 }
903 
909 static inline void __parport_ip32_write_control(struct parport *p,
910  unsigned int c)
911 {
912  struct parport_ip32_private * const priv = p->physport->private_data;
913  CHECK_EXTRA_BITS(p, c, priv->dcr_writable);
914  c &= priv->dcr_writable; /* only writable bits */
915  writeb(c, priv->regs.dcr);
916  priv->dcr_cache = c; /* update soft copy */
917 }
918 
929 static inline void __parport_ip32_frob_control(struct parport *p,
930  unsigned int mask,
931  unsigned int val)
932 {
933  unsigned int c;
934  c = (__parport_ip32_read_control(p) & ~mask) ^ val;
935  __parport_ip32_write_control(p, c);
936 }
937 
945 static inline unsigned char parport_ip32_read_control(struct parport *p)
946 {
947  const unsigned int rm =
948  DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
949  return __parport_ip32_read_control(p) & rm;
950 }
951 
960 static inline void parport_ip32_write_control(struct parport *p,
961  unsigned char c)
962 {
963  const unsigned int wm =
964  DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
965  CHECK_EXTRA_BITS(p, c, wm);
966  __parport_ip32_frob_control(p, wm, c & wm);
967 }
968 
978 static inline unsigned char parport_ip32_frob_control(struct parport *p,
979  unsigned char mask,
980  unsigned char val)
981 {
982  const unsigned int wm =
983  DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
984  CHECK_EXTRA_BITS(p, mask, wm);
985  CHECK_EXTRA_BITS(p, val, wm);
986  __parport_ip32_frob_control(p, mask & wm, val & wm);
987  return parport_ip32_read_control(p);
988 }
989 
994 static inline void parport_ip32_disable_irq(struct parport *p)
995 {
996  __parport_ip32_frob_control(p, DCR_IRQ, 0);
997 }
998 
1003 static inline void parport_ip32_enable_irq(struct parport *p)
1004 {
1005  __parport_ip32_frob_control(p, DCR_IRQ, DCR_IRQ);
1006 }
1007 
1014 static inline void parport_ip32_data_forward(struct parport *p)
1015 {
1016  __parport_ip32_frob_control(p, DCR_DIR, 0);
1017 }
1018 
1026 static inline void parport_ip32_data_reverse(struct parport *p)
1027 {
1028  __parport_ip32_frob_control(p, DCR_DIR, DCR_DIR);
1029 }
1030 
1036 static void parport_ip32_init_state(struct pardevice *dev,
1037  struct parport_state *s)
1038 {
1039  s->u.ip32.dcr = DCR_SELECT | DCR_nINIT;
1040  s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
1041 }
1042 
1048 static void parport_ip32_save_state(struct parport *p,
1049  struct parport_state *s)
1050 {
1051  s->u.ip32.dcr = __parport_ip32_read_control(p);
1052  s->u.ip32.ecr = parport_ip32_read_econtrol(p);
1053 }
1054 
1060 static void parport_ip32_restore_state(struct parport *p,
1061  struct parport_state *s)
1062 {
1063  parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK);
1064  parport_ip32_write_econtrol(p, s->u.ip32.ecr);
1065  __parport_ip32_write_control(p, s->u.ip32.dcr);
1066 }
1067 
1068 /*--- EPP mode functions -----------------------------------------------*/
1069 
1076 static unsigned int parport_ip32_clear_epp_timeout(struct parport *p)
1077 {
1078  struct parport_ip32_private * const priv = p->physport->private_data;
1079  unsigned int cleared;
1080 
1081  if (!(parport_ip32_read_status(p) & DSR_TIMEOUT))
1082  cleared = 1;
1083  else {
1084  unsigned int r;
1085  /* To clear timeout some chips require double read */
1086  parport_ip32_read_status(p);
1087  r = parport_ip32_read_status(p);
1088  /* Some reset by writing 1 */
1089  writeb(r | DSR_TIMEOUT, priv->regs.dsr);
1090  /* Others by writing 0 */
1091  writeb(r & ~DSR_TIMEOUT, priv->regs.dsr);
1092 
1093  r = parport_ip32_read_status(p);
1094  cleared = !(r & DSR_TIMEOUT);
1095  }
1096 
1097  pr_trace(p, "(): %s", cleared ? "cleared" : "failed");
1098  return cleared;
1099 }
1100 
1109 static size_t parport_ip32_epp_read(void __iomem *eppreg,
1110  struct parport *p, void *buf,
1111  size_t len, int flags)
1112 {
1113  struct parport_ip32_private * const priv = p->physport->private_data;
1114  size_t got;
1115  parport_ip32_set_mode(p, ECR_MODE_EPP);
1116  parport_ip32_data_reverse(p);
1117  parport_ip32_write_control(p, DCR_nINIT);
1118  if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
1119  readsb(eppreg, buf, len);
1120  if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1121  parport_ip32_clear_epp_timeout(p);
1122  return -EIO;
1123  }
1124  got = len;
1125  } else {
1126  u8 *bufp = buf;
1127  for (got = 0; got < len; got++) {
1128  *bufp++ = readb(eppreg);
1129  if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1130  parport_ip32_clear_epp_timeout(p);
1131  break;
1132  }
1133  }
1134  }
1135  parport_ip32_data_forward(p);
1136  parport_ip32_set_mode(p, ECR_MODE_PS2);
1137  return got;
1138 }
1139 
1148 static size_t parport_ip32_epp_write(void __iomem *eppreg,
1149  struct parport *p, const void *buf,
1150  size_t len, int flags)
1151 {
1152  struct parport_ip32_private * const priv = p->physport->private_data;
1153  size_t written;
1154  parport_ip32_set_mode(p, ECR_MODE_EPP);
1155  parport_ip32_data_forward(p);
1156  parport_ip32_write_control(p, DCR_nINIT);
1157  if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
1158  writesb(eppreg, buf, len);
1159  if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1160  parport_ip32_clear_epp_timeout(p);
1161  return -EIO;
1162  }
1163  written = len;
1164  } else {
1165  const u8 *bufp = buf;
1166  for (written = 0; written < len; written++) {
1167  writeb(*bufp++, eppreg);
1168  if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1169  parport_ip32_clear_epp_timeout(p);
1170  break;
1171  }
1172  }
1173  }
1174  parport_ip32_set_mode(p, ECR_MODE_PS2);
1175  return written;
1176 }
1177 
1185 static size_t parport_ip32_epp_read_data(struct parport *p, void *buf,
1186  size_t len, int flags)
1187 {
1188  struct parport_ip32_private * const priv = p->physport->private_data;
1189  return parport_ip32_epp_read(priv->regs.eppData0, p, buf, len, flags);
1190 }
1191 
1199 static size_t parport_ip32_epp_write_data(struct parport *p, const void *buf,
1200  size_t len, int flags)
1201 {
1202  struct parport_ip32_private * const priv = p->physport->private_data;
1203  return parport_ip32_epp_write(priv->regs.eppData0, p, buf, len, flags);
1204 }
1205 
1213 static size_t parport_ip32_epp_read_addr(struct parport *p, void *buf,
1214  size_t len, int flags)
1215 {
1216  struct parport_ip32_private * const priv = p->physport->private_data;
1217  return parport_ip32_epp_read(priv->regs.eppAddr, p, buf, len, flags);
1218 }
1219 
1227 static size_t parport_ip32_epp_write_addr(struct parport *p, const void *buf,
1228  size_t len, int flags)
1229 {
1230  struct parport_ip32_private * const priv = p->physport->private_data;
1231  return parport_ip32_epp_write(priv->regs.eppAddr, p, buf, len, flags);
1232 }
1233 
1234 /*--- ECP mode functions (FIFO) ----------------------------------------*/
1235 
1248 static unsigned int parport_ip32_fifo_wait_break(struct parport *p,
1249  unsigned long expire)
1250 {
1251  cond_resched();
1252  if (time_after(jiffies, expire)) {
1253  pr_debug1(PPIP32 "%s: FIFO write timed out\n", p->name);
1254  return 1;
1255  }
1256  if (signal_pending(current)) {
1257  pr_debug1(PPIP32 "%s: Signal pending\n", p->name);
1258  return 1;
1259  }
1260  if (!(parport_ip32_read_status(p) & DSR_nFAULT)) {
1261  pr_debug1(PPIP32 "%s: nFault asserted low\n", p->name);
1262  return 1;
1263  }
1264  return 0;
1265 }
1266 
1275 static unsigned int parport_ip32_fwp_wait_polling(struct parport *p)
1276 {
1277  struct parport_ip32_private * const priv = p->physport->private_data;
1278  struct parport * const physport = p->physport;
1279  unsigned long expire;
1280  unsigned int count;
1281  unsigned int ecr;
1282 
1283  expire = jiffies + physport->cad->timeout;
1284  count = 0;
1285  while (1) {
1286  if (parport_ip32_fifo_wait_break(p, expire))
1287  break;
1288 
1289  /* Check FIFO state. We do nothing when the FIFO is nor full,
1290  * nor empty. It appears that the FIFO full bit is not always
1291  * reliable, the FIFO state is sometimes wrongly reported, and
1292  * the chip gets confused if we give it another byte. */
1293  ecr = parport_ip32_read_econtrol(p);
1294  if (ecr & ECR_F_EMPTY) {
1295  /* FIFO is empty, fill it up */
1296  count = priv->fifo_depth;
1297  break;
1298  }
1299 
1300  /* Wait a moment... */
1301  udelay(FIFO_POLLING_INTERVAL);
1302  } /* while (1) */
1303 
1304  return count;
1305 }
1306 
1315 static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p)
1316 {
1317  static unsigned int lost_interrupt = 0;
1318  struct parport_ip32_private * const priv = p->physport->private_data;
1319  struct parport * const physport = p->physport;
1320  unsigned long nfault_timeout;
1321  unsigned long expire;
1322  unsigned int count;
1323  unsigned int ecr;
1324 
1325  nfault_timeout = min((unsigned long)physport->cad->timeout,
1326  msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
1327  expire = jiffies + physport->cad->timeout;
1328  count = 0;
1329  while (1) {
1330  if (parport_ip32_fifo_wait_break(p, expire))
1331  break;
1332 
1333  /* Initialize mutex used to take interrupts into account */
1334  INIT_COMPLETION(priv->irq_complete);
1335 
1336  /* Enable serviceIntr */
1337  parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1338 
1339  /* Enabling serviceIntr while the FIFO is empty does not
1340  * always generate an interrupt, so check for emptiness
1341  * now. */
1342  ecr = parport_ip32_read_econtrol(p);
1343  if (!(ecr & ECR_F_EMPTY)) {
1344  /* FIFO is not empty: wait for an interrupt or a
1345  * timeout to occur */
1346  wait_for_completion_interruptible_timeout(
1347  &priv->irq_complete, nfault_timeout);
1348  ecr = parport_ip32_read_econtrol(p);
1349  if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR)
1350  && !lost_interrupt) {
1351  printk(KERN_WARNING PPIP32
1352  "%s: lost interrupt in %s\n",
1353  p->name, __func__);
1354  lost_interrupt = 1;
1355  }
1356  }
1357 
1358  /* Disable serviceIntr */
1359  parport_ip32_frob_econtrol(p, ECR_SERVINTR, ECR_SERVINTR);
1360 
1361  /* Check FIFO state */
1362  if (ecr & ECR_F_EMPTY) {
1363  /* FIFO is empty, fill it up */
1364  count = priv->fifo_depth;
1365  break;
1366  } else if (ecr & ECR_SERVINTR) {
1367  /* FIFO is not empty, but we know that can safely push
1368  * writeIntrThreshold bytes into it */
1369  count = priv->writeIntrThreshold;
1370  break;
1371  }
1372  /* FIFO is not empty, and we did not get any interrupt.
1373  * Either it's time to check for nFault, or a signal is
1374  * pending. This is verified in
1375  * parport_ip32_fifo_wait_break(), so we continue the loop. */
1376  } /* while (1) */
1377 
1378  return count;
1379 }
1380 
1392 static size_t parport_ip32_fifo_write_block_pio(struct parport *p,
1393  const void *buf, size_t len)
1394 {
1395  struct parport_ip32_private * const priv = p->physport->private_data;
1396  const u8 *bufp = buf;
1397  size_t left = len;
1398 
1399  priv->irq_mode = PARPORT_IP32_IRQ_HERE;
1400 
1401  while (left > 0) {
1402  unsigned int count;
1403 
1404  count = (p->irq == PARPORT_IRQ_NONE) ?
1405  parport_ip32_fwp_wait_polling(p) :
1406  parport_ip32_fwp_wait_interrupt(p);
1407  if (count == 0)
1408  break; /* Transmission should be stopped */
1409  if (count > left)
1410  count = left;
1411  if (count == 1) {
1412  writeb(*bufp, priv->regs.fifo);
1413  bufp++, left--;
1414  } else {
1415  writesb(priv->regs.fifo, bufp, count);
1416  bufp += count, left -= count;
1417  }
1418  }
1419 
1420  priv->irq_mode = PARPORT_IP32_IRQ_FWD;
1421 
1422  return len - left;
1423 }
1424 
1436 static size_t parport_ip32_fifo_write_block_dma(struct parport *p,
1437  const void *buf, size_t len)
1438 {
1439  struct parport_ip32_private * const priv = p->physport->private_data;
1440  struct parport * const physport = p->physport;
1441  unsigned long nfault_timeout;
1442  unsigned long expire;
1443  size_t written;
1444  unsigned int ecr;
1445 
1446  priv->irq_mode = PARPORT_IP32_IRQ_HERE;
1447 
1448  parport_ip32_dma_start(DMA_TO_DEVICE, (void *)buf, len);
1449  INIT_COMPLETION(priv->irq_complete);
1450  parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN);
1451 
1452  nfault_timeout = min((unsigned long)physport->cad->timeout,
1453  msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
1454  expire = jiffies + physport->cad->timeout;
1455  while (1) {
1456  if (parport_ip32_fifo_wait_break(p, expire))
1457  break;
1458  wait_for_completion_interruptible_timeout(&priv->irq_complete,
1459  nfault_timeout);
1460  ecr = parport_ip32_read_econtrol(p);
1461  if (ecr & ECR_SERVINTR)
1462  break; /* DMA transfer just finished */
1463  }
1464  parport_ip32_dma_stop();
1465  written = len - parport_ip32_dma_get_residue();
1466 
1467  priv->irq_mode = PARPORT_IP32_IRQ_FWD;
1468 
1469  return written;
1470 }
1471 
1481 static size_t parport_ip32_fifo_write_block(struct parport *p,
1482  const void *buf, size_t len)
1483 {
1484  size_t written = 0;
1485  if (len)
1486  /* FIXME - Maybe some threshold value should be set for @len
1487  * under which we revert to PIO mode? */
1488  written = (p->modes & PARPORT_MODE_DMA) ?
1489  parport_ip32_fifo_write_block_dma(p, buf, len) :
1490  parport_ip32_fifo_write_block_pio(p, buf, len);
1491  return written;
1492 }
1493 
1502 static unsigned int parport_ip32_drain_fifo(struct parport *p,
1503  unsigned long timeout)
1504 {
1505  unsigned long expire = jiffies + timeout;
1506  unsigned int polling_interval;
1507  unsigned int counter;
1508 
1509  /* Busy wait for approx. 200us */
1510  for (counter = 0; counter < 40; counter++) {
1511  if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
1512  break;
1513  if (time_after(jiffies, expire))
1514  break;
1515  if (signal_pending(current))
1516  break;
1517  udelay(5);
1518  }
1519  /* Poll slowly. Polling interval starts with 1 millisecond, and is
1520  * increased exponentially until 128. */
1521  polling_interval = 1; /* msecs */
1522  while (!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY)) {
1523  if (time_after_eq(jiffies, expire))
1524  break;
1525  msleep_interruptible(polling_interval);
1526  if (signal_pending(current))
1527  break;
1528  if (polling_interval < 128)
1529  polling_interval *= 2;
1530  }
1531 
1532  return !!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY);
1533 }
1534 
1542 static unsigned int parport_ip32_get_fifo_residue(struct parport *p,
1543  unsigned int mode)
1544 {
1545  struct parport_ip32_private * const priv = p->physport->private_data;
1546  unsigned int residue;
1547  unsigned int cnfga;
1548 
1549  /* FIXME - We are missing one byte if the printer is off-line. I
1550  * don't know how to detect this. It looks that the full bit is not
1551  * always reliable. For the moment, the problem is avoided in most
1552  * cases by testing for BUSY in parport_ip32_compat_write_data().
1553  */
1554  if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
1555  residue = 0;
1556  else {
1557  pr_debug1(PPIP32 "%s: FIFO is stuck\n", p->name);
1558 
1559  /* Stop all transfers.
1560  *
1561  * Microsoft's document instructs to drive DCR_STROBE to 0,
1562  * but it doesn't work (at least in Compatibility mode, not
1563  * tested in ECP mode). Switching directly to Test mode (as
1564  * in parport_pc) is not an option: it does confuse the port,
1565  * ECP service interrupts are no more working after that. A
1566  * hard reset is then needed to revert to a sane state.
1567  *
1568  * Let's hope that the FIFO is really stuck and that the
1569  * peripheral doesn't wake up now.
1570  */
1571  parport_ip32_frob_control(p, DCR_STROBE, 0);
1572 
1573  /* Fill up FIFO */
1574  for (residue = priv->fifo_depth; residue > 0; residue--) {
1575  if (parport_ip32_read_econtrol(p) & ECR_F_FULL)
1576  break;
1577  writeb(0x00, priv->regs.fifo);
1578  }
1579  }
1580  if (residue)
1581  pr_debug1(PPIP32 "%s: %d PWord%s left in FIFO\n",
1582  p->name, residue,
1583  (residue == 1) ? " was" : "s were");
1584 
1585  /* Now reset the FIFO */
1586  parport_ip32_set_mode(p, ECR_MODE_PS2);
1587 
1588  /* Host recovery for ECP mode */
1589  if (mode == ECR_MODE_ECP) {
1590  parport_ip32_data_reverse(p);
1591  parport_ip32_frob_control(p, DCR_nINIT, 0);
1592  if (parport_wait_peripheral(p, DSR_PERROR, 0))
1593  pr_debug1(PPIP32 "%s: PEerror timeout 1 in %s\n",
1594  p->name, __func__);
1595  parport_ip32_frob_control(p, DCR_STROBE, DCR_STROBE);
1596  parport_ip32_frob_control(p, DCR_nINIT, DCR_nINIT);
1597  if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR))
1598  pr_debug1(PPIP32 "%s: PEerror timeout 2 in %s\n",
1599  p->name, __func__);
1600  }
1601 
1602  /* Adjust residue if needed */
1603  parport_ip32_set_mode(p, ECR_MODE_CFG);
1604  cnfga = readb(priv->regs.cnfgA);
1605  if (!(cnfga & CNFGA_nBYTEINTRANS)) {
1606  pr_debug1(PPIP32 "%s: cnfgA contains 0x%02x\n",
1607  p->name, cnfga);
1608  pr_debug1(PPIP32 "%s: Accounting for extra byte\n",
1609  p->name);
1610  residue++;
1611  }
1612 
1613  /* Don't care about partial PWords since we do not support
1614  * PWord != 1 byte. */
1615 
1616  /* Back to forward PS2 mode. */
1617  parport_ip32_set_mode(p, ECR_MODE_PS2);
1618  parport_ip32_data_forward(p);
1619 
1620  return residue;
1621 }
1622 
1630 static size_t parport_ip32_compat_write_data(struct parport *p,
1631  const void *buf, size_t len,
1632  int flags)
1633 {
1634  static unsigned int ready_before = 1;
1635  struct parport_ip32_private * const priv = p->physport->private_data;
1636  struct parport * const physport = p->physport;
1637  size_t written = 0;
1638 
1639  /* Special case: a timeout of zero means we cannot call schedule().
1640  * Also if O_NONBLOCK is set then use the default implementation. */
1641  if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1642  return parport_ieee1284_write_compat(p, buf, len, flags);
1643 
1644  /* Reset FIFO, go in forward mode, and disable ackIntEn */
1645  parport_ip32_set_mode(p, ECR_MODE_PS2);
1646  parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1647  parport_ip32_data_forward(p);
1648  parport_ip32_disable_irq(p);
1649  parport_ip32_set_mode(p, ECR_MODE_PPF);
1650  physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
1651 
1652  /* Wait for peripheral to become ready */
1653  if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
1654  DSR_nBUSY | DSR_nFAULT)) {
1655  /* Avoid to flood the logs */
1656  if (ready_before)
1657  printk(KERN_INFO PPIP32 "%s: not ready in %s\n",
1658  p->name, __func__);
1659  ready_before = 0;
1660  goto stop;
1661  }
1662  ready_before = 1;
1663 
1664  written = parport_ip32_fifo_write_block(p, buf, len);
1665 
1666  /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */
1667  parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
1668 
1669  /* Check for a potential residue */
1670  written -= parport_ip32_get_fifo_residue(p, ECR_MODE_PPF);
1671 
1672  /* Then, wait for BUSY to get low. */
1673  if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
1674  printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
1675  p->name, __func__);
1676 
1677 stop:
1678  /* Reset FIFO */
1679  parport_ip32_set_mode(p, ECR_MODE_PS2);
1680  physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1681 
1682  return written;
1683 }
1684 
1685 /*
1686  * FIXME - Insert here parport_ip32_ecp_read_data().
1687  */
1688 
1696 static size_t parport_ip32_ecp_write_data(struct parport *p,
1697  const void *buf, size_t len,
1698  int flags)
1699 {
1700  static unsigned int ready_before = 1;
1701  struct parport_ip32_private * const priv = p->physport->private_data;
1702  struct parport * const physport = p->physport;
1703  size_t written = 0;
1704 
1705  /* Special case: a timeout of zero means we cannot call schedule().
1706  * Also if O_NONBLOCK is set then use the default implementation. */
1707  if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1708  return parport_ieee1284_ecp_write_data(p, buf, len, flags);
1709 
1710  /* Negotiate to forward mode if necessary. */
1711  if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
1712  /* Event 47: Set nInit high. */
1713  parport_ip32_frob_control(p, DCR_nINIT | DCR_AUTOFD,
1714  DCR_nINIT | DCR_AUTOFD);
1715 
1716  /* Event 49: PError goes high. */
1717  if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) {
1718  printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s",
1719  p->name, __func__);
1720  physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
1721  return 0;
1722  }
1723  }
1724 
1725  /* Reset FIFO, go in forward mode, and disable ackIntEn */
1726  parport_ip32_set_mode(p, ECR_MODE_PS2);
1727  parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1728  parport_ip32_data_forward(p);
1729  parport_ip32_disable_irq(p);
1730  parport_ip32_set_mode(p, ECR_MODE_ECP);
1731  physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
1732 
1733  /* Wait for peripheral to become ready */
1734  if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
1735  DSR_nBUSY | DSR_nFAULT)) {
1736  /* Avoid to flood the logs */
1737  if (ready_before)
1738  printk(KERN_INFO PPIP32 "%s: not ready in %s\n",
1739  p->name, __func__);
1740  ready_before = 0;
1741  goto stop;
1742  }
1743  ready_before = 1;
1744 
1745  written = parport_ip32_fifo_write_block(p, buf, len);
1746 
1747  /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */
1748  parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
1749 
1750  /* Check for a potential residue */
1751  written -= parport_ip32_get_fifo_residue(p, ECR_MODE_ECP);
1752 
1753  /* Then, wait for BUSY to get low. */
1754  if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
1755  printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
1756  p->name, __func__);
1757 
1758 stop:
1759  /* Reset FIFO */
1760  parport_ip32_set_mode(p, ECR_MODE_PS2);
1761  physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1762 
1763  return written;
1764 }
1765 
1766 /*
1767  * FIXME - Insert here parport_ip32_ecp_write_addr().
1768  */
1769 
1770 /*--- Default parport operations ---------------------------------------*/
1771 
1772 static __initdata struct parport_operations parport_ip32_ops = {
1773  .write_data = parport_ip32_write_data,
1774  .read_data = parport_ip32_read_data,
1775 
1776  .write_control = parport_ip32_write_control,
1777  .read_control = parport_ip32_read_control,
1778  .frob_control = parport_ip32_frob_control,
1779 
1780  .read_status = parport_ip32_read_status,
1781 
1782  .enable_irq = parport_ip32_enable_irq,
1783  .disable_irq = parport_ip32_disable_irq,
1784 
1785  .data_forward = parport_ip32_data_forward,
1786  .data_reverse = parport_ip32_data_reverse,
1787 
1788  .init_state = parport_ip32_init_state,
1789  .save_state = parport_ip32_save_state,
1790  .restore_state = parport_ip32_restore_state,
1791 
1792  .epp_write_data = parport_ieee1284_epp_write_data,
1793  .epp_read_data = parport_ieee1284_epp_read_data,
1794  .epp_write_addr = parport_ieee1284_epp_write_addr,
1795  .epp_read_addr = parport_ieee1284_epp_read_addr,
1796 
1797  .ecp_write_data = parport_ieee1284_ecp_write_data,
1798  .ecp_read_data = parport_ieee1284_ecp_read_data,
1799  .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1800 
1801  .compat_write_data = parport_ieee1284_write_compat,
1802  .nibble_read_data = parport_ieee1284_read_nibble,
1803  .byte_read_data = parport_ieee1284_read_byte,
1804 
1805  .owner = THIS_MODULE,
1806 };
1807 
1808 /*--- Device detection -------------------------------------------------*/
1809 
1818 static __init unsigned int parport_ip32_ecp_supported(struct parport *p)
1819 {
1820  struct parport_ip32_private * const priv = p->physport->private_data;
1821  unsigned int ecr;
1822 
1823  ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
1824  writeb(ecr, priv->regs.ecr);
1825  if (readb(priv->regs.ecr) != (ecr | ECR_F_EMPTY))
1826  goto fail;
1827 
1828  pr_probe(p, "Found working ECR register\n");
1829  parport_ip32_set_mode(p, ECR_MODE_SPP);
1830  parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1831  return 1;
1832 
1833 fail:
1834  pr_probe(p, "ECR register not found\n");
1835  return 0;
1836 }
1837 
1846 static __init unsigned int parport_ip32_fifo_supported(struct parport *p)
1847 {
1848  struct parport_ip32_private * const priv = p->physport->private_data;
1849  unsigned int configa, configb;
1850  unsigned int pword;
1851  unsigned int i;
1852 
1853  /* Configuration mode */
1854  parport_ip32_set_mode(p, ECR_MODE_CFG);
1855  configa = readb(priv->regs.cnfgA);
1856  configb = readb(priv->regs.cnfgB);
1857 
1858  /* Find out PWord size */
1859  switch (configa & CNFGA_ID_MASK) {
1860  case CNFGA_ID_8:
1861  pword = 1;
1862  break;
1863  case CNFGA_ID_16:
1864  pword = 2;
1865  break;
1866  case CNFGA_ID_32:
1867  pword = 4;
1868  break;
1869  default:
1870  pr_probe(p, "Unknown implementation ID: 0x%0x\n",
1871  (configa & CNFGA_ID_MASK) >> CNFGA_ID_SHIFT);
1872  goto fail;
1873  break;
1874  }
1875  if (pword != 1) {
1876  pr_probe(p, "Unsupported PWord size: %u\n", pword);
1877  goto fail;
1878  }
1879  priv->pword = pword;
1880  pr_probe(p, "PWord is %u bits\n", 8 * priv->pword);
1881 
1882  /* Check for compression support */
1883  writeb(configb | CNFGB_COMPRESS, priv->regs.cnfgB);
1884  if (readb(priv->regs.cnfgB) & CNFGB_COMPRESS)
1885  pr_probe(p, "Hardware compression detected (unsupported)\n");
1886  writeb(configb & ~CNFGB_COMPRESS, priv->regs.cnfgB);
1887 
1888  /* Reset FIFO and go in test mode (no interrupt, no DMA) */
1889  parport_ip32_set_mode(p, ECR_MODE_TST);
1890 
1891  /* FIFO must be empty now */
1892  if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
1893  pr_probe(p, "FIFO not reset\n");
1894  goto fail;
1895  }
1896 
1897  /* Find out FIFO depth. */
1898  priv->fifo_depth = 0;
1899  for (i = 0; i < 1024; i++) {
1900  if (readb(priv->regs.ecr) & ECR_F_FULL) {
1901  /* FIFO full */
1902  priv->fifo_depth = i;
1903  break;
1904  }
1905  writeb((u8)i, priv->regs.fifo);
1906  }
1907  if (i >= 1024) {
1908  pr_probe(p, "Can't fill FIFO\n");
1909  goto fail;
1910  }
1911  if (!priv->fifo_depth) {
1912  pr_probe(p, "Can't get FIFO depth\n");
1913  goto fail;
1914  }
1915  pr_probe(p, "FIFO is %u PWords deep\n", priv->fifo_depth);
1916 
1917  /* Enable interrupts */
1918  parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1919 
1920  /* Find out writeIntrThreshold: number of PWords we know we can write
1921  * if we get an interrupt. */
1922  priv->writeIntrThreshold = 0;
1923  for (i = 0; i < priv->fifo_depth; i++) {
1924  if (readb(priv->regs.fifo) != (u8)i) {
1925  pr_probe(p, "Invalid data in FIFO\n");
1926  goto fail;
1927  }
1928  if (!priv->writeIntrThreshold
1929  && readb(priv->regs.ecr) & ECR_SERVINTR)
1930  /* writeIntrThreshold reached */
1931  priv->writeIntrThreshold = i + 1;
1932  if (i + 1 < priv->fifo_depth
1933  && readb(priv->regs.ecr) & ECR_F_EMPTY) {
1934  /* FIFO empty before the last byte? */
1935  pr_probe(p, "Data lost in FIFO\n");
1936  goto fail;
1937  }
1938  }
1939  if (!priv->writeIntrThreshold) {
1940  pr_probe(p, "Can't get writeIntrThreshold\n");
1941  goto fail;
1942  }
1943  pr_probe(p, "writeIntrThreshold is %u\n", priv->writeIntrThreshold);
1944 
1945  /* FIFO must be empty now */
1946  if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
1947  pr_probe(p, "Can't empty FIFO\n");
1948  goto fail;
1949  }
1950 
1951  /* Reset FIFO */
1952  parport_ip32_set_mode(p, ECR_MODE_PS2);
1953  /* Set reverse direction (must be in PS2 mode) */
1954  parport_ip32_data_reverse(p);
1955  /* Test FIFO, no interrupt, no DMA */
1956  parport_ip32_set_mode(p, ECR_MODE_TST);
1957  /* Enable interrupts */
1958  parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1959 
1960  /* Find out readIntrThreshold: number of PWords we can read if we get
1961  * an interrupt. */
1962  priv->readIntrThreshold = 0;
1963  for (i = 0; i < priv->fifo_depth; i++) {
1964  writeb(0xaa, priv->regs.fifo);
1965  if (readb(priv->regs.ecr) & ECR_SERVINTR) {
1966  /* readIntrThreshold reached */
1967  priv->readIntrThreshold = i + 1;
1968  break;
1969  }
1970  }
1971  if (!priv->readIntrThreshold) {
1972  pr_probe(p, "Can't get readIntrThreshold\n");
1973  goto fail;
1974  }
1975  pr_probe(p, "readIntrThreshold is %u\n", priv->readIntrThreshold);
1976 
1977  /* Reset ECR */
1978  parport_ip32_set_mode(p, ECR_MODE_PS2);
1979  parport_ip32_data_forward(p);
1980  parport_ip32_set_mode(p, ECR_MODE_SPP);
1981  return 1;
1982 
1983 fail:
1984  priv->fifo_depth = 0;
1985  parport_ip32_set_mode(p, ECR_MODE_SPP);
1986  return 0;
1987 }
1988 
1989 /*--- Initialization code ----------------------------------------------*/
1990 
2002 static void __init
2003 parport_ip32_make_isa_registers(struct parport_ip32_regs *regs,
2004  void __iomem *base, void __iomem *base_hi,
2005  unsigned int regshift)
2006 {
2007 #define r_base(offset) ((u8 __iomem *)base + ((offset) << regshift))
2008 #define r_base_hi(offset) ((u8 __iomem *)base_hi + ((offset) << regshift))
2009  *regs = (struct parport_ip32_regs){
2010  .data = r_base(0),
2011  .dsr = r_base(1),
2012  .dcr = r_base(2),
2013  .eppAddr = r_base(3),
2014  .eppData0 = r_base(4),
2015  .eppData1 = r_base(5),
2016  .eppData2 = r_base(6),
2017  .eppData3 = r_base(7),
2018  .ecpAFifo = r_base(0),
2019  .fifo = r_base_hi(0),
2020  .cnfgA = r_base_hi(0),
2021  .cnfgB = r_base_hi(1),
2022  .ecr = r_base_hi(2)
2023  };
2024 #undef r_base_hi
2025 #undef r_base
2026 }
2027 
2034 static __init struct parport *parport_ip32_probe_port(void)
2035 {
2036  struct parport_ip32_regs regs;
2037  struct parport_ip32_private *priv = NULL;
2038  struct parport_operations *ops = NULL;
2039  struct parport *p = NULL;
2040  int err;
2041 
2042  parport_ip32_make_isa_registers(&regs, &mace->isa.parallel,
2043  &mace->isa.ecp1284, 8 /* regshift */);
2044 
2045  ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2046  priv = kmalloc(sizeof(struct parport_ip32_private), GFP_KERNEL);
2047  p = parport_register_port(0, PARPORT_IRQ_NONE, PARPORT_DMA_NONE, ops);
2048  if (ops == NULL || priv == NULL || p == NULL) {
2049  err = -ENOMEM;
2050  goto fail;
2051  }
2052  p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel);
2053  p->base_hi = MACE_BASE + offsetof(struct sgi_mace, isa.ecp1284);
2054  p->private_data = priv;
2055 
2056  *ops = parport_ip32_ops;
2057  *priv = (struct parport_ip32_private){
2058  .regs = regs,
2059  .dcr_writable = DCR_DIR | DCR_SELECT | DCR_nINIT |
2060  DCR_AUTOFD | DCR_STROBE,
2061  .irq_mode = PARPORT_IP32_IRQ_FWD,
2062  };
2063  init_completion(&priv->irq_complete);
2064 
2065  /* Probe port. */
2066  if (!parport_ip32_ecp_supported(p)) {
2067  err = -ENODEV;
2068  goto fail;
2069  }
2070  parport_ip32_dump_state(p, "begin init", 0);
2071 
2072  /* We found what looks like a working ECR register. Simply assume
2073  * that all modes are correctly supported. Enable basic modes. */
2074  p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2075  p->modes |= PARPORT_MODE_TRISTATE;
2076 
2077  if (!parport_ip32_fifo_supported(p)) {
2078  printk(KERN_WARNING PPIP32
2079  "%s: error: FIFO disabled\n", p->name);
2080  /* Disable hardware modes depending on a working FIFO. */
2081  features &= ~PARPORT_IP32_ENABLE_SPP;
2082  features &= ~PARPORT_IP32_ENABLE_ECP;
2083  /* DMA is not needed if FIFO is not supported. */
2084  features &= ~PARPORT_IP32_ENABLE_DMA;
2085  }
2086 
2087  /* Request IRQ */
2088  if (features & PARPORT_IP32_ENABLE_IRQ) {
2089  int irq = MACEISA_PARALLEL_IRQ;
2090  if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) {
2091  printk(KERN_WARNING PPIP32
2092  "%s: error: IRQ disabled\n", p->name);
2093  /* DMA cannot work without interrupts. */
2094  features &= ~PARPORT_IP32_ENABLE_DMA;
2095  } else {
2096  pr_probe(p, "Interrupt support enabled\n");
2097  p->irq = irq;
2098  priv->dcr_writable |= DCR_IRQ;
2099  }
2100  }
2101 
2102  /* Allocate DMA resources */
2103  if (features & PARPORT_IP32_ENABLE_DMA) {
2104  if (parport_ip32_dma_register())
2105  printk(KERN_WARNING PPIP32
2106  "%s: error: DMA disabled\n", p->name);
2107  else {
2108  pr_probe(p, "DMA support enabled\n");
2109  p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */
2110  p->modes |= PARPORT_MODE_DMA;
2111  }
2112  }
2113 
2114  if (features & PARPORT_IP32_ENABLE_SPP) {
2115  /* Enable compatibility FIFO mode */
2116  p->ops->compat_write_data = parport_ip32_compat_write_data;
2117  p->modes |= PARPORT_MODE_COMPAT;
2118  pr_probe(p, "Hardware support for SPP mode enabled\n");
2119  }
2120  if (features & PARPORT_IP32_ENABLE_EPP) {
2121  /* Set up access functions to use EPP hardware. */
2122  p->ops->epp_read_data = parport_ip32_epp_read_data;
2123  p->ops->epp_write_data = parport_ip32_epp_write_data;
2124  p->ops->epp_read_addr = parport_ip32_epp_read_addr;
2125  p->ops->epp_write_addr = parport_ip32_epp_write_addr;
2126  p->modes |= PARPORT_MODE_EPP;
2127  pr_probe(p, "Hardware support for EPP mode enabled\n");
2128  }
2129  if (features & PARPORT_IP32_ENABLE_ECP) {
2130  /* Enable ECP FIFO mode */
2131  p->ops->ecp_write_data = parport_ip32_ecp_write_data;
2132  /* FIXME - not implemented */
2133 /* p->ops->ecp_read_data = parport_ip32_ecp_read_data; */
2134 /* p->ops->ecp_write_addr = parport_ip32_ecp_write_addr; */
2135  p->modes |= PARPORT_MODE_ECP;
2136  pr_probe(p, "Hardware support for ECP mode enabled\n");
2137  }
2138 
2139  /* Initialize the port with sensible values */
2140  parport_ip32_set_mode(p, ECR_MODE_PS2);
2141  parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
2142  parport_ip32_data_forward(p);
2143  parport_ip32_disable_irq(p);
2144  parport_ip32_write_data(p, 0x00);
2145  parport_ip32_dump_state(p, "end init", 0);
2146 
2147  /* Print out what we found */
2148  printk(KERN_INFO "%s: SGI IP32 at 0x%lx (0x%lx)",
2149  p->name, p->base, p->base_hi);
2150  if (p->irq != PARPORT_IRQ_NONE)
2151  printk(", irq %d", p->irq);
2152  printk(" [");
2153 #define printmode(x) if (p->modes & PARPORT_MODE_##x) \
2154  printk("%s%s", f++ ? "," : "", #x)
2155  {
2156  unsigned int f = 0;
2157  printmode(PCSPP);
2158  printmode(TRISTATE);
2159  printmode(COMPAT);
2160  printmode(EPP);
2161  printmode(ECP);
2162  printmode(DMA);
2163  }
2164 #undef printmode
2165  printk("]\n");
2166 
2167  parport_announce_port(p);
2168  return p;
2169 
2170 fail:
2171  if (p)
2172  parport_put_port(p);
2173  kfree(priv);
2174  kfree(ops);
2175  return ERR_PTR(err);
2176 }
2177 
2185 static __exit void parport_ip32_unregister_port(struct parport *p)
2186 {
2187  struct parport_ip32_private * const priv = p->physport->private_data;
2188  struct parport_operations *ops = p->ops;
2189 
2190  parport_remove_port(p);
2191  if (p->modes & PARPORT_MODE_DMA)
2192  parport_ip32_dma_unregister();
2193  if (p->irq != PARPORT_IRQ_NONE)
2194  free_irq(p->irq, p);
2195  parport_put_port(p);
2196  kfree(priv);
2197  kfree(ops);
2198 }
2199 
2203 static int __init parport_ip32_init(void)
2204 {
2205  pr_info(PPIP32 "SGI IP32 built-in parallel port driver v0.6\n");
2206  this_port = parport_ip32_probe_port();
2207  return IS_ERR(this_port) ? PTR_ERR(this_port) : 0;
2208 }
2209 
2213 static void __exit parport_ip32_exit(void)
2214 {
2215  parport_ip32_unregister_port(this_port);
2216 }
2217 
2218 /*--- Module stuff -----------------------------------------------------*/
2219 
2220 MODULE_AUTHOR("Arnaud Giersch <[email protected]>");
2221 MODULE_DESCRIPTION("SGI IP32 built-in parallel port driver");
2222 MODULE_LICENSE("GPL");
2223 MODULE_VERSION("0.6"); /* update in parport_ip32_init() too */
2224 
2225 module_init(parport_ip32_init);
2226 module_exit(parport_ip32_exit);
2227 
2228 module_param(verbose_probing, bool, S_IRUGO);
2229 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialization");
2230 
2231 module_param(features, uint, S_IRUGO);
2232 MODULE_PARM_DESC(features,
2233  "Bit mask of features to enable"
2234  ", bit 0: IRQ support"
2235  ", bit 1: DMA support"
2236  ", bit 2: hardware SPP mode"
2237  ", bit 3: hardware EPP mode"
2238  ", bit 4: hardware ECP mode");
2239 
2240 /*--- Inform (X)Emacs about preferred coding style ---------------------*/
2241 /*
2242  * Local Variables:
2243  * mode: c
2244  * c-file-style: "linux"
2245  * indent-tabs-mode: t
2246  * tab-width: 8
2247  * fill-column: 78
2248  * ispell-local-dictionary: "american"
2249  * End:
2250  */
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