|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
Go to the source code of this file.
Macros | |
| #define | ATH5K_MAX_TSF_READ 10 |
ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct : The &struct ath5k_hw : beacon interval
This is a workaround for IBSS mode
The need for this function arises from the fact that we have 4 separate HW timer registers (TIMER0 - TIMER3), which are closely related to the next beacon target time (NBTT), and that the HW updates these timers separately based on the current TSF value. The hardware increments each timer by the beacon interval, when the local TSF converted to TU is equal to the value stored in the timer.
The reception of a beacon with the same BSSID can update the local HW TSF at any time - this is something we can't avoid. If the TSF jumps to a time which is later than the time stored in a timer, this timer will not be updated until the TSF in TU wraps around at 16 bit (the size of the timers) and reaches the time which is stored in the timer.
The problem is that these timers are closely related to TIMER0 (NBTT) and that they define a time "window". When the TSF jumps between two timers (e.g. ATIM and NBTT), the one in the past will be left behind (not updated), while the one in the future will be updated every beacon interval. This causes the window to get larger, until the TSF wraps around as described above and the timer which was left behind gets updated again. But - because the beacon interval is usually not an exact divisor of the size of the timers (16 bit), an unwanted "window" between these timers has developed!
This is especially important with the ATIM window, because during the ATIM window only ATIM frames and no data frames are allowed to be sent, which creates transmission pauses after each beacon. This symptom has been described as "ramping ping" because ping times increase linearly for some time and then drop down again. A wrong window on the DMA beacon timer has the same effect, so we check for these two conditions.
Returns true if O.K.
| int ath5k_hw_get_frame_duration | ( | struct ath5k_hw * | ah, |
| enum ieee80211_band | band, | ||
| int | len, | ||
| struct ieee80211_rate * | rate, | ||
| bool | shortpre | ||
| ) |
ath5k_hw_init_beacon_timers() - Initialize beacon timers : The &struct ath5k_hw : Next TBTT : Current beacon interval
This function is used to initialize beacon timers based on current operation mode and settings.
| void ath5k_hw_pcu_init | ( | struct ath5k_hw * | ah, |
| enum nl80211_iftype | op_mode | ||
| ) |
ath5k_hw_pcu_init() - Initialize PCU : The &struct ath5k_hw : One of enum nl80211_iftype : One of enum ath5k_driver_mode
This function is used to initialize PCU by setting current operation mode and various other settings.
ath5k_hw_reset_tsf() - Force a TSF reset : The &struct ath5k_hw
Forces a TSF reset on PCU
ath5k_hw_set_bssid_mask() - Filter out bssids we listen : The &struct ath5k_hw : The BSSID mask to set (array of octets)
BSSID masking is a method used by AR5212 and newer hardware to inform PCU which bits of the interface's MAC address should be looked at when trying to decide which packets to ACK. In station mode and AP mode with a single BSS every bit matters since we lock to only one BSS. In AP mode with multiple BSSes (virtual interfaces) not every bit matters because hw must accept frames for all BSSes and so we tweak some bits of our mac address in order to have multiple BSSes.
For more information check out ../hw.c of the common ath module.
ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class : The &struct ath5k_hw : IEEE 802.11 coverage class number
Sets IFS intervals and ACK/CTS timeouts for given coverage class.
ath5k_hw_set_mcast_filter() - Set multicast filter : The &struct ath5k_hw : Lower 32bits of muticast filter : Higher 16bits of multicast filter
| int ath5k_hw_set_opmode | ( | struct ath5k_hw * | ah, |
| enum nl80211_iftype | op_mode | ||
| ) |
ath5k_hw_start_rx_pcu() - Start RX engine : The &struct ath5k_hw
Starts RX engine on PCU so that hw can process RXed frames (ACK etc).
NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics) : The &struct ath5k_hw
Reads MIB counters from PCU and updates sw statistics. Is called after a MIB interrupt, because one of these counters might have reached their maximum and triggered the MIB interrupt, to let us read and clear the counter.
NOTE: Is called in interrupt context!
1.8.2