#include <linux/types.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/crc32.h>
#include <linux/if_vlan.h>
#include <linux/bitops.h>
#include <linux/workqueue.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <linux/dmi.h>

Data Structures
struct	rx_desc

struct	tx_desc

struct	rhine_private

Macros
#define	pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#define	DRV_NAME "via-rhine"

#define	DRV_VERSION "1.5.0"

#define	DRV_RELDATE "2010-10-09"

#define	RHINE_MSG_DEFAULT (0x0000)

#define	TX_RING_SIZE 16

#define	TX_QUEUE_LEN 10 /* Limit ring entries actually used. */

#define	RX_RING_SIZE 64

#define	TX_TIMEOUT (2*HZ)

#define	PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/

#define	MCAM_SIZE 32

#define	VCAM_SIZE 32

#define	IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)

#define	TXDESC 0x00e08000

#define	BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))\|(x)), (p)); } while (0)

#define	WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))\|(x)), (p)); } while (0)

#define	DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))\|(x)), (p)); } while (0)

#define	BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x))

#define	WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x))

#define	DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x))

#define	BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)

#define	WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)

#define	DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)

#define	BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))\|(x), (p)); } while (0)

#define	WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))\|(x), (p)); } while (0)

#define	DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))\|(x), (p)); } while (0)

#define	RHINE_EVENT_NAPI_RX

#define	RHINE_EVENT_NAPI_TX_ERR

#define	RHINE_EVENT_NAPI_TX (IntrTxDone \| RHINE_EVENT_NAPI_TX_ERR)

#define	RHINE_EVENT_NAPI

#define	RHINE_EVENT_SLOW (IntrPCIErr \| IntrLinkChange)

#define	RHINE_EVENT (RHINE_EVENT_NAPI \| RHINE_EVENT_SLOW)

#define	RHINE_PM_OPS NULL

Enumerations
enum	rhine_revs { VT86C100A = 0x00, VTunknown0 = 0x20, VT6102 = 0x40, VT8231 = 0x50, VT8233 = 0x60, VT8235 = 0x74, VT8237 = 0x78, VTunknown1 = 0x7C, VT6105 = 0x80, VT6105_B0 = 0x83, VT6105L = 0x8A, VT6107 = 0x8C, VTunknown2 = 0x8E, VT6105M = 0x90 }

enum	rhine_quirks { rqWOL = 0x0001, rqForceReset = 0x0002, rq6patterns = 0x0040, rqStatusWBRace = 0x0080, rqRhineI = 0x0100 }

enum	register_offsets { PCIDeviceConfig =0x50040, GenCtrl =0x50070, IntrTimerCtrl =0x50074, IntrClear =0x50080, IntrStatus =0x50084, IntrEnable =0x50088, MIICtrl =0x52000, TxStationAddr =0x50120, EEPROMCtrl =0x51000, GPIOCtrl =0x5008C, TxDescCtrl =0x50090, TxRingPtr =0x50098, HiPriTxRingPtr =0x50094, TxRingHiAddr =0x5009C, TxProducerIdx =0x500A0, TxConsumerIdx =0x500A4, TxThreshold =0x500B0, CompletionHiAddr =0x500B4, TxCompletionAddr =0x500B8, RxCompletionAddr =0x500BC, RxCompletionQ2Addr =0x500C0, CompletionQConsumerIdx =0x500C4, RxDMACtrl =0x500D0, RxDescQCtrl =0x500D4, RxDescQHiAddr =0x500DC, RxDescQAddr =0x500E0, RxDescQIdx =0x500E8, RxDMAStatus =0x500F0, RxFilterMode =0x500F4, TxMode =0x55000, VlanType =0x55064, PerfFilterTable =0x56000, HashTable =0x56100, TxGfpMem =0x58000, RxGfpMem =0x5a000, ChipCmd = 0x00, ChipConfig = 0x04, EECtrl = 0x08, PCIBusCfg = 0x0C, IntrStatus = 0x10, IntrMask = 0x14, IntrEnable = 0x18, IntrHoldoff = 0x1C, TxRingPtr = 0x20, TxConfig = 0x24, RxRingPtr = 0x30, RxConfig = 0x34, ClkRun = 0x3C, WOLCmd = 0x40, PauseCmd = 0x44, RxFilterAddr = 0x48, RxFilterData = 0x4C, BootRomAddr = 0x50, BootRomData = 0x54, SiliconRev = 0x58, StatsCtrl = 0x5C, StatsData = 0x60, RxPktErrs = 0x60, RxMissed = 0x68, RxCRCErrs = 0x64, BasicControl = 0x80, BasicStatus = 0x84, AnegAdv = 0x90, AnegPeer = 0x94, PhyStatus = 0xC0, MIntrCtrl = 0xC4, MIntrStatus = 0xC8, PhyCtrl = 0xE4, PGSEL = 0xCC, PMDCSR = 0xE4, TSTDAT = 0xFC, DSPCFG = 0xF4, SDCFG = 0xF8, StationAddr =0x00, RxConfig =0x06, TxConfig =0x07, ChipCmd =0x08, ChipCmd1 =0x09, TQWake =0x0A, IntrStatus =0x0C, IntrEnable =0x0E, MulticastFilter0 =0x10, MulticastFilter1 =0x14, RxRingPtr =0x18, TxRingPtr =0x1C, GFIFOTest =0x54, MIIPhyAddr =0x6C, MIIStatus =0x6D, PCIBusConfig =0x6E, PCIBusConfig1 =0x6F, MIICmd =0x70, MIIRegAddr =0x71, MIIData =0x72, MACRegEEcsr =0x74, ConfigA =0x78, ConfigB =0x79, ConfigC =0x7A, ConfigD =0x7B, RxMissed =0x7C, RxCRCErrs =0x7E, MiscCmd =0x81, StickyHW =0x83, IntrStatus2 =0x84, CamMask =0x88, CamCon =0x92, CamAddr =0x93, WOLcrSet =0xA0, PwcfgSet =0xA1, WOLcgSet =0xA3, WOLcrClr =0xA4, WOLcrClr1 =0xA6, WOLcgClr =0xA7, PwrcsrSet =0xA8, PwrcsrSet1 =0xA9, PwrcsrClr =0xAC, PwrcsrClr1 =0xAD, TxBufCount = 0x20, RxBufCount = 0x21, OpModes = 0x22, TxQed = 0x23, RxQed = 0x24, MaxBurst = 0x25, RxUnit = 0x60, EthStatus = 0x61, StationAddr0 = 0x67, EthStats = 0x69, LEDCtrl = 0x81 }

enum	backoff_bits { BackOptional =0x01, BackModify =0x02, BackCaptureEffect =0x04, BackRandom =0x08 }

enum	tcr_bits { TCR_PQEN =0x01, TCR_LB0 =0x02, TCR_LB1 =0x04, TCR_OFSET =0x08, TCR_RTGOPT =0x10, TCR_RTFT0 =0x20, TCR_RTFT1 =0x40, TCR_RTSF =0x80 }

enum	camcon_bits { CAMC_CAMEN =0x01, CAMC_VCAMSL =0x02, CAMC_CAMWR =0x04, CAMC_CAMRD =0x08 }

enum	bcr1_bits { BCR1_POT0 =0x01, BCR1_POT1 =0x02, BCR1_POT2 =0x04, BCR1_CTFT0 =0x08, BCR1_CTFT1 =0x10, BCR1_CTSF =0x20, BCR1_TXQNOBK =0x40, BCR1_VIDFR =0x80, BCR1_MED0 =0x40, BCR1_MED1 =0x80 }

enum	intr_status_bits { IntrLinkChange =0xf0000000, IntrStatsMax =0x08000000, IntrAbnormalSummary =0x02000000, IntrGeneralTimer =0x01000000, IntrSoftware =0x800000, IntrRxComplQ1Low =0x400000, IntrTxComplQLow =0x200000, IntrPCI =0x100000, IntrDMAErr =0x080000, IntrTxDataLow =0x040000, IntrRxComplQ2Low =0x020000, IntrRxDescQ1Low =0x010000, IntrNormalSummary =0x8000, IntrTxDone =0x4000, IntrTxDMADone =0x2000, IntrTxEmpty =0x1000, IntrEarlyRxQ2 =0x0800, IntrEarlyRxQ1 =0x0400, IntrRxQ2Done =0x0200, IntrRxQ1Done =0x0100, IntrRxGFPDead =0x80, IntrRxDescQ2Low =0x40, IntrNoTxCsum =0x20, IntrTxBadID =0x10, IntrHiPriTxBadID =0x08, IntrRxGfp =0x04, IntrTxGfp =0x02, IntrPCIPad =0x01, IntrRxDone =IntrRxQ2Done \| IntrRxQ1Done, IntrRxEmpty =IntrRxDescQ1Low \| IntrRxDescQ2Low, IntrNormalMask =0xff00, IntrAbnormalMask =0x3ff00fe, IntrSummary =0x0001, IntrPCIErr =0x0002, IntrMACCtrl =0x0008, IntrTxDone =0x0004, IntrRxDone =0x0010, IntrRxStart =0x0020, IntrDrvRqst =0x0040, StatsMax =0x0080, LinkChange =0x0100, IntrTxDMADone =0x0200, IntrRxDMADone =0x0400, RFCON = 0x00020000, RFCOFF = 0x00010000, LSCStatus = 0x00008000, ANCStatus = 0x00004000, FBE = 0x00002000, FBEMask = 0x00001800, ParityErr = 0x00000000, TargetErr = 0x00001000, MasterErr = 0x00000800, TUNF = 0x00000400, ROVF = 0x00000200, ETI = 0x00000100, ERI = 0x00000080, CNTOVF = 0x00000040, RBU = 0x00000020, TBU = 0x00000010, TI = 0x00000008, RI = 0x00000004, RxErr = 0x00000002, IntrRxDone =0x01, IntrRxPCIFault =0x02, IntrRxPCIErr =0x04, IntrTxDone =0x100, IntrTxPCIFault =0x200, IntrTxPCIErr =0x400, LinkChange =0x10000, NegotiationChange =0x20000, StatsMax =0x40000, IntrRxDone =0x01, IntrRxInvalid =0x02, IntrRxPCIFault =0x04, IntrRxPCIErr =0x08, IntrTxDone =0x10, IntrTxInvalid =0x20, IntrTxPCIFault =0x40, IntrTxPCIErr =0x80, IntrEarlyRx =0x100, IntrWakeup =0x200, IntrRxDone = 0x0001, IntrTxDone = 0x0002, IntrRxErr = 0x0004, IntrTxError = 0x0008, IntrRxEmpty = 0x0020, IntrPCIErr = 0x0040, IntrStatsMax = 0x0080, IntrRxEarly = 0x0100, IntrTxUnderrun = 0x0210, IntrRxOverflow = 0x0400, IntrRxDropped = 0x0800, IntrRxNoBuf = 0x1000, IntrTxAborted = 0x2000, IntrLinkChange = 0x4000, IntrRxWakeUp = 0x8000, IntrTxDescRace = 0x080000, IntrNormalSummary = IntrRxDone \| IntrTxDone, IntrTxErrSummary }

enum	wol_bits { WOLucast = 0x10, WOLmagic = 0x20, WOLbmcast = 0x30, WOLlnkon = 0x40, WOLlnkoff = 0x80 }

enum	rx_status_bits { RxOK =0x8000, RxWholePkt =0x0300, RxErr =0x008F }

enum	desc_status_bits { DescOwned = 0x80000000, DescWholePkt = 0x60000000, DescEndPkt = 0x40000000, DescStartPkt = 0x20000000, DescEndRing = 0x02000000, DescUseLink = 0x01000000, RxDescErrorSummary = 0x8000, RxDescCRCError = 0x0002, RxDescCollisionSeen = 0x0040, RxDescFrameTooLong = 0x0080, RxDescRunt = 0x0800, RxDescDescErr = 0x4000, RxWholePkt = 0x00000300, RxLengthOver2047 = 0x38000010, DescOwn =0x8000, DescEndPacket =0x4000, DescEndRing =0x2000, LastFrag =0x80000000, DescIntrOnTx =0x8000, DescIntrOnDMADone =0x80000000, DisableAlign = 0x00000001, DescOwn =0x80000000, DescMore =0x40000000, DescIntr =0x20000000, DescNoCRC =0x10000000, DescPktOK =0x08000000, DescSizeMask =0xfff, DescTxAbort =0x04000000, DescTxFIFO =0x02000000, DescTxCarrier =0x01000000, DescTxDefer =0x00800000, DescTxExcDefer =0x00400000, DescTxOOWCol =0x00200000, DescTxExcColl =0x00100000, DescTxCollCount =0x000f0000, DescRxAbort =0x04000000, DescRxOver =0x02000000, DescRxDest =0x01800000, DescRxLong =0x00400000, DescRxRunt =0x00200000, DescRxInvalid =0x00100000, DescRxCRC =0x00080000, DescRxAlign =0x00040000, DescRxLoop =0x00020000, DesRxColl =0x00010000, DescOwn =0x80000000, DescEndPacket =0x40000000, DescEndRing =0x20000000, DescIntr =0x10000000, RX_EOP =0x0040, DescOwn =0x8000, DescOwn =0x80000000 }

enum	desc_length_bits { DescTag =0x00010000 }

enum	chip_cmd_bits { CmdInit =0x01, CmdStart =0x02, CmdStop =0x04, CmdRxOn =0x08, CmdTxOn =0x10, Cmd1TxDemand =0x20, CmdRxDemand =0x40, Cmd1EarlyRx =0x01, Cmd1EarlyTx =0x02, Cmd1FDuplex =0x04, Cmd1NoTxPoll =0x08, Cmd1Reset =0x80 }

Functions
	MODULE_AUTHOR ("Donald Becker <[email protected]>")

	MODULE_DESCRIPTION ("VIA Rhine PCI Fast Ethernet driver")

	MODULE_LICENSE ("GPL")

	module_param (debug, int, 0)

	module_param (rx_copybreak, int, 0)

	module_param (avoid_D3, bool, 0)

	MODULE_PARM_DESC (debug,"VIA Rhine debug message flags")

	MODULE_PARM_DESC (rx_copybreak,"VIA Rhine copy breakpoint for copy-only-tiny-frames")

	MODULE_PARM_DESC (avoid_D3,"Avoid power state D3 (work-around for broken BIOSes)")

	MODULE_DEVICE_TABLE (pci, rhine_pci_tbl)

	module_init (rhine_init)

	module_exit (rhine_cleanup)

Macro Definition Documentation

#define BYTE_REG_BITS_IS_ON	(	x,
		p
	)	(ioread8((p)) & (x))

Definition at line 473 of file via-rhine.c.

#define BYTE_REG_BITS_OFF	(	x,
		p
	)	do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)

Definition at line 477 of file via-rhine.c.

#define BYTE_REG_BITS_ON	(	x,
		p
	)	do { iowrite8((ioread8((p))\|(x)), (p)); } while (0)

Definition at line 469 of file via-rhine.c.

#define BYTE_REG_BITS_SET	(	x,
		m,
		p
	)	do { iowrite8((ioread8((p)) & (~(m)))\|(x), (p)); } while (0)

Definition at line 481 of file via-rhine.c.

#define DRV_NAME "via-rhine"

Definition at line 34 of file via-rhine.c.

#define DRV_RELDATE "2010-10-09"

Definition at line 36 of file via-rhine.c.

#define DRV_VERSION "1.5.0"

Definition at line 35 of file via-rhine.c.

#define DWORD_REG_BITS_IS_ON	(	x,
		p
	)	(ioread32((p)) & (x))

Definition at line 475 of file via-rhine.c.

#define DWORD_REG_BITS_OFF	(	x,
		p
	)	do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)

Definition at line 479 of file via-rhine.c.

#define DWORD_REG_BITS_ON	(	x,
		p
	)	do { iowrite32((ioread32((p))\|(x)), (p)); } while (0)

Definition at line 471 of file via-rhine.c.

#define DWORD_REG_BITS_SET	(	x,
		m,
		p
	)	do { iowrite32((ioread32((p)) & (~(m)))\|(x), (p)); } while (0)

Definition at line 483 of file via-rhine.c.

#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)

Definition at line 271 of file via-rhine.c.

#define MCAM_SIZE 32

Definition at line 137 of file via-rhine.c.

#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/

Definition at line 86 of file via-rhine.c.

#define pr_fmt ( fmt ) KBUILD_MODNAME ": " fmt

Definition at line 32 of file via-rhine.c.

#define RHINE_EVENT (RHINE_EVENT_NAPI | RHINE_EVENT_SLOW)

Definition at line 776 of file via-rhine.c.

#define RHINE_EVENT_NAPI

Value:

(RHINE_EVENT_NAPI_RX | \
                 RHINE_EVENT_NAPI_TX | \
                 IntrStatsMax)

Definition at line 772 of file via-rhine.c.

#define RHINE_EVENT_NAPI_RX

Value:

(IntrRxDone | \
                 IntrRxErr | \
                 IntrRxEmpty | \
                 IntrRxOverflow | \
                 IntrRxDropped | \
                 IntrRxNoBuf | \
                 IntrRxWakeUp)

Definition at line 758 of file via-rhine.c.

#define RHINE_EVENT_NAPI_TX (IntrTxDone | RHINE_EVENT_NAPI_TX_ERR)

Definition at line 770 of file via-rhine.c.

#define RHINE_EVENT_NAPI_TX_ERR

Value:

(IntrTxError | \
                 IntrTxAborted | \
                 IntrTxUnderrun | \
                 IntrTxDescRace)

Definition at line 766 of file via-rhine.c.

#define RHINE_EVENT_SLOW (IntrPCIErr | IntrLinkChange)

Definition at line 775 of file via-rhine.c.

#define RHINE_MSG_DEFAULT (0x0000)

Definition at line 43 of file via-rhine.c.

#define RHINE_PM_OPS NULL

Definition at line 2354 of file via-rhine.c.

#define RX_RING_SIZE 64

Definition at line 79 of file via-rhine.c.

#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */

Definition at line 78 of file via-rhine.c.

#define TX_RING_SIZE 16

Definition at line 77 of file via-rhine.c.

#define TX_TIMEOUT (2*HZ)

Definition at line 84 of file via-rhine.c.

#define TXDESC 0x00e08000

Definition at line 396 of file via-rhine.c.

#define VCAM_SIZE 32

Definition at line 138 of file via-rhine.c.

#define WORD_REG_BITS_IS_ON	(	x,
		p
	)	(ioread16((p)) & (x))

Definition at line 474 of file via-rhine.c.

#define WORD_REG_BITS_OFF	(	x,
		p
	)	do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)

Definition at line 478 of file via-rhine.c.

#define WORD_REG_BITS_ON	(	x,
		p
	)	do { iowrite16((ioread16((p))\|(x)), (p)); } while (0)

Definition at line 470 of file via-rhine.c.

#define WORD_REG_BITS_SET	(	x,
		m,
		p
	)	do { iowrite16((ioread16((p)) & (~(m)))\|(x), (p)); } while (0)

Definition at line 482 of file via-rhine.c.

Enumeration Type Documentation

enum backoff_bits

Enumerator:

BackOptional
BackModify
BackCaptureEffect
BackRandom

Definition at line 302 of file via-rhine.c.

enum bcr1_bits

Enumerator:

BCR1_POT0
BCR1_POT1
BCR1_POT2
BCR1_CTFT0
BCR1_CTFT1
BCR1_CTSF
BCR1_TXQNOBK
BCR1_VIDFR
BCR1_MED0
BCR1_MED1

Definition at line 328 of file via-rhine.c.

enum camcon_bits

Enumerator:

CAMC_CAMEN
CAMC_VCAMSL
CAMC_CAMWR
CAMC_CAMRD

Definition at line 320 of file via-rhine.c.

enum chip_cmd_bits

Enumerator:

CmdInit
CmdStart
CmdStop
CmdRxOn
CmdTxOn
Cmd1TxDemand
CmdRxDemand
Cmd1EarlyRx
Cmd1EarlyTx
Cmd1FDuplex
Cmd1NoTxPoll
Cmd1Reset

Definition at line 413 of file via-rhine.c.

enum desc_length_bits

Enumerator:

DescTag

Definition at line 408 of file via-rhine.c.

enum desc_status_bits

Enumerator:

DescOwned
DescWholePkt
DescEndPkt
DescStartPkt
DescEndRing
DescUseLink
RxDescErrorSummary
RxDescCRCError
RxDescCollisionSeen
RxDescFrameTooLong
RxDescRunt
RxDescDescErr
RxWholePkt
RxLengthOver2047
DescOwn
DescEndPacket
DescEndRing
LastFrag
DescIntrOnTx
DescIntrOnDMADone
DisableAlign
DescOwn
DescMore
DescIntr
DescNoCRC
DescPktOK
DescSizeMask
DescTxAbort
DescTxFIFO
DescTxCarrier
DescTxDefer
DescTxExcDefer
DescTxOOWCol
DescTxExcColl
DescTxCollCount
DescRxAbort
DescRxOver
DescRxDest
DescRxLong
DescRxRunt
DescRxInvalid
DescRxCRC
DescRxAlign
DescRxLoop
DesRxColl
DescOwn
DescEndPacket
DescEndRing
DescIntr
RX_EOP
DescOwn
DescOwn

Definition at line 403 of file via-rhine.c.

enum intr_status_bits

Enumerator:

IntrLinkChange
IntrStatsMax
IntrAbnormalSummary
IntrGeneralTimer
IntrSoftware
IntrRxComplQ1Low
IntrTxComplQLow
IntrPCI
IntrDMAErr
IntrTxDataLow
IntrRxComplQ2Low
IntrRxDescQ1Low
IntrNormalSummary
IntrTxDone
IntrTxDMADone
IntrTxEmpty
IntrEarlyRxQ2
IntrEarlyRxQ1
IntrRxQ2Done
IntrRxQ1Done
IntrRxGFPDead
IntrRxDescQ2Low
IntrNoTxCsum
IntrTxBadID
IntrHiPriTxBadID
IntrRxGfp
IntrTxGfp
IntrPCIPad
IntrRxDone
IntrRxEmpty
IntrNormalMask
IntrAbnormalMask
IntrSummary
IntrPCIErr
IntrMACCtrl
IntrTxDone
IntrRxDone
IntrRxStart
IntrDrvRqst
StatsMax
LinkChange
IntrTxDMADone
IntrRxDMADone
RFCON
RFCOFF
LSCStatus
ANCStatus
FBE
FBEMask
ParityErr
TargetErr
MasterErr
TUNF
ROVF
ETI
ERI
CNTOVF
RBU
TBU
TI
RI
RxErr
IntrRxDone
IntrRxPCIFault
IntrRxPCIErr
IntrTxDone
IntrTxPCIFault
IntrTxPCIErr
LinkChange
NegotiationChange
StatsMax
IntrRxDone
IntrRxInvalid
IntrRxPCIFault
IntrRxPCIErr
IntrTxDone
IntrTxInvalid
IntrTxPCIFault
IntrTxPCIErr
IntrEarlyRx
IntrWakeup
IntrRxDone
IntrTxDone
IntrRxErr
IntrTxError
IntrRxEmpty
IntrPCIErr
IntrStatsMax
IntrRxEarly
IntrTxUnderrun
IntrRxOverflow
IntrRxDropped
IntrRxNoBuf
IntrTxAborted
IntrLinkChange
IntrRxWakeUp
IntrTxDescRace
IntrNormalSummary
IntrTxErrSummary

Definition at line 350 of file via-rhine.c.

enum register_offsets

Enumerator:

PCIDeviceConfig
GenCtrl
IntrTimerCtrl
IntrClear
IntrStatus
IntrEnable
MIICtrl
TxStationAddr
EEPROMCtrl
GPIOCtrl
TxDescCtrl
TxRingPtr
HiPriTxRingPtr
TxRingHiAddr
TxProducerIdx
TxConsumerIdx
TxThreshold
CompletionHiAddr
TxCompletionAddr
RxCompletionAddr
RxCompletionQ2Addr
CompletionQConsumerIdx
RxDMACtrl
RxDescQCtrl
RxDescQHiAddr
RxDescQAddr
RxDescQIdx
RxDMAStatus
RxFilterMode
TxMode
VlanType
PerfFilterTable
HashTable
TxGfpMem
RxGfpMem
ChipCmd
ChipConfig
EECtrl
PCIBusCfg
IntrStatus
IntrMask
IntrEnable
IntrHoldoff
TxRingPtr
TxConfig
RxRingPtr
RxConfig
ClkRun
WOLCmd
PauseCmd
RxFilterAddr
RxFilterData
BootRomAddr
BootRomData
SiliconRev
StatsCtrl
StatsData
RxPktErrs
RxMissed
RxCRCErrs
BasicControl
BasicStatus
AnegAdv
AnegPeer
PhyStatus
MIntrCtrl
MIntrStatus
PhyCtrl
PGSEL
PMDCSR
TSTDAT
DSPCFG
SDCFG
StationAddr
RxConfig
TxConfig
ChipCmd
ChipCmd1
TQWake
IntrStatus
IntrEnable
MulticastFilter0
MulticastFilter1
RxRingPtr
TxRingPtr
GFIFOTest
MIIPhyAddr
MIIStatus
PCIBusConfig
PCIBusConfig1
MIICmd
MIIRegAddr
MIIData
MACRegEEcsr
ConfigA
ConfigB
ConfigC
ConfigD
RxMissed
RxCRCErrs
MiscCmd
StickyHW
IntrStatus2
CamMask
CamCon
CamAddr
WOLcrSet
PwcfgSet
WOLcgSet
WOLcrClr
WOLcrClr1
WOLcgClr
PwrcsrSet
PwrcsrSet1
PwrcsrClr
PwrcsrClr1
TxBufCount
RxBufCount
OpModes
TxQed
RxQed
MaxBurst
RxUnit
EthStatus
StationAddr0
EthStats
LEDCtrl

Definition at line 284 of file via-rhine.c.

enum rhine_quirks

Enumerator:

rqWOL
rqForceReset
rq6patterns
rqStatusWBRace
rqRhineI

Definition at line 257 of file via-rhine.c.

enum rhine_revs

Enumerator:

VT86C100A
VTunknown0
VT6102
VT8231
VT8233
VT8235
VT8237
VTunknown1
VT6105
VT6105_B0
VT6105L
VT6107
VTunknown2
VT6105M

Definition at line 240 of file via-rhine.c.

enum rx_status_bits

Enumerator:

RxOK
RxWholePkt
RxErr

Definition at line 398 of file via-rhine.c.

enum tcr_bits

Enumerator:

TCR_PQEN
TCR_LB0
TCR_LB1
TCR_OFSET
TCR_RTGOPT
TCR_RTFT0
TCR_RTFT1
TCR_RTSF

Definition at line 308 of file via-rhine.c.

enum wol_bits

Enumerator:

WOLucast
WOLmagic
WOLbmcast
WOLlnkon
WOLlnkoff

Definition at line 373 of file via-rhine.c.

Function Documentation

MODULE_AUTHOR ( "Donald Becker <[email protected]>" )

MODULE_DESCRIPTION ( "VIA Rhine PCI Fast Ethernet driver" )

MODULE_DEVICE_TABLE	(	pci	,
		rhine_pci_tbl
	)

module_exit ( rhine_cleanup )

module_init ( rhine_init )

MODULE_LICENSE ( "GPL" )

module_param	(	debug	,
		int	,
		0
	)

module_param	(	rx_copybreak	,
		int	,
		0
	)

module_param	(	avoid_D3	,
		bool	,
		0
	)

MODULE_PARM_DESC	(	debug	,
		"VIA Rhine debug message flags"
	)

MODULE_PARM_DESC	(	rx_copybreak	,
		"VIA Rhine copy breakpoint for copy-only-tiny-frames"
	)

MODULE_PARM_DESC	(	avoid_D3	,
		"Avoid power state D3 (work-around for broken BIOSes)"
	)

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation